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target/efm32: general formatting/style cleanup 

Signed-off-by: Rafael Silva <perigoso@riseup.net>
This commit is contained in:
Rafael Silva 2022-07-07 18:37:40 +01:00 committed by Rachel Mant
parent 018fc517a1
commit 42d36d9d10
1 changed files with 322 additions and 379 deletions
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163
src/target/efm32.c
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@ -31,7 +31,6 @@
*/ */
/* Refer to the family reference manuals: /* Refer to the family reference manuals:
*
* *
* Also refer to AN0062 "Programming Internal Flash Over the Serial Wire Debug Interface" * Also refer to AN0062 "Programming Internal Flash Over the Serial Wire Debug Interface"
* http://www.silabs.com/Support%20Documents/TechnicalDocs/an0062.pdf * http://www.silabs.com/Support%20Documents/TechnicalDocs/an0062.pdf
@ -63,11 +62,9 @@ const struct command_s efm32_cmd_list[] = {
{"serial", (cmd_handler)efm32_cmd_serial, "Prints unique number"}, {"serial", (cmd_handler)efm32_cmd_serial, "Prints unique number"},
{"efm_info", (cmd_handler)efm32_cmd_efm_info, "Prints information about the device"}, {"efm_info", (cmd_handler)efm32_cmd_efm_info, "Prints information about the device"},
{"bootloader", (cmd_handler)efm32_cmd_bootloader, "Bootloader status in CLW0"}, {"bootloader", (cmd_handler)efm32_cmd_bootloader, "Bootloader status in CLW0"},
{NULL, NULL, NULL} {NULL, NULL, NULL},
}; };
/* -------------------------------------------------------------------------- */ /* -------------------------------------------------------------------------- */
/* Memory System Controller (MSC) Registers */ /* Memory System Controller (MSC) Registers */
/* -------------------------------------------------------------------------- */ /* -------------------------------------------------------------------------- */
@ -97,7 +94,6 @@ const struct command_s efm32_cmd_list[] = {
#define EFM32_MSC_STATUS_INVADDR (1 << 2) #define EFM32_MSC_STATUS_INVADDR (1 << 2)
#define EFM32_MSC_STATUS_WDATAREADY (1 << 3) #define EFM32_MSC_STATUS_WDATAREADY (1 << 3)
/* -------------------------------------------------------------------------- */ /* -------------------------------------------------------------------------- */
/* Flash Infomation Area */ /* Flash Infomation Area */
/* -------------------------------------------------------------------------- */ /* -------------------------------------------------------------------------- */
@ -108,7 +104,6 @@ const struct command_s efm32_cmd_list[] = {
#define EFM32_V1_DI (EFM32_INFO + 0x8000) #define EFM32_V1_DI (EFM32_INFO + 0x8000)
#define EFM32_V2_DI (EFM32_INFO + 0x81B0) #define EFM32_V2_DI (EFM32_INFO + 0x81B0)
/* -------------------------------------------------------------------------- */ /* -------------------------------------------------------------------------- */
/* Lock Bits (LB) */ /* Lock Bits (LB) */
/* -------------------------------------------------------------------------- */ /* -------------------------------------------------------------------------- */
@ -122,7 +117,7 @@ const struct command_s efm32_cmd_list[] = {
#define EFM32_CLW0_PINRESETSOFT (1 << 2) #define EFM32_CLW0_PINRESETSOFT (1 << 2)
/* -------------------------------------------------------------------------- */ /* -------------------------------------------------------------------------- */
/* Device Information (DI) Area - Version 1 V1 */ /* Device Information (DI) Area - Version 1 */
/* -------------------------------------------------------------------------- */ /* -------------------------------------------------------------------------- */
#define EFM32_V1_DI_CMU_LFRCOCTRL (EFM32_V1_DI + 0x020) #define EFM32_V1_DI_CMU_LFRCOCTRL (EFM32_V1_DI + 0x020)
@ -183,7 +178,7 @@ const struct command_s efm32_cmd_list[] = {
#define EFM32_V1_DI_EUI_SILABS 0x000b57 #define EFM32_V1_DI_EUI_SILABS 0x000b57
/* -------------------------------------------------------------------------- */ /* -------------------------------------------------------------------------- */
/* Device Information (DI) Area - Version 2 V2 */ /* Device Information (DI) Area - Version 2 */
/* -------------------------------------------------------------------------- */ /* -------------------------------------------------------------------------- */
#define EFM32_V2_DI_CAL (EFM32_V2_DI + 0x000) /* CRC of DI-page and calibration temperature */ #define EFM32_V2_DI_CAL (EFM32_V2_DI + 0x000) /* CRC of DI-page and calibration temperature */
@ -338,7 +333,6 @@ efm32_device_t const efm32_devices[] = {
{63, true, 2048, "EFR32FG14V", 0x400e0000, 2048, 16384, "Flex Gecko"}, {63, true, 2048, "EFR32FG14V", 0x400e0000, 2048, 16384, "Flex Gecko"},
}; };
/* miscchip */ /* miscchip */
typedef struct efm32_v2_di_miscchip_t { typedef struct efm32_v2_di_miscchip_t {
uint8_t pincount; uint8_t pincount;
@ -369,16 +363,14 @@ efm32_v2_di_tempgrade_t const efm32_v2_di_tempgrades[] = {
{0, "-40 to 85degC"}, {0, "-40 to 85degC"},
{1, "-40 to 125degC"}, {1, "-40 to 125degC"},
{2, "-40 to 105degC"}, {2, "-40 to 105degC"},
{3, "0 to 70degC"} {3, "0 to 70degC"},
}; };
/* -------------------------------------------------------------------------- */ /* -------------------------------------------------------------------------- */
/* Helper functions - Version 1 V1 */ /* Helper functions */
/* -------------------------------------------------------------------------- */ /* -------------------------------------------------------------------------- */
/** /* Reads the EFM32 Extended Unique Identifier EUI64 (V1) */
* Reads the EFM32 Extended Unique Identifier EUI64 (V1)
*/
static uint64_t efm32_v1_read_eui64(target *t) static uint64_t efm32_v1_read_eui64(target *t)
{ {
uint64_t eui; uint64_t eui;
@ -389,23 +381,7 @@ static uint64_t efm32_v1_read_eui64(target *t)
return eui; return eui;
} }
#if 0 /* Reads the Unique Number (DI V2 only) */
/**
* Reads the EFM32 Extended Unique Identifier EUI48 (V2)
*/
static uint64_t efm32_v2_read_eui48(target *t)
{
uint64_t eui;
eui = (uint64_t)target_mem_read32(t, EFM32_V2_DI_EUI48H) << 32;
eui |= (uint64_t)target_mem_read32(t, EFM32_V2_DI_EUI48L) << 0;
return eui;
}
#endif
/**
* Reads the Unique Number (DI V2 only)
*/
static uint64_t efm32_v2_read_unique(target *t, uint8_t di_version) static uint64_t efm32_v2_read_unique(target *t, uint8_t di_version)
{ {
uint64_t unique; uint64_t unique;
@ -419,9 +395,7 @@ static uint64_t efm32_v2_read_unique(target *t, uint8_t di_version)
} }
} }
/** /* Reads the EFM32 flash size in kiB */
* Reads the EFM32 flash size in kiB
*/
static uint16_t efm32_read_flash_size(target *t, uint8_t di_version) static uint16_t efm32_read_flash_size(target *t, uint8_t di_version)
{ {
switch (di_version) { switch (di_version) {
@ -433,9 +407,8 @@ static uint16_t efm32_read_flash_size(target *t, uint8_t di_version)
return 0; return 0;
} }
} }
/**
* Reads the EFM32 RAM size in kiB /* Reads the EFM32 RAM size in kiB */
*/
static uint16_t efm32_read_ram_size(target *t, uint8_t di_version) static uint16_t efm32_read_ram_size(target *t, uint8_t di_version)
{ {
switch (di_version) { switch (di_version) {
@ -447,9 +420,10 @@ static uint16_t efm32_read_ram_size(target *t, uint8_t di_version)
return 0; return 0;
} }
} }
/** /**
* Reads the EFM32 reported flash page size in bytes. Note: This * Reads the EFM32 reported flash page size in bytes. Note: This
* driver ignores this value, and uses a conservative hard-coded * driver ignores this value and uses a conservative hard-coded
* value. There are errata on the value reported by the EFM32 * value. There are errata on the value reported by the EFM32
* eg. DI_101 * eg. DI_101
*/ */
@ -471,10 +445,7 @@ static uint32_t efm32_flash_page_size(target *t, uint8_t di_version)
return (1 << (mem_info_page_size + 10)); /* uint8_t ovf here */ return (1 << (mem_info_page_size + 10)); /* uint8_t ovf here */
} }
/* Reads the EFM32 Part Number */
/**
* Reads the EFM32 Part Number
*/
static uint16_t efm32_read_part_number(target *t, uint8_t di_version) static uint16_t efm32_read_part_number(target *t, uint8_t di_version)
{ {
switch (di_version) { switch (di_version) {
@ -486,9 +457,8 @@ static uint16_t efm32_read_part_number(target *t, uint8_t di_version)
return 0; return 0;
} }
} }
/**
* Reads the EFM32 Part Family /* Reads the EFM32 Part Family */
*/
static uint8_t efm32_read_part_family(target *t, uint8_t di_version) static uint8_t efm32_read_part_family(target *t, uint8_t di_version)
{ {
switch (di_version) { switch (di_version) {
@ -500,9 +470,8 @@ static uint8_t efm32_read_part_family(target *t, uint8_t di_version)
return 0; return 0;
} }
} }
/**
* Reads the EFM32 Radio part number (EZR parts with V1 DI only) /* Reads the EFM32 Radio part number (EZR parts with V1 DI only) */
*/
static uint16_t efm32_read_radio_part_number(target *t, uint8_t di_version) static uint16_t efm32_read_radio_part_number(target *t, uint8_t di_version)
{ {
switch (di_version) { switch (di_version) {
@ -513,9 +482,7 @@ static uint16_t efm32_read_radio_part_number(target *t, uint8_t di_version)
} }
} }
/** /* Reads the EFM32 Misc. Chip definitions */
* Reads the EFM32 Misc. Chip definitions
*/
static efm32_v2_di_miscchip_t efm32_v2_read_miscchip(target *t, uint8_t di_version) static efm32_v2_di_miscchip_t efm32_v2_read_miscchip(target *t, uint8_t di_version)
{ {
uint32_t meminfo; uint32_t meminfo;
@ -537,9 +504,7 @@ static efm32_v2_di_miscchip_t efm32_v2_read_miscchip(target *t, uint8_t di_versi
/* Shared Functions */ /* Shared Functions */
/* -------------------------------------------------------------------------- */ /* -------------------------------------------------------------------------- */
static void efm32_add_flash(target *t, target_addr addr, size_t length, size_t page_size)
static void efm32_add_flash(target *t, target_addr addr, size_t length,
size_t page_size)
{ {
struct target_flash *f = calloc(1, sizeof(*f)); struct target_flash *f = calloc(1, sizeof(*f));
if (!f) { /* calloc failed: heap exhaustion */ if (!f) { /* calloc failed: heap exhaustion */
@ -556,9 +521,7 @@ static void efm32_add_flash(target *t, target_addr addr, size_t length,
target_add_flash(t, f); target_add_flash(t, f);
} }
/** /* Lookup device */
* Lookup device
*/
static size_t efm32_lookup_device_index(target *t, uint8_t di_version) static size_t efm32_lookup_device_index(target *t, uint8_t di_version)
{ {
uint8_t part_family = efm32_read_part_family(t, di_version); uint8_t part_family = efm32_read_part_family(t, di_version);
@ -569,8 +532,9 @@ static size_t efm32_lookup_device_index(target *t, uint8_t di_version)
return i; return i;
} }
} }
/* Unknown family */ /* Unknown family */
return 9999; return UINT32_MAX;
} }
static efm32_device_t const *efm32_get_device(size_t index) static efm32_device_t const *efm32_get_device(size_t index)
@ -581,9 +545,7 @@ static efm32_device_t const * efm32_get_device(size_t index)
return &efm32_devices[index]; return &efm32_devices[index];
} }
/** /* Probe */
* Probe
*/
struct efm32_priv_s { struct efm32_priv_s {
char efm32_variant_string[60]; char efm32_variant_string[60];
}; };
@ -605,7 +567,7 @@ bool efm32_probe(target *t)
return false; return false;
} }
/* Check the OUI in the EUI is silabs or energymicro. /* Check if the OUI in the EUI is silabs or energymicro.
* Use this to identify the Device Identification (DI) version */ * Use this to identify the Device Identification (DI) version */
uint64_t oui24 = ((efm32_v1_read_eui64(t) >> 40) & 0xFFFFFF); uint64_t oui24 = ((efm32_v1_read_eui64(t) >> 40) & 0xFFFFFF);
if (oui24 == EFM32_V1_DI_EUI_SILABS) { if (oui24 == EFM32_V1_DI_EUI_SILABS) {
@ -643,15 +605,14 @@ bool efm32_probe(target *t)
struct efm32_priv_s *priv_storage = calloc(1, sizeof(*priv_storage)); struct efm32_priv_s *priv_storage = calloc(1, sizeof(*priv_storage));
t->target_storage = (void *)priv_storage; t->target_storage = (void *)priv_storage;
snprintf(priv_storage->efm32_variant_string, snprintf(priv_storage->efm32_variant_string, sizeof(priv_storage->efm32_variant_string), "%c\b%c\b%s %d F%d %s",
sizeof(priv_storage->efm32_variant_string), "%c\b%c\b%s %d F%d %s", di_version + 48, (uint8_t)device_index + 32, device->name, part_number, flash_kib, device->description);
di_version + 48, (uint8_t)device_index + 32,
device->name, part_number, flash_kib, device->description);
/* Setup Target */ /* Setup Target */
t->target_options |= CORTEXM_TOPT_INHIBIT_NRST; t->target_options |= CORTEXM_TOPT_INHIBIT_NRST;
t->driver = priv_storage->efm32_variant_string; t->driver = priv_storage->efm32_variant_string;
tc_printf(t, "flash size %d page size %d\n", flash_size, flash_page_size); tc_printf(t, "flash size %d page size %d\n", flash_size, flash_page_size);
target_add_ram(t, SRAM_BASE, ram_size); target_add_ram(t, SRAM_BASE, ram_size);
efm32_add_flash(t, 0x00000000, flash_size, flash_page_size); efm32_add_flash(t, 0x00000000, flash_size, flash_page_size);
if (device->user_data_size) { /* optional User Data (UD) section */ if (device->user_data_size) { /* optional User Data (UD) section */
@ -660,14 +621,13 @@ bool efm32_probe(target *t)
if (device->bootloader_size) { /* optional Bootloader (BL) section */ if (device->bootloader_size) { /* optional Bootloader (BL) section */
efm32_add_flash(t, 0x0fe10000, device->bootloader_size, flash_page_size); efm32_add_flash(t, 0x0fe10000, device->bootloader_size, flash_page_size);
} }
target_add_commands(t, efm32_cmd_list, "EFM32"); target_add_commands(t, efm32_cmd_list, "EFM32");
return true; return true;
} }
/** /* Erase flash row by row */
* Erase flash row by row
*/
static int efm32_flash_erase(struct target_flash *f, target_addr addr, size_t len) static int efm32_flash_erase(struct target_flash *f, target_addr addr, size_t len)
{ {
target *t = f->t; target *t = f->t;
@ -680,7 +640,7 @@ static int efm32_flash_erase(struct target_flash *f, target_addr addr, size_t le
/* Unlock */ /* Unlock */
target_mem_write32(t, EFM32_MSC_LOCK(msc), EFM32_MSC_LOCK_LOCKKEY); target_mem_write32(t, EFM32_MSC_LOCK(msc), EFM32_MSC_LOCK_LOCKKEY);
/* Set WREN bit to enabel MSC write and erase functionality */ /* Set WREN bit to enable MSC write and erase functionality */
target_mem_write32(t, EFM32_MSC_WRITECTRL(msc), 1); target_mem_write32(t, EFM32_MSC_WRITECTRL(msc), 1);
while (len) { while (len) {
@ -707,11 +667,8 @@ static int efm32_flash_erase(struct target_flash *f, target_addr addr, size_t le
return 0; return 0;
} }
/** /* Write flash page by page */
* Write flash page by page static int efm32_flash_write(struct target_flash *f, target_addr dest, const void *src, size_t len)
*/
static int efm32_flash_write(struct target_flash *f,
target_addr dest, const void *src, size_t len)
{ {
(void)len; (void)len;
target *t = f->t; target *t = f->t;
@ -720,13 +677,11 @@ static int efm32_flash_write(struct target_flash *f,
return true; return true;
} }
/* Write flashloader */ /* Write flashloader */
target_mem_write(t, SRAM_BASE, efm32_flash_write_stub, target_mem_write(t, SRAM_BASE, efm32_flash_write_stub, sizeof(efm32_flash_write_stub));
sizeof(efm32_flash_write_stub));
/* Write Buffer */ /* Write Buffer */
target_mem_write(t, STUB_BUFFER_BASE, src, len); target_mem_write(t, STUB_BUFFER_BASE, src, len);
/* Run flashloader */ /* Run flashloader */
int ret = cortexm_run_stub(t, SRAM_BASE, dest, STUB_BUFFER_BASE, len, int ret = cortexm_run_stub(t, SRAM_BASE, dest, STUB_BUFFER_BASE, len, device->msc_addr);
device->msc_addr);
#ifdef ENABLE_DEBUG #ifdef ENABLE_DEBUG
/* Check the MSC_IF */ /* Check the MSC_IF */
@ -737,9 +692,7 @@ static int efm32_flash_write(struct target_flash *f,
return ret; return ret;
} }
/** /* Uses the MSC ERASEMAIN0/1 command to erase the entire flash */
* Uses the MSC ERASEMAIN0 command to erase the entire flash
*/
static bool efm32_mass_erase(target *t) static bool efm32_mass_erase(target *t)
{ {
efm32_device_t const* device = efm32_get_device(t->driver[2] - 32); efm32_device_t const* device = efm32_get_device(t->driver[2] - 32);
@ -748,7 +701,7 @@ static bool efm32_mass_erase(target *t)
} }
uint32_t msc = device->msc_addr; uint32_t msc = device->msc_addr;
/* Set WREN bit to enabel MSC write and erase functionality */ /* Set WREN bit to enable MSC write and erase functionality */
target_mem_write32(t, EFM32_MSC_WRITECTRL(msc), 1); target_mem_write32(t, EFM32_MSC_WRITECTRL(msc), 1);
/* Unlock mass erase */ /* Unlock mass erase */
@ -772,9 +725,7 @@ static bool efm32_mass_erase(target *t)
return true; return true;
} }
/** /* Reads the 40-bit unique number */
* Reads the 40-bit unique number
*/
static bool efm32_cmd_serial(target *t, int argc, const char **argv) static bool efm32_cmd_serial(target *t, int argc, const char **argv)
{ {
(void)argc; (void)argc;
@ -797,9 +748,8 @@ static bool efm32_cmd_serial(target *t, int argc, const char **argv)
return true; return true;
} }
/**
* Prints various information we know about the device /* Prints various information we know about the device */
*/
static bool efm32_cmd_efm_info(target *t, int argc, const char **argv) static bool efm32_cmd_efm_info(target *t, int argc, const char **argv)
{ {
(void)argc; (void)argc;
@ -831,11 +781,10 @@ static bool efm32_cmd_efm_info(target *t, int argc, const char **argv)
uint32_t flash_page_size_reported = efm32_flash_page_size(t, di_version); uint32_t flash_page_size_reported = efm32_flash_page_size(t, di_version);
uint32_t flash_page_size = device->flash_page_size; uint32_t flash_page_size = device->flash_page_size;
tc_printf(t, "%s %d F%d = %s %dkiB flash, %dkiB ram\n", tc_printf(t, "%s %d F%d = %s %dkiB flash, %dkiB ram\n", device->name, part_number, flash_kib, device->description,
device->name, part_number, flash_kib, flash_kib, ram_kib);
device->description, flash_kib, ram_kib); tc_printf(t, "Device says flash page size is %d bytes, we're using %d bytes\n", flash_page_size_reported,
tc_printf(t, "Device says flash page size is %d bytes, we're using %d bytes\n", flash_page_size);
flash_page_size_reported, flash_page_size);
if (flash_page_size_reported < flash_page_size) { if (flash_page_size_reported < flash_page_size) {
tc_printf(t, "This is bad, flash writes may be corrupted\n"); tc_printf(t, "This is bad, flash writes may be corrupted\n");
} }
@ -846,14 +795,12 @@ static bool efm32_cmd_efm_info(target *t, int argc, const char **argv)
efm32_v2_di_pkgtype_t const *pkgtype = NULL; efm32_v2_di_pkgtype_t const *pkgtype = NULL;
efm32_v2_di_tempgrade_t const *tempgrade; efm32_v2_di_tempgrade_t const *tempgrade;
for (size_t i = 0; i < (sizeof(efm32_v2_di_pkgtypes) / for (size_t i = 0; i < (sizeof(efm32_v2_di_pkgtypes) / sizeof(efm32_v2_di_pkgtype_t)); i++) {
sizeof(efm32_v2_di_pkgtype_t)); i++) {
if (efm32_v2_di_pkgtypes[i].pkgtype == miscchip.pkgtype) { if (efm32_v2_di_pkgtypes[i].pkgtype == miscchip.pkgtype) {
pkgtype = &efm32_v2_di_pkgtypes[i]; pkgtype = &efm32_v2_di_pkgtypes[i];
} }
} }
for (size_t i = 0; i < (sizeof(efm32_v2_di_tempgrades) / for (size_t i = 0; i < (sizeof(efm32_v2_di_tempgrades) / sizeof(efm32_v2_di_tempgrade_t)); i++) {
sizeof(efm32_v2_di_tempgrade_t)); i++) {
if (efm32_v2_di_tempgrades[i].tempgrade == miscchip.tempgrade) { if (efm32_v2_di_tempgrades[i].tempgrade == miscchip.tempgrade) {
tempgrade = &efm32_v2_di_tempgrades[i]; tempgrade = &efm32_v2_di_tempgrades[i];
} }
@ -896,8 +843,7 @@ static bool efm32_cmd_bootloader(target *t, int argc, const char **argv)
bool bootloader_status = (clw0 & EFM32_CLW0_BOOTLOADER_ENABLE) ? 1 : 0; bool bootloader_status = (clw0 & EFM32_CLW0_BOOTLOADER_ENABLE) ? 1 : 0;
if (argc == 1) { if (argc == 1) {
tc_printf(t, "Bootloader %s\n", tc_printf(t, "Bootloader %s\n", bootloader_status ? "enabled" : "disabled");
bootloader_status ? "enabled" : "disabled");
return true; return true;
} else { } else {
bootloader_status = (argv[1][0] == 'e'); bootloader_status = (argv[1][0] == 'e');
@ -929,10 +875,11 @@ static bool efm32_cmd_bootloader(target *t, int argc, const char **argv)
return true; return true;
} }
/* -------------------------------------------------------------------------- */
/* Authentication Access Port (AAP) */
/* -------------------------------------------------------------------------- */
/*** Authentication Access Port (AAP) **/ /* There's an additional AP on the SW-DP that is accessible when the part
/* There's an additional AP on the SW-DP is accessable when the part
* is almost entirely locked. * is almost entirely locked.
* *
* The AAP can be used to issue a DEVICEERASE command, which erases: * The AAP can be used to issue a DEVICEERASE command, which erases:
@ -945,7 +892,7 @@ static bool efm32_cmd_bootloader(target *t, int argc, const char **argv)
* * Bootloader (BL) if present * * Bootloader (BL) if present
* *
* Once the DEVICEERASE command has completed, the main AP will be * Once the DEVICEERASE command has completed, the main AP will be
* accessable again. If the device has a bootloader, it will attempt * accessible again. If the device has a bootloader, it will attempt
* to boot from this. If you have just unlocked the device the * to boot from this. If you have just unlocked the device the
* bootloader could be anything (even garbage, if the bootloader * bootloader could be anything (even garbage, if the bootloader
* wasn't used before the DEVICEERASE). Therefore you may want to * wasn't used before the DEVICEERASE). Therefore you may want to
@ -972,9 +919,7 @@ static bool efm32_cmd_bootloader(target *t, int argc, const char **argv)
static bool efm32_aap_mass_erase(target *t); static bool efm32_aap_mass_erase(target *t);
/** /* AAP Probe */
* AAP Probe
*/
struct efm32_aap_priv_s { struct efm32_aap_priv_s {
char aap_driver_string[42]; char aap_driver_string[42];
}; };
@ -1001,9 +946,7 @@ void efm32_aap_probe(ADIv5_AP_t *ap)
DEBUG_INFO("EFM32: AAP STATUS=%08" PRIx32 "\n", adiv5_ap_read(ap, AAP_STATUS)); DEBUG_INFO("EFM32: AAP STATUS=%08" PRIx32 "\n", adiv5_ap_read(ap, AAP_STATUS));
struct efm32_aap_priv_s *priv_storage = calloc(1, sizeof(*priv_storage)); struct efm32_aap_priv_s *priv_storage = calloc(1, sizeof(*priv_storage));
sprintf(priv_storage->aap_driver_string, sprintf(priv_storage->aap_driver_string, "EFM32 Authentication Access Port rev.%d", aap_revision);
"EFM32 Authentication Access Port rev.%d",
aap_revision);
t->driver = priv_storage->aap_driver_string; t->driver = priv_storage->aap_driver_string;
t->regs_size = 4; t->regs_size = 4;
} }