target: add samx7x probe method
adds support for SAME70, SAMS70, SAMV71 and SAMV70 Signed-off-by: Rafael Silva <perigoso@riseup.net>
This commit is contained in:
Rafael Silva
Rachel Mant
parent
e3142ade8c
commit
430d306511
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@ -413,6 +413,7 @@ bool cortexm_probe(ADIv5_AP_t *ap)
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PROBE(nrf51_probe);
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break;
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case AP_DESIGNER_ATMEL:
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PROBE(samx7x_probe);
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PROBE(sam4l_probe);
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PROBE(samd_probe);
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PROBE(samx5x_probe);
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@ -21,7 +21,7 @@
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/* This file implements Atmel SAM3/4 target specific functions for detecting
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* the device, providing the XML memory map and Flash memory programming.
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*
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* Supported devices: SAM3N, SAM3S, SAM3U, SAM3X, and SAM4S
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* Supported devices: SAM3N, SAM3S, SAM3U, SAM3X, SAM4S, SAME70, SAMS70, SAMV71, SAMV70
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*/
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#include "general.h"
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@ -43,6 +43,7 @@ const struct command_s sam3x_cmd_list[] = {
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};
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/* Enhanced Embedded Flash Controller (EEFC) Register Map */
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#define SAMX7X_EEFC_BASE 0x400E0C00
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#define SAM3N_EEFC_BASE 0x400E0A00
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#define SAM3X_EEFC_BASE(x) (0x400E0A00+((x)*0x200))
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#define SAM3U_EEFC_BASE(x) (0x400E0800+((x)*0x200))
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@ -77,44 +78,72 @@ const struct command_s sam3x_cmd_list[] = {
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#define SAM3X_CHIPID_CIDR 0x400E0940
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#define SAM34NSU_CHIPID_CIDR 0x400E0740
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#define SAMX_CHIPID_EXID (SAM3X_CHIPID_CIDR + 0x4)
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#define CHIPID_CIDR_VERSION_MASK (0x1F << 0)
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#define CHIPID_CIDR_EPROC_CM3 (0x03 << 5)
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#define CHIPID_CIDR_EPROC_CM4 (0x07 << 5)
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#define CHIPID_CIDR_EPROC_MASK (0x07 << 5)
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#define CHIPID_CIDR_NVPSIZ_MASK (0x0F << 8)
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#define CHIPID_CIDR_NVPSIZ_8K (0x01 << 8)
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#define CHIPID_CIDR_NVPSIZ_16K (0x02 << 8)
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#define CHIPID_CIDR_NVPSIZ_32K (0x03 << 8)
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#define CHIPID_CIDR_NVPSIZ_64K (0x05 << 8)
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#define CHIPID_CIDR_NVPSIZ_128K (0x07 << 8)
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#define CHIPID_CIDR_NVPSIZ_256K (0x09 << 8)
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#define CHIPID_CIDR_NVPSIZ_512K (0x0A << 8)
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#define CHIPID_CIDR_NVPSIZ_1024K (0x0C << 8)
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#define CHIPID_CIDR_NVPSIZ_2048K (0x0E << 8)
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#define CHIPID_CIDR_NVPSIZ2_MASK (0x0F << 12)
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#define CHIPID_CIDR_SRAMSIZ_MASK (0x0F << 16)
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#define CHIPID_CIDR_ARCH_MASK (0xFF << 20)
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#define CHIPID_CIDR_ARCH_SAM3UxC (0x80 << 20)
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#define CHIPID_CIDR_ARCH_SAM3UxE (0x81 << 20)
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#define CHIPID_CIDR_ARCH_SAM3XxC (0x84 << 20)
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#define CHIPID_CIDR_ARCH_SAM3XxE (0x85 << 20)
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#define CHIPID_CIDR_ARCH_SAM3XxG (0x86 << 20)
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#define CHIPID_CIDR_ARCH_SAM3NxA (0x93 << 20)
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#define CHIPID_CIDR_ARCH_SAM3NxB (0x94 << 20)
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#define CHIPID_CIDR_ARCH_SAM3NxC (0x95 << 20)
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#define CHIPID_CIDR_ARCH_SAM3SxA (0x88 << 20)
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#define CHIPID_CIDR_ARCH_SAM3SxB (0x89 << 20)
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#define CHIPID_CIDR_ARCH_SAM3SxC (0x8A << 20)
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#define CHIPID_CIDR_ARCH_SAM4SxA (0x88 << 20)
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#define CHIPID_CIDR_ARCH_SAM4SxB (0x89 << 20)
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#define CHIPID_CIDR_ARCH_SAM4SxC (0x8A << 20)
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#define CHIPID_CIDR_ARCH_SAM4SDB (0x99 << 20)
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#define CHIPID_CIDR_ARCH_SAM4SDC (0x9A << 20)
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#define CHIPID_CIDR_NVPTYP_MASK (0x07 << 28)
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#define CHIPID_CIDR_NVPTYP_FLASH (0x02 << 28)
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#define CHIPID_CIDR_NVPTYP_ROM_FLASH (0x03 << 28)
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#define CHIPID_CIDR_EPROC_OFFSET (5)
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#define CHIPID_CIDR_EPROC_MASK (0x7 << CHIPID_CIDR_EPROC_OFFSET)
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#define CHIPID_CIDR_EPROC_CM7 (0x0 << CHIPID_CIDR_EPROC_OFFSET)
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#define CHIPID_CIDR_EPROC_CM3 (0x3 << CHIPID_CIDR_EPROC_OFFSET)
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#define CHIPID_CIDR_EPROC_CM4 (0x7 << CHIPID_CIDR_EPROC_OFFSET)
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#define CHIPID_CIDR_NVPSIZ_OFFSET (8)
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#define CHIPID_CIDR_NVPSIZ_MASK (0xF << CHIPID_CIDR_NVPSIZ_OFFSET)
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#define CHIPID_CIDR_NVPSIZ_8K (0x1 << CHIPID_CIDR_NVPSIZ_OFFSET)
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#define CHIPID_CIDR_NVPSIZ_16K (0x2 << CHIPID_CIDR_NVPSIZ_OFFSET)
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#define CHIPID_CIDR_NVPSIZ_32K (0x3 << CHIPID_CIDR_NVPSIZ_OFFSET)
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#define CHIPID_CIDR_NVPSIZ_64K (0x5 << CHIPID_CIDR_NVPSIZ_OFFSET)
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#define CHIPID_CIDR_NVPSIZ_128K (0x7 << CHIPID_CIDR_NVPSIZ_OFFSET)
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#define CHIPID_CIDR_NVPSIZ_256K (0x9 << CHIPID_CIDR_NVPSIZ_OFFSET)
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#define CHIPID_CIDR_NVPSIZ_512K (0xA << CHIPID_CIDR_NVPSIZ_OFFSET)
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#define CHIPID_CIDR_NVPSIZ_1024K (0xC << CHIPID_CIDR_NVPSIZ_OFFSET)
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#define CHIPID_CIDR_NVPSIZ_2048K (0xE << CHIPID_CIDR_NVPSIZ_OFFSET)
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#define CHIPID_CIDR_NVPSIZ2_OFFSET (12)
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#define CHIPID_CIDR_NVPSIZ2_MASK (0xF << CHIPID_CIDR_NVPSIZ2_OFFSET)
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#define CHIPID_CIDR_SRAMSIZ_OFFSET (16)
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#define CHIPID_CIDR_SRAMSIZ_MASK (0xF << CHIPID_CIDR_SRAMSIZ_OFFSET)
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#define CHIPID_CIDR_SRAMSIZ_384K (0x2 << CHIPID_CIDR_SRAMSIZ_OFFSET)
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#define CHIPID_CIDR_SRAMSIZ_256K (0xD << CHIPID_CIDR_SRAMSIZ_OFFSET)
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#define CHIPID_CIDR_ARCH_OFFSET (20)
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#define CHIPID_CIDR_ARCH_MASK (0xFF << CHIPID_CIDR_ARCH_OFFSET)
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#define CHIPID_CIDR_ARCH_SAME70 (0x10 << CHIPID_CIDR_ARCH_OFFSET)
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#define CHIPID_CIDR_ARCH_SAMS70 (0x11 << CHIPID_CIDR_ARCH_OFFSET)
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#define CHIPID_CIDR_ARCH_SAMV71 (0x12 << CHIPID_CIDR_ARCH_OFFSET)
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#define CHIPID_CIDR_ARCH_SAMV70 (0x13 << CHIPID_CIDR_ARCH_OFFSET)
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#define CHIPID_CIDR_ARCH_SAM3UxC (0x80 << CHIPID_CIDR_ARCH_OFFSET)
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#define CHIPID_CIDR_ARCH_SAM3UxE (0x81 << CHIPID_CIDR_ARCH_OFFSET)
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#define CHIPID_CIDR_ARCH_SAM3XxC (0x84 << CHIPID_CIDR_ARCH_OFFSET)
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#define CHIPID_CIDR_ARCH_SAM3XxE (0x85 << CHIPID_CIDR_ARCH_OFFSET)
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#define CHIPID_CIDR_ARCH_SAM3XxG (0x86 << CHIPID_CIDR_ARCH_OFFSET)
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#define CHIPID_CIDR_ARCH_SAM3NxA (0x93 << CHIPID_CIDR_ARCH_OFFSET)
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#define CHIPID_CIDR_ARCH_SAM3NxB (0x94 << CHIPID_CIDR_ARCH_OFFSET)
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#define CHIPID_CIDR_ARCH_SAM3NxC (0x95 << CHIPID_CIDR_ARCH_OFFSET)
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#define CHIPID_CIDR_ARCH_SAM3SxA (0x88 << CHIPID_CIDR_ARCH_OFFSET)
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#define CHIPID_CIDR_ARCH_SAM3SxB (0x89 << CHIPID_CIDR_ARCH_OFFSET)
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#define CHIPID_CIDR_ARCH_SAM3SxC (0x8A << CHIPID_CIDR_ARCH_OFFSET)
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#define CHIPID_CIDR_ARCH_SAM4SxA (0x88 << CHIPID_CIDR_ARCH_OFFSET)
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#define CHIPID_CIDR_ARCH_SAM4SxB (0x89 << CHIPID_CIDR_ARCH_OFFSET)
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#define CHIPID_CIDR_ARCH_SAM4SxC (0x8A << CHIPID_CIDR_ARCH_OFFSET)
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#define CHIPID_CIDR_ARCH_SAM4SDB (0x99 << CHIPID_CIDR_ARCH_OFFSET)
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#define CHIPID_CIDR_ARCH_SAM4SDC (0x9A << CHIPID_CIDR_ARCH_OFFSET)
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#define CHIPID_CIDR_NVPTYP_OFFSET (28)
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#define CHIPID_CIDR_NVPTYP_MASK (0x7 << CHIPID_CIDR_NVPTYP_OFFSET)
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#define CHIPID_CIDR_NVPTYP_FLASH (0x2 << CHIPID_CIDR_NVPTYP_OFFSET)
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#define CHIPID_CIDR_NVPTYP_ROM_FLASH (0x3 << CHIPID_CIDR_NVPTYP_OFFSET)
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#define CHIPID_CIDR_EXT (0x01 << 31)
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#define CHIPID_EXID_SAMX7X_PINS_OFFSET (0)
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#define CHIPID_EXID_SAMX7X_PINS_MASK (0x3 << CHIPID_EXID_SAMX7X_PINS_OFFSET)
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#define CHIPID_EXID_SAMX7X_PINS_Q (0x2 << CHIPID_EXID_SAMX7X_PINS_OFFSET)
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#define CHIPID_EXID_SAMX7X_PINS_N (0x1 << CHIPID_EXID_SAMX7X_PINS_OFFSET)
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#define CHIPID_EXID_SAMX7X_PINS_J (0x0 << CHIPID_EXID_SAMX7X_PINS_OFFSET)
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#define SAM3_PAGE_SIZE 256
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#define SAM4_PAGE_SIZE 512
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@ -124,6 +153,10 @@ struct sam_flash {
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uint8_t write_cmd;
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};
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struct sam_priv_s {
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char sam_variant_string[60];
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};
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static void sam3_add_flash(target *t,
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uint32_t eefc_base, uint32_t addr, size_t length)
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{
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@ -195,6 +228,149 @@ static size_t sam_flash_size(uint32_t cidr)
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return 0;
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}
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static size_t sam_sram_size(uint32_t cidr)
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{
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switch (cidr & CHIPID_CIDR_SRAMSIZ_MASK) {
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case CHIPID_CIDR_SRAMSIZ_256K:
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return 0x40000;
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case CHIPID_CIDR_SRAMSIZ_384K:
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return 0x60000;
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default:
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return 0;
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}
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}
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struct samx7x_descr {
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char product_code;
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uint8_t product_id;
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char pins;
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uint32_t ram_size;
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uint32_t flash_size;
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uint8_t density;
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char revision;
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};
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struct samx7x_descr samx7x_parse_id(uint32_t cidr, uint32_t exid) {
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struct samx7x_descr descr = {0};
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switch (cidr & CHIPID_CIDR_ARCH_MASK) {
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case CHIPID_CIDR_ARCH_SAME70:
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descr.product_code = 'E';
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descr.product_id = 70;
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break;
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case CHIPID_CIDR_ARCH_SAMS70:
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descr.product_code = 'S';
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descr.product_id = 70;
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break;
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case CHIPID_CIDR_ARCH_SAMV71:
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descr.product_code = 'V';
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descr.product_id = 71;
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break;
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case CHIPID_CIDR_ARCH_SAMV70:
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descr.product_code = 'V';
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descr.product_id = 70;
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break;
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}
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// A = Revision A, legacy version
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// B = Revision B, current variant
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switch (exid & CHIPID_CIDR_VERSION_MASK) {
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case 0:
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descr.revision = 'A';
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break;
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case 1:
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descr.revision = 'B';
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break;
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default:
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descr.revision = '_';
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break;
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}
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// Q = 144 pins
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// N = 100 pins
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// J = 64 pins
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switch (exid & CHIPID_EXID_SAMX7X_PINS_MASK) {
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case CHIPID_EXID_SAMX7X_PINS_Q:
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descr.pins = 'Q';
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break;
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case CHIPID_EXID_SAMX7X_PINS_N:
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descr.pins = 'N';
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break;
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case CHIPID_EXID_SAMX7X_PINS_J:
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descr.pins = 'J';
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break;
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}
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descr.ram_size = sam_sram_size(cidr);
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descr.flash_size = sam_flash_size(cidr);
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// 21 = 2048 KB
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// 20 = 1024 KB
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// 19 = 512 KB
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switch (descr.flash_size)
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{
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case 0x200000:
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descr.density = 21;
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break;
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case 0x100000:
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descr.density = 20;
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break;
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case 0x80000:
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descr.density = 19;
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break;
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default:
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descr.density = 0;
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break;
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}
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return descr;
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}
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bool samx7x_probe(target *t)
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{
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uint32_t cidr = target_mem_read32(t, SAM3X_CHIPID_CIDR);
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uint32_t exid = 0;
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if (cidr & CHIPID_CIDR_EXT) {
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exid = target_mem_read32(t, SAMX_CHIPID_EXID);
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}
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switch (cidr & CHIPID_CIDR_ARCH_MASK) {
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case CHIPID_CIDR_ARCH_SAME70:
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case CHIPID_CIDR_ARCH_SAMS70:
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case CHIPID_CIDR_ARCH_SAMV71:
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case CHIPID_CIDR_ARCH_SAMV70:
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break;
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default:
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return false;
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}
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struct samx7x_descr descr = samx7x_parse_id(cidr, exid);
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target_add_ram(t, 0x20400000, descr.ram_size);
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sam4_add_flash(t, SAMX7X_EEFC_BASE, 0x00400000, descr.flash_size);
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target_add_commands(t, sam3x_cmd_list, "SAMX7X");
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struct sam_priv_s *priv_storage = calloc(1, sizeof(*priv_storage));
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if (!priv_storage) { /* calloc failed: heap exhaustion */
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DEBUG_WARN("calloc: failed in %s\n", __func__);
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return false;
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}
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t->target_storage = (void*)priv_storage;
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sprintf(priv_storage->sam_variant_string,
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"SAM%c%02d%c%d%c",
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descr.product_code,
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descr.product_id,
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descr.pins,
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descr.density,
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descr.revision);
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t->driver = priv_storage->sam_variant_string;
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return true;
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}
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bool sam3x_probe(target *t)
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{
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uint32_t cidr = target_mem_read32(t, SAM3X_CHIPID_CIDR);
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@ -292,7 +468,10 @@ static uint32_t sam3x_flash_base(target *t)
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if (strcmp(t->driver, "Atmel SAM4S") == 0) {
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return SAM4S_EEFC_BASE(0);
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}
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return SAM3N_EEFC_BASE;
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if (strcmp(t->driver, "Atmel SAM3N/S") == 0) {
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return SAM3N_EEFC_BASE;
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}
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return SAMX7X_EEFC_BASE;
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}
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static int sam4_flash_erase(struct target_flash *f, target_addr addr, size_t len)
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@ -188,6 +188,7 @@ bool lpc15xx_probe(target *t);
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bool lpc17xx_probe(target *t);
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bool lpc43xx_probe(target *t);
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bool lpc546xx_probe(target *t);
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bool samx7x_probe(target *t);
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bool sam3x_probe(target *t);
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bool sam4l_probe(target *t);
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bool nrf51_probe(target *t);
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