stm32g0: Run clang-format through much of the code
This commit is contained in:
dragonmux
Piotr Esden-Tempski
parent
ba7c6a3048
commit
43afb5207a
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@ -146,11 +146,13 @@ enum STM32G0_DEV_ID {
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STM32G07_8 = 0x460,
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STM32G0B_C = 0x467
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};
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struct stm32g0_saved_regs_s {
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uint32_t rcc_apbenr1;
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uint32_t dbg_cr;
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uint32_t dbg_apb_fz1;
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};
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struct stm32g0_priv_s {
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struct stm32g0_saved_regs_s saved_regs;
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bool irreversible_enabled;
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@ -168,14 +170,13 @@ static bool stm32g0_cmd_option(target *t, int argc, const char **argv);
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static bool stm32g0_cmd_irreversible(target *t, int argc, const char **argv);
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const struct command_s stm32g0_cmd_list[] = {
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{ "erase_bank 1|2", stm32g0_cmd_erase_bank, "Erase specified Flash bank" },
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{ "option", stm32g0_cmd_option, "Manipulate option bytes" },
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{ "irreversible", stm32g0_cmd_irreversible, "Allow irreversible operations: (enable|disable)" },
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{ NULL, NULL, NULL },
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{"erase_bank 1|2", stm32g0_cmd_erase_bank, "Erase specified Flash bank"},
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{"option", stm32g0_cmd_option, "Manipulate option bytes"},
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{"irreversible", stm32g0_cmd_irreversible, "Allow irreversible operations: (enable|disable)"},
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{NULL, NULL, NULL},
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};
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static void stm32g0_add_flash(target *t, uint32_t addr, size_t length,
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size_t blocksize)
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static void stm32g0_add_flash(target *t, uint32_t addr, size_t length, size_t blocksize)
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{
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target_flash_s *f = calloc(1, sizeof(*f));
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if (!f) { /* calloc failed: heap exhaustion */
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@ -189,7 +190,7 @@ static void stm32g0_add_flash(target *t, uint32_t addr, size_t length,
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f->erase = stm32g0_flash_erase;
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f->write = stm32g0_flash_write;
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f->buf_size = blocksize;
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f->erased = 0xFF;
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f->erased = 0xffU;
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target_add_flash(t, f);
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}
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@ -235,6 +236,7 @@ bool stm32g0_probe(target *t)
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default:
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return false;
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}
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t->mass_erase = stm32g0_mass_erase;
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target_add_ram(t, RAM_START, ram_size);
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/* Dual banks: contiguous in memory */
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@ -247,7 +249,7 @@ bool stm32g0_probe(target *t)
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/* Save private storage */
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struct stm32g0_priv_s *priv_storage = calloc(1, sizeof(*priv_storage));
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priv_storage->irreversible_enabled = false;
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t->target_storage = (void*)priv_storage;
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t->target_storage = priv_storage;
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/* OTP Flash area */
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stm32g0_add_flash(t, FLASH_OTP_START, FLASH_OTP_SIZE, FLASH_OTP_BLOCKSIZE);
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@ -265,20 +267,18 @@ bool stm32g0_probe(target *t)
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*/
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static bool stm32g0_attach(target *t)
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{
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struct stm32g0_priv_s *ps = (struct stm32g0_priv_s*)t->target_storage;
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struct stm32g0_priv_s *ps = (struct stm32g0_priv_s *)t->target_storage;
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if (!cortexm_attach(t))
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return false;
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ps->saved_regs.rcc_apbenr1 = target_mem_read32(t, RCC_APBENR1);
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target_mem_write32(t, RCC_APBENR1, ps->saved_regs.rcc_apbenr1 |
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RCC_APBENR1_DBGEN);
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target_mem_write32(t, RCC_APBENR1, ps->saved_regs.rcc_apbenr1 | RCC_APBENR1_DBGEN);
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ps->saved_regs.dbg_cr = target_mem_read32(t, DBG_CR);
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target_mem_write32(t, DBG_CR, ps->saved_regs.dbg_cr |
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(DBG_CR_DBG_STANDBY | DBG_CR_DBG_STOP));
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target_mem_write32(t, DBG_CR, ps->saved_regs.dbg_cr | (DBG_CR_DBG_STANDBY | DBG_CR_DBG_STOP));
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ps->saved_regs.dbg_apb_fz1 = target_mem_read32(t, DBG_APB_FZ1);
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target_mem_write32(t, DBG_APB_FZ1, ps->saved_regs.dbg_apb_fz1 |
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(DBG_APB_FZ1_DBG_IWDG_STOP | DBG_APB_FZ1_DBG_WWDG_STOP));
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target_mem_write32(
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t, DBG_APB_FZ1, ps->saved_regs.dbg_apb_fz1 | (DBG_APB_FZ1_DBG_IWDG_STOP | DBG_APB_FZ1_DBG_WWDG_STOP));
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return true;
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}
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@ -290,14 +290,13 @@ static bool stm32g0_attach(target *t)
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*/
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static void stm32g0_detach(target *t)
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{
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struct stm32g0_priv_s *ps = (struct stm32g0_priv_s*)t->target_storage;
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struct stm32g0_priv_s *ps = (struct stm32g0_priv_s *)t->target_storage;
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/*
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* First re-enable DBGEN clock, in case it got disabled in the meantime
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* (happens during flash), so that writes to DBG_* registers below succeed.
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*/
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target_mem_write32(t, RCC_APBENR1, ps->saved_regs.rcc_apbenr1 |
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RCC_APBENR1_DBGEN);
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target_mem_write32(t, RCC_APBENR1, ps->saved_regs.rcc_apbenr1 | RCC_APBENR1_DBGEN);
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/*
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* Then restore the DBG_* registers and clock settings.
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@ -367,8 +366,7 @@ static int stm32g0_flash_erase(target_flash_s *f, target_addr addr, size_t len)
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page_nb = FLASH_BANK2_START_PAGE_NB;
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}
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/* Erase */
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uint32_t flash_cr = (uint32_t)((page_nb << FLASH_CR_PNB_SHIFT) |
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FLASH_CR_PER);
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uint32_t flash_cr = (uint32_t)((page_nb << FLASH_CR_PNB_SHIFT) | FLASH_CR_PER);
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if (on_bank2)
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flash_cr |= (uint32_t)(FLASH_CR_BKER);
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@ -389,8 +387,7 @@ static int stm32g0_flash_erase(target_flash_s *f, target_addr addr, size_t len)
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/* Check for error */
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uint32_t flash_sr = target_mem_read32(t, FLASH_SR);
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if (flash_sr & FLASH_SR_ERROR_MASK) {
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DEBUG_WARN("stm32g0 flash erase error: sr 0x%" PRIx32 "\n",
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flash_sr);
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DEBUG_WARN("stm32g0 flash erase error: sr 0x%" PRIx32 "\n", flash_sr);
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goto exit_error;
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}
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goto exit_cleanup;
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@ -411,12 +408,11 @@ exit_cleanup:
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* OTP area is programmed as the "program" area. It can be programmed 8-bytes
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* by 8-bytes.
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*/
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static int stm32g0_flash_write(target_flash_s *f, target_addr dest,
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const void *src, size_t len)
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static int stm32g0_flash_write(target_flash_s *f, target_addr dest, const void *src, size_t len)
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{
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target *t = f->t;
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target *const t = f->t;
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int ret = 0;
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struct stm32g0_priv_s *ps = (struct stm32g0_priv_s*)t->target_storage;
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struct stm32g0_priv_s *ps = (struct stm32g0_priv_s *)t->target_storage;
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if ((dest >= (target_addr)FLASH_OTP_START) && !ps->irreversible_enabled) {
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tc_printf(t, "Irreversible operations disabled\n");
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@ -438,12 +434,10 @@ static int stm32g0_flash_write(target_flash_s *f, target_addr dest,
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} while (flash_sr & FLASH_SR_BSY_MASK);
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if (flash_sr & FLASH_SR_ERROR_MASK) {
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DEBUG_WARN("stm32g0 flash write error: sr 0x%" PRIx32 "\n",
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flash_sr);
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DEBUG_WARN("stm32g0 flash write error: sr 0x%" PRIx32 "\n", flash_sr);
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goto exit_error;
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}
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if ((dest == (target_addr)FLASH_START) &&
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target_mem_read32(t, FLASH_START) != 0xFFFFFFFF) {
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if ((dest == (target_addr)FLASH_START) && target_mem_read32(t, FLASH_START) != 0xFFFFFFFF) {
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uint32_t flash_acr = target_mem_read32(t, FLASH_ACR);
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flash_acr &= ~(uint32_t)FLASH_ACR_EMPTY;
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target_mem_write32(t, FLASH_ACR, flash_acr);
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@ -586,20 +580,18 @@ static const struct registers_s options_def[NB_REG_OPT] = {
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[SECR_ENUM] = { FLASH_SECR, 0x00000000 }
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};
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static void write_registers(target *t, const struct registers_s *regs,
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uint8_t nb_regs)
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static void write_registers(target *const t, const struct registers_s *const regs, const size_t nb_regs)
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{
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for (uint8_t i = 0U; i < nb_regs; i++) {
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if (regs[i].addr > 0U)
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target_mem_write32(t, regs[i].addr, regs[i].val);
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for (size_t reg = 0U; reg < nb_regs; ++reg) {
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if (regs[reg].addr > 0U)
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target_mem_write32(t, regs[reg].addr, regs[reg].val);
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}
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}
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/*
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* Option bytes programming.
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*/
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static bool stm32g0_option_write(target *t,
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const struct registers_s *options_req)
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static bool stm32g0_option_write(target *const t, const struct registers_s *const options_req)
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{
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stm32g0_flash_unlock(t);
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stm32g0_flash_option_unlock(t);
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@ -633,14 +625,13 @@ exit_error:
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* This table is further written to the target.
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* The register is added only if its address is valid.
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*/
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static bool add_reg_value(struct registers_s *reg_req,
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const struct registers_s *reg_def,
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uint8_t reg_def_len, uint32_t addr, uint32_t val)
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static bool add_reg_value(struct registers_s *const reg_req, const struct registers_s *const reg_def,
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const size_t reg_def_len, const uint32_t addr, const uint32_t val)
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{
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for (uint8_t j = 0U; j < reg_def_len; j++) {
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if (addr == reg_def[j].addr) {
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reg_req[j].addr = addr;
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reg_req[j].val = val;
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for (size_t reg = 0U; reg < reg_def_len; ++reg) {
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if (addr == reg_def[reg].addr) {
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reg_req[reg].addr = addr;
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reg_req[reg].val = val;
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return true;
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}
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}
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@ -650,26 +641,19 @@ static bool add_reg_value(struct registers_s *reg_req,
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/*
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* Parse (address, value) register pairs given on the command line.
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*/
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static bool parse_cmdline_registers(int args_nb, const char **reg_str,
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struct registers_s *reg_req,
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const struct registers_s *reg_def,
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uint8_t reg_def_len)
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static bool parse_cmdline_registers(const uint32_t argc, const char *const *const argv,
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struct registers_s *const reg_req, const struct registers_s *const reg_def, const size_t reg_def_len)
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{
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uint32_t addr = 0U;
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uint32_t val = 0U;
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uint8_t valid_regs_nb = 0U;
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uint32_t valid_regs = 0U;
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for (uint8_t i = 0U; i < args_nb; i += 2U) {
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addr = strtoul(reg_str[i], NULL, 0);
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val = strtoul(reg_str[i + 1], NULL, 0);
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for (uint32_t i = 0U; i < argc; i += 2U) {
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const uint32_t addr = strtoul(argv[i], NULL, 0);
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const uint32_t val = strtoul(argv[i + 1], NULL, 0);
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if (add_reg_value(reg_req, reg_def, reg_def_len, addr, val))
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valid_regs_nb++;
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++valid_regs;
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}
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if (valid_regs_nb > 0U)
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return true;
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else
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return false;
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return valid_regs > 0U;
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}
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/*
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@ -678,24 +662,19 @@ static bool parse_cmdline_registers(int args_nb, const char **reg_str,
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*/
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static bool validate_options(target *t, const struct registers_s *options_req)
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{
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struct stm32g0_priv_s *ps = (struct stm32g0_priv_s*)t->target_storage;
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struct stm32g0_priv_s *ps = (struct stm32g0_priv_s *)t->target_storage;
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if (((options_req[OPTR_ENUM].val & FLASH_OPTR_RDP_MASK) ==
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(uint32_t)0xCC) &&
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!ps->irreversible_enabled) {
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if ((options_req[OPTR_ENUM].val & FLASH_OPTR_RDP_MASK) == 0xccU && !ps->irreversible_enabled) {
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tc_printf(t, "Irreversible operations disabled\n");
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return false;
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}
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return true;
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}
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static void display_registers(target *t, const struct registers_s *reg_def,
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uint8_t len)
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static void display_registers(target *t, const struct registers_s *reg_def, const size_t len)
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{
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uint32_t val = 0U;
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for (uint8_t i = 0U; i < len; i++) {
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val = target_mem_read32(t, reg_def[i].addr);
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for (size_t i = 0; i < len; i++) {
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const uint32_t val = target_mem_read32(t, reg_def[i].addr);
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tc_printf(t, "0x%08X: 0x%08X\n", reg_def[i].addr, val);
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}
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}
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@ -709,15 +688,13 @@ static void display_registers(target *t, const struct registers_s *reg_def,
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*/
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static bool stm32g0_cmd_option(target *t, int argc, const char **argv)
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{
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struct registers_s options_req[NB_REG_OPT] = { { 0U, 0U } };
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struct registers_s options_req[NB_REG_OPT] = {{0U, 0U}};
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if ((argc == 2) && !strcmp(argv[1], "erase")) {
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if (argc == 2 && !strcmp(argv[1], "erase")) {
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if (!stm32g0_option_write(t, options_def))
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goto exit_error;
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} else if ((argc > 2) && (argc % 2U == 0U) &&
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!strcmp(argv[1], "write")) {
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if (!parse_cmdline_registers(argc - 2, argv + 2, options_req,
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options_def, NB_REG_OPT))
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} else if ((argc > 2) && (argc % 2U == 0U) && !strcmp(argv[1], "write")) {
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if (!parse_cmdline_registers((uint32_t)argc - 2U, argv + 2U, options_req, options_def, NB_REG_OPT))
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goto exit_error;
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if (!validate_options(t, options_req))
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goto exit_error;
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@ -741,15 +718,13 @@ exit_error:
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*/
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static bool stm32g0_cmd_irreversible(target *t, int argc, const char **argv)
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{
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struct stm32g0_priv_s *ps = (struct stm32g0_priv_s*)t->target_storage;
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struct stm32g0_priv_s *ps = (struct stm32g0_priv_s *)t->target_storage;
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bool ret = true;
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if (argc == 2) {
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if (!parse_enable_or_disable(argv[1],
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&(ps->irreversible_enabled)))
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if (!parse_enable_or_disable(argv[1], &(ps->irreversible_enabled)))
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ret = false;
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}
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tc_printf(t, "Irreversible operations: %s\n",
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ps->irreversible_enabled ? "enabled" : "disabled");
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tc_printf(t, "Irreversible operations: %s\n", ps->irreversible_enabled ? "enabled" : "disabled");
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return ret;
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}
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