Adiv5: Print Designer/Partno when device is not recognized

t->idcode is now 16 bit.

src/command.c

@@ -257,9 +257,18 @@ bool cmd_swdp_scan(target *t, int argc, char **argv)
 static void display_target(int i, target *t, void *context)
 {
 	(void)context;
-	gdb_outf("%2d   %c  %s %s\n", i, target_attached(t)?'*':' ',
+	if (!strcmp(target_driver_name(t), "ARM Cortex-M")) {
-			 target_driver_name(t),
+		gdb_outf("***%2d%sUnknown %s Designer %3x Partno %3x %s\n",
-			 (target_core_name(t)) ? target_core_name(t): "");
+				 i, target_attached(t)?" * ":" ",
+				 target_driver_name(t),
+				 target_designer(t),
+				 target_idcode(t),
+				 (target_core_name(t)) ? target_core_name(t): "");
+	} else {
+		gdb_outf("%2d   %c  %s %s\n", i, target_attached(t)?'*':' ',
+				 target_driver_name(t),
+				 (target_core_name(t)) ? target_core_name(t): "");
+	}
 }
 
 bool cmd_targets(target *t, int argc, char **argv)

src/include/target.h

@@ -51,6 +51,8 @@ void target_detach(target *t);
 bool target_attached(target *t);
 const char *target_driver_name(target *t);
 const char *target_core_name(target *t);
+unsigned int target_designer(target *t);
+unsigned int target_idcode(target *t);
 
 /* Memory access functions */
 bool target_mem_map(target *t, char *buf, size_t len);

src/platforms/pc/cl_utils.c

@@ -265,9 +265,18 @@ void cl_init(BMP_CL_OPTIONS_t *opt, int argc, char **argv)
 static void display_target(int i, target *t, void *context)
 {
 	(void)context;
-	DEBUG_INFO("*** %2d   %c  %s %s\n", i, target_attached(t)?'*':' ',
+	if (!strcmp(target_driver_name(t), "ARM Cortex-M")) {
-		  target_driver_name(t),
+		DEBUG_INFO("***%2d%sUnknown %s Designer %3x Partno %3x %s\n",
-		  (target_core_name(t)) ? target_core_name(t): "");
+			  i, target_attached(t)?" * ":" ",
+			  target_driver_name(t),
+			  target_designer(t),
+			  target_idcode(t),
+			  (target_core_name(t)) ? target_core_name(t): "");
+	} else {
+		DEBUG_INFO("*** %2d   %c  %s %s\n", i, target_attached(t)?'*':' ',
+			  target_driver_name(t),
+			  (target_core_name(t)) ? target_core_name(t): "");
+	}
 }
 
 int cl_execute(BMP_CL_OPTIONS_t *opt)

src/target/adiv5.c

@@ -198,7 +198,10 @@ static const struct {
 	{0x00d, 0x00, 0,      aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("CoreSight ETM11", "(Embedded Trace)")},
 	{0x00e, 0x00, 0,      aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-M7 FBP",  "(Flash Patch and Breakpoint)")},
 	{0x101, 0x00, 0,      aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("System TSGEN",   "(Time Stamp Generator)")},
+	{0x471, 0x00, 0,      aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-M0  ROM",  "(Cortex-M0 ROM)")},
 	{0x490, 0x00, 0,      aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-A15 GIC", "(Generic Interrupt Controller)")},
+	{0x4c0, 0x00, 0,      aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-M0+ ROM",  "(Cortex-M0+ ROM)")},
+	{0x4c4, 0x00, 0,      aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-M4 ROM",  "(Cortex-M4 ROM)")},
 	{0x4c7, 0x00, 0,      aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-M7 PPB",  "(Private Peripheral Bus ROM Table)")},
 	{0x906, 0x14, 0,      aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("CoreSight CTI",  "(Cross Trigger)")},
 	{0x907, 0x00, 0,      aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("CoreSight ETB",  "(Trace Buffer)")},
@@ -444,8 +447,8 @@ static bool adiv5_component_probe(ADIv5_AP_t *ap, uint32_t addr, int recursion,
 			DEBUG_WARN("Fault reading ROM table entry\n");
 		}
 
-		DEBUG_INFO("ROM: Table BASE=0x%" PRIx32 " SYSMEM=0x%" PRIx32 ", designer %3"
+		DEBUG_INFO("ROM: Table BASE=0x%" PRIx32 " SYSMEM=0x%08" PRIx32
-			  PRIx32 " Partno %3" PRIx32 "\n", addr, memtype, designer,
+				   ", designer %3x Partno %3x\n", addr, memtype, designer,
 			  partno);
 #endif
 		if (recursion == 0) {

src/target/cortexm.c

@@ -273,6 +273,8 @@ bool cortexm_probe(ADIv5_AP_t *ap)
 	}
 
 	adiv5_ap_ref(ap);
+	t->t_designer = ap->ap_designer;
+	t->idcode     = ap->ap_partno;
 	struct cortexm_priv *priv = calloc(1, sizeof(*priv));
 	if (!priv) {			/* calloc failed: heap exhaustion */
 		DEBUG_WARN("calloc: failed in %s\n", __func__);
@@ -370,7 +372,6 @@ bool cortexm_probe(ADIv5_AP_t *ap)
 	} else {
 		target_check_error(t);
 	}
-
 #define PROBE(x) \
 	do { if ((x)(t)) {target_halt_resume(t, 0); return true;} else target_check_error(t); } while (0)
 

src/target/nrf51.c

@@ -132,7 +132,6 @@ bool nrf51_probe(target *t)
 	if ((info_part != 0xffffffff) && (info_part != 0) &&
 		((info_part & 0x00ff000) == 0x52000)) {
 		uint32_t ram_size = target_mem_read32(t, NRF52_INFO_RAM);
-		t->idcode = info_part;
 		t->driver = "Nordic nRF52";
 		t->target_options |= CORTEXM_TOPT_INHIBIT_SRST;
 		target_add_ram(t, 0x20000000, ram_size * 1024);

src/target/sam3x.c

@@ -170,9 +170,9 @@ static void sam4_add_flash(target *t,
 	target_add_flash(t, f);
 }
 
-static size_t sam_flash_size(uint32_t idcode)
+static size_t sam_flash_size(uint32_t cidr)
 {
-	switch (idcode & CHIPID_CIDR_NVPSIZ_MASK) {
+	switch (cidr & CHIPID_CIDR_NVPSIZ_MASK) {
 	case CHIPID_CIDR_NVPSIZ_8K:
 		return 0x2000;
 	case CHIPID_CIDR_NVPSIZ_16K:
@@ -197,9 +197,9 @@ static size_t sam_flash_size(uint32_t idcode)
 
 bool sam3x_probe(target *t)
 {
-	t->idcode = target_mem_read32(t, SAM3X_CHIPID_CIDR);
+	uint32_t cidr = target_mem_read32(t, SAM3X_CHIPID_CIDR);
-	size_t size = sam_flash_size(t->idcode);
+	size_t size = sam_flash_size(cidr);
-	switch (t->idcode & (CHIPID_CIDR_ARCH_MASK | CHIPID_CIDR_EPROC_MASK)) {
+	switch (cidr & (CHIPID_CIDR_ARCH_MASK | CHIPID_CIDR_EPROC_MASK)) {
 	case CHIPID_CIDR_ARCH_SAM3XxC | CHIPID_CIDR_EPROC_CM3:
 	case CHIPID_CIDR_ARCH_SAM3XxE | CHIPID_CIDR_EPROC_CM3:
 	case CHIPID_CIDR_ARCH_SAM3XxG | CHIPID_CIDR_EPROC_CM3:
@@ -212,9 +212,9 @@ bool sam3x_probe(target *t)
 		return true;
 	}
 
-	t->idcode = target_mem_read32(t, SAM34NSU_CHIPID_CIDR);
+	cidr = target_mem_read32(t, SAM34NSU_CHIPID_CIDR);
-	size = sam_flash_size(t->idcode);
+	size = sam_flash_size(cidr);
-	switch (t->idcode & (CHIPID_CIDR_ARCH_MASK | CHIPID_CIDR_EPROC_MASK)) {
+	switch (cidr & (CHIPID_CIDR_ARCH_MASK | CHIPID_CIDR_EPROC_MASK)) {
 	case CHIPID_CIDR_ARCH_SAM3NxA | CHIPID_CIDR_EPROC_CM3:
 	case CHIPID_CIDR_ARCH_SAM3NxB | CHIPID_CIDR_EPROC_CM3:
 	case CHIPID_CIDR_ARCH_SAM3NxC | CHIPID_CIDR_EPROC_CM3:
@@ -224,7 +224,7 @@ bool sam3x_probe(target *t)
 		t->driver = "Atmel SAM3N/S";
 		target_add_ram(t, 0x20000000, 0x200000);
 		/* These devices only have a single bank */
-		size = sam_flash_size(t->idcode);
+		size = sam_flash_size(cidr);
 		sam3_add_flash(t, SAM3N_EEFC_BASE, 0x400000, size);
 		target_add_commands(t, sam3x_cmd_list, "SAM3N/S");
 		return true;
@@ -248,7 +248,7 @@ bool sam3x_probe(target *t)
 	case CHIPID_CIDR_ARCH_SAM4SDC | CHIPID_CIDR_EPROC_CM4:
 		t->driver = "Atmel SAM4S";
 		target_add_ram(t, 0x20000000, 0x400000);
-		size_t size = sam_flash_size(t->idcode);
+		size_t size = sam_flash_size(cidr);
 		if (size <= 0x80000) {
 			/* Smaller devices have a single bank */
 			sam4_add_flash(t, SAM4S_EEFC_BASE(0), 0x400000, size);

src/target/sam4l.c

@@ -186,13 +186,13 @@ static void sam4l_add_flash(target *t, uint32_t addr, size_t length)
 }
 
 /* Return size of RAM */
-static size_t sam_ram_size(uint32_t idcode) {
+static size_t sam_ram_size(uint32_t cidr) {
-	return __ram_size[((idcode >> CHIPID_CIDR_SRAMSIZ_SHIFT) & CHIPID_CIDR_SRAMSIZ_MASK)];
+	return __ram_size[((cidr >> CHIPID_CIDR_SRAMSIZ_SHIFT) & CHIPID_CIDR_SRAMSIZ_MASK)];
 }
 
 /* Return size of FLASH */
-static size_t sam_nvp_size(uint32_t idcode) {
+static size_t sam_nvp_size(uint32_t cidr) {
-	return __nvp_size[((idcode >> CHIPID_CIDR_NVPSIZ_SHIFT) & CHIPID_CIDR_NVPSIZ_MASK)];
+	return __nvp_size[((cidr >> CHIPID_CIDR_NVPSIZ_SHIFT) & CHIPID_CIDR_NVPSIZ_MASK)];
 }
 
 #define SMAP_BASE	0x400a3000
@@ -228,14 +228,14 @@ bool sam4l_probe(target *t)
 {
 	size_t	ram_size, flash_size;
 
-	t->idcode = target_mem_read32(t, SAM4L_CHIPID_CIDR);
+	uint32_t cidr = target_mem_read32(t, SAM4L_CHIPID_CIDR);
-	if (((t->idcode >> CHIPID_CIDR_ARCH_SHIFT) & CHIPID_CIDR_ARCH_MASK) == SAM4L_ARCH) {
+	if (((cidr >> CHIPID_CIDR_ARCH_SHIFT) & CHIPID_CIDR_ARCH_MASK) == SAM4L_ARCH) {
 		t->driver = "Atmel SAM4L";
 		/* this function says we need to do "extra" stuff after reset */
 		t->extended_reset = sam4l_extended_reset;
-		ram_size = sam_ram_size(t->idcode);
+		ram_size = sam_ram_size(cidr);
 		target_add_ram(t, 0x20000000, ram_size);
-		flash_size = sam_nvp_size(t->idcode);
+		flash_size = sam_nvp_size(cidr);
 		sam4l_add_flash(t, 0x0, flash_size);
 		DEBUG_INFO("\nSAM4L: RAM = 0x%x (%dK), FLASH = 0x%x (%dK)\n",
 			(unsigned int) ram_size, (unsigned int) (ram_size / 1024),

src/target/target.c

@@ -502,6 +502,16 @@ const char *target_core_name(target *t)
 	return t->core;
 }
 
+unsigned int target_designer(target *t)
+{
+	return t->t_designer;
+}
+
+unsigned int target_idcode(target *t)
+{
+	return t->idcode;
+}
+
 uint32_t target_mem_read32(target *t, uint32_t addr)
 {
 	uint32_t ret;

src/target/target_internal.h

@@ -111,7 +111,8 @@ struct target_s {
 
 	/* target-defined options */
 	unsigned target_options;
-	uint32_t idcode;
+	uint16_t t_designer;
+	uint16_t idcode;
 	uint32_t target_storage;
 
 	struct target_ram *ram;