ADIv5 structural changes.
- Probe ROM table - Mem-AP no longer pretends to be a target - AP no longer provides priv pointer
This commit is contained in:
Gareth McMullin
parent
8d9d6f692c
commit
459bae4ea1
162
src/adiv5.c
162
src/adiv5.c
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@ -20,27 +20,24 @@
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/* This file implements the transport generic functions of the
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* ARM Debug Interface v5 Architecure Specification, ARM doc IHI0031A.
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*
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* Issues:
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* Currently doesn't use ROM table for introspection, just assumes
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* the device is Cortex-M3.
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*/
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#include "general.h"
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#include "jtag_scan.h"
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#include "gdb_packet.h"
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#include "adiv5.h"
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#include "target.h"
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#include "cortexm.h"
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#ifndef DO_RESET_SEQ
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#define DO_RESET_SEQ 0
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#endif
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static const char adiv5_driver_str[] = "ARM ADIv5 MEM-AP";
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/* ROM table CIDR values */
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#define CIDR_ROM_TABLE 0xb105100d
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#define CIDR_GENERIC_IP 0xb105e00d
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static bool ap_check_error(target *t);
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static void ap_mem_read(target *t, void *dest, uint32_t src, size_t len);
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static void ap_mem_write(target *t, uint32_t dest, const void *src, size_t len);
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#define PIDR_REV_MASK 0x0FFF00000ULL
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#define PIDR_ARMv7M 0x4000BB000ULL
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#define PIDR_ARMv7MF 0x4000BB00CULL
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void adiv5_dp_ref(ADIv5_DP_t *dp)
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{
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@ -62,8 +59,6 @@ void adiv5_ap_unref(ADIv5_AP_t *ap)
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{
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if (--(ap->refcnt) == 0) {
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adiv5_dp_unref(ap->dp);
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if (ap->priv)
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ap->priv_free(ap->priv);
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free(ap);
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}
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}
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@ -73,6 +68,91 @@ void adiv5_dp_write(ADIv5_DP_t *dp, uint16_t addr, uint32_t value)
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dp->low_access(dp, ADIV5_LOW_WRITE, addr, value);
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}
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static uint32_t adiv5_mem_read32(ADIv5_AP_t *ap, uint32_t addr)
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{
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uint32_t ret;
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adiv5_mem_read(ap, &ret, addr, sizeof(ret));
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return ret;
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}
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static void adiv5_component_probe(ADIv5_AP_t *ap, uint32_t addr)
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{
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addr &= ~3;
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uint64_t pidr = 0;
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uint32_t cidr = 0;
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for (int i = 0; i < 4; i++) {
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uint32_t x = adiv5_mem_read32(ap, addr + 0xfe0 + 4*i);
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pidr |= (x & 0xff) << (i * 8);
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}
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pidr |= (uint64_t)adiv5_mem_read32(ap, addr + 0xfd0) << 32;
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for (int i = 0; i < 4; i++) {
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uint32_t x = adiv5_mem_read32(ap, addr + 0xff0 + 4*i);
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cidr |= ((uint64_t)(x & 0xff)) << (i * 8);
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}
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switch (cidr) {
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case CIDR_ROM_TABLE: /* This is a ROM table, probe recursively */
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for (int i = 0; i < 256; i++) {
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uint32_t entry = adiv5_mem_read32(ap, addr + i*4);
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if (entry == 0)
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break;
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if ((entry & 1) == 0)
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continue;
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adiv5_component_probe(ap, addr + (entry & ~0xfff));
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}
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break;
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case CIDR_GENERIC_IP:
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switch (pidr & ~PIDR_REV_MASK) {
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case PIDR_ARMv7MF:
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case PIDR_ARMv7M:
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cortexm_probe(ap);
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break;
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}
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break;
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}
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}
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ADIv5_AP_t *adiv5_new_ap(ADIv5_DP_t *dp, uint8_t apsel)
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{
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ADIv5_AP_t *ap, tmpap;
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/* Assume valid and try to read IDR */
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memset(&tmpap, 0, sizeof(tmpap));
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tmpap.dp = dp;
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tmpap.apsel = apsel;
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tmpap.idr = adiv5_ap_read(&tmpap, ADIV5_AP_IDR);
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if(!tmpap.idr) /* IDR Invalid - Should we not continue here? */
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return NULL;
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/* Check for ARM Mem-AP */
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uint16_t mfg = (tmpap.idr >> 17) & 0x3ff;
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uint8_t cls = (tmpap.idr >> 13) & 0xf;
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uint8_t type = tmpap.idr & 0xf;
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if (mfg != 0x23B) /* Ditch if not ARM */
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return NULL;
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if ((cls != 8) || (type == 0)) /* Ditch if not Mem-AP */
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return NULL;
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/* It's valid to so create a heap copy */
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ap = malloc(sizeof(*ap));
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memcpy(ap, &tmpap, sizeof(*ap));
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adiv5_dp_ref(dp);
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ap->cfg = adiv5_ap_read(ap, ADIV5_AP_CFG);
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ap->base = adiv5_ap_read(ap, ADIV5_AP_BASE);
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ap->csw = adiv5_ap_read(ap, ADIV5_AP_CSW) &
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~(ADIV5_AP_CSW_SIZE_MASK | ADIV5_AP_CSW_ADDRINC_MASK);
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DEBUG("%3d: IDR=%08X CFG=%08X BASE=%08X CSW=%08X\n",
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apsel, ap->idr, ap->cfg, ap->base, ap->csw);
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return ap;
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}
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void adiv5_dp_init(ADIv5_DP_t *dp)
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{
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uint32_t ctrlstat;
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@ -113,56 +193,26 @@ void adiv5_dp_init(ADIv5_DP_t *dp)
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/* Probe for APs on this DP */
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for(int i = 0; i < 256; i++) {
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ADIv5_AP_t *ap, tmpap;
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target *t;
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ADIv5_AP_t *ap = adiv5_new_ap(dp, i);
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if (ap == NULL)
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continue;
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/* Assume valid and try to read IDR */
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memset(&tmpap, 0, sizeof(tmpap));
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tmpap.dp = dp;
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tmpap.apsel = i;
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tmpap.idr = adiv5_ap_read(&tmpap, ADIV5_AP_IDR);
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if(!tmpap.idr) /* IDR Invalid - Should we not continue here? */
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break;
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/* It's valid to so create a heap copy */
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ap = malloc(sizeof(*ap));
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memcpy(ap, &tmpap, sizeof(*ap));
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adiv5_dp_ref(dp);
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ap->cfg = adiv5_ap_read(ap, ADIV5_AP_CFG);
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ap->base = adiv5_ap_read(ap, ADIV5_AP_BASE);
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ap->csw = adiv5_ap_read(ap, ADIV5_AP_CSW) &
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~(ADIV5_AP_CSW_SIZE_MASK | ADIV5_AP_CSW_ADDRINC_MASK);
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if (ap->base == 0xffffffff) {
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/* No debug entries... useless AP */
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adiv5_ap_unref(ap);
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continue;
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}
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/* Should probe further here to make sure it's a valid target.
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* AP should be unref'd if not valid.
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*/
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/* Prepend to target list... */
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t = target_new(sizeof(*t));
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adiv5_ap_ref(ap);
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t->priv = ap;
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t->priv_free = (void (*)(void *))adiv5_ap_unref;
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t->driver = adiv5_driver_str;
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t->check_error = ap_check_error;
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t->mem_read = ap_mem_read;
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t->mem_write = ap_mem_write;
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/* The rest sould only be added after checking ROM table */
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cortexm_probe(t);
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adiv5_component_probe(ap, ap->base);
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}
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adiv5_dp_unref(dp);
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}
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static bool ap_check_error(target *t)
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{
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ADIv5_AP_t *ap = adiv5_target_ap(t);
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return adiv5_dp_error(ap->dp) != 0;
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}
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enum align {
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ALIGN_BYTE = 0,
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ALIGN_HALFWORD = 1,
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@ -208,10 +258,9 @@ static void * extract(void *dest, uint32_t src, uint32_t val, enum align align)
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return (uint8_t *)dest + (1 << align);
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}
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static void
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ap_mem_read(target *t, void *dest, uint32_t src, size_t len)
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void
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adiv5_mem_read(ADIv5_AP_t *ap, void *dest, uint32_t src, size_t len)
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{
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ADIv5_AP_t *ap = adiv5_target_ap(t);
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uint32_t tmp;
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uint32_t osrc = src;
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enum align align = MIN(ALIGNOF(src), ALIGNOF(len));
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@ -237,10 +286,9 @@ ap_mem_read(target *t, void *dest, uint32_t src, size_t len)
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extract(dest, src, tmp, align);
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}
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static void
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ap_mem_write(target *t, uint32_t dest, const void *src, size_t len)
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void
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adiv5_mem_write(ADIv5_AP_t *ap, uint32_t dest, const void *src, size_t len)
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{
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ADIv5_AP_t *ap = adiv5_target_ap(t);
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uint32_t odest = dest;
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enum align align = MIN(ALIGNOF(dest), ALIGNOF(len));
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@ -82,6 +82,7 @@ static int cortexm_hostio_request(target *t);
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static void cortexm_hostio_reply(target *t, int32_t retcode, uint32_t errcode);
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struct cortexm_priv {
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ADIv5_AP_t *ap;
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bool stepping;
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bool on_bkpt;
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/* Watchpoint unit status */
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@ -197,8 +198,48 @@ static const char tdesc_cortex_mf[] =
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" </feature>"
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"</target>";
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bool cortexm_probe(target *t)
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ADIv5_AP_t *cortexm_ap(target *t)
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{
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return ((struct cortexm_priv *)t->priv)->ap;
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}
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static void cortexm_mem_read(target *t, void *dest, uint32_t src, size_t len)
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{
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adiv5_mem_read(cortexm_ap(t), dest, src, len);
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}
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static void cortexm_mem_write(target *t, uint32_t dest, const void *src, size_t len)
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{
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adiv5_mem_write(cortexm_ap(t), dest, src, len);
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}
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static bool cortexm_check_error(target *t)
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{
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ADIv5_AP_t *ap = cortexm_ap(t);
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return adiv5_dp_error(ap->dp) != 0;
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}
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static void cortexm_priv_free(void *priv)
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{
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adiv5_ap_unref(((struct cortexm_priv *)priv)->ap);
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free(priv);
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}
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bool cortexm_probe(ADIv5_AP_t *ap)
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{
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target *t;
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t = target_new(sizeof(*t));
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adiv5_ap_ref(ap);
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struct cortexm_priv *priv = calloc(1, sizeof(*priv));
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t->priv = priv;
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t->priv_free = cortexm_priv_free;
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priv->ap = ap;
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t->check_error = cortexm_check_error;
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t->mem_read = cortexm_mem_read;
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t->mem_write = cortexm_mem_write;
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t->driver = cortexm_driver_str;
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t->attach = cortexm_attach;
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@ -229,11 +270,6 @@ bool cortexm_probe(target *t)
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t->tdesc = tdesc_cortex_mf;
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}
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ADIv5_AP_t *ap = adiv5_target_ap(t);
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struct cortexm_priv *priv = calloc(1, sizeof(*priv));
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ap->priv = priv;
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ap->priv_free = free;
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/* Default vectors to catch */
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priv->demcr = CORTEXM_DEMCR_TRCENA | CORTEXM_DEMCR_VC_HARDERR |
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CORTEXM_DEMCR_VC_CORERESET;
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@ -260,8 +296,7 @@ bool cortexm_probe(target *t)
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bool cortexm_attach(target *t)
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{
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ADIv5_AP_t *ap = adiv5_target_ap(t);
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struct cortexm_priv *priv = ap->priv;
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struct cortexm_priv *priv = t->priv;
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unsigned i;
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uint32_t r;
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int tries;
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@ -323,8 +358,7 @@ bool cortexm_attach(target *t)
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void cortexm_detach(target *t)
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{
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ADIv5_AP_t *ap = adiv5_target_ap(t);
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struct cortexm_priv *priv = ap->priv;
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struct cortexm_priv *priv = t->priv;
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unsigned i;
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/* Clear any stale breakpoints */
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@ -343,7 +377,7 @@ enum { DB_DHCSR, DB_DCRSR, DB_DCRDR, DB_DEMCR };
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static void cortexm_regs_read(target *t, void *data)
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{
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ADIv5_AP_t *ap = adiv5_target_ap(t);
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ADIv5_AP_t *ap = cortexm_ap(t);
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uint32_t *regs = data;
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unsigned i;
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@ -374,7 +408,7 @@ static void cortexm_regs_read(target *t, void *data)
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static void cortexm_regs_write(target *t, const void *data)
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{
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ADIv5_AP_t *ap = adiv5_target_ap(t);
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ADIv5_AP_t *ap = cortexm_ap(t);
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const uint32_t *regs = data;
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unsigned i;
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@ -459,8 +493,7 @@ static void cortexm_halt_request(target *t)
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static int cortexm_halt_wait(target *t)
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{
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ADIv5_AP_t *ap = adiv5_target_ap(t);
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struct cortexm_priv *priv = ap->priv;
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struct cortexm_priv *priv = t->priv;
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volatile uint32_t dhcsr = 0;
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volatile struct exception e;
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@ -521,8 +554,7 @@ static int cortexm_halt_wait(target *t)
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void cortexm_halt_resume(target *t, bool step)
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{
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ADIv5_AP_t *ap = adiv5_target_ap(t);
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struct cortexm_priv *priv = ap->priv;
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struct cortexm_priv *priv = t->priv;
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uint32_t dhcsr = CORTEXM_DHCSR_DBGKEY | CORTEXM_DHCSR_C_DEBUGEN;
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if (step)
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@ -639,8 +671,7 @@ int cortexm_run_stub(target *t, uint32_t loadaddr,
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static int cortexm_set_hw_bp(target *t, uint32_t addr)
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{
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ADIv5_AP_t *ap = adiv5_target_ap(t);
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struct cortexm_priv *priv = ap->priv;
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struct cortexm_priv *priv = t->priv;
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uint32_t val = addr;
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unsigned i;
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@ -664,8 +695,7 @@ static int cortexm_set_hw_bp(target *t, uint32_t addr)
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static int cortexm_clear_hw_bp(target *t, uint32_t addr)
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{
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ADIv5_AP_t *ap = adiv5_target_ap(t);
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struct cortexm_priv *priv = ap->priv;
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struct cortexm_priv *priv = t->priv;
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unsigned i;
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for(i = 0; i < priv->hw_breakpoint_max; i++)
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@ -686,8 +716,7 @@ static int cortexm_clear_hw_bp(target *t, uint32_t addr)
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static int
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cortexm_set_hw_wp(target *t, uint8_t type, uint32_t addr, uint8_t len)
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{
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ADIv5_AP_t *ap = adiv5_target_ap(t);
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struct cortexm_priv *priv = ap->priv;
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struct cortexm_priv *priv = t->priv;
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unsigned i;
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switch(len) { /* Convert bytes size to mask size */
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@ -728,8 +757,7 @@ cortexm_set_hw_wp(target *t, uint8_t type, uint32_t addr, uint8_t len)
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static int
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cortexm_clear_hw_wp(target *t, uint8_t type, uint32_t addr, uint8_t len)
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{
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ADIv5_AP_t *ap = adiv5_target_ap(t);
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struct cortexm_priv *priv = ap->priv;
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struct cortexm_priv *priv = t->priv;
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unsigned i;
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switch(len) {
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@ -764,8 +792,7 @@ cortexm_clear_hw_wp(target *t, uint8_t type, uint32_t addr, uint8_t len)
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static int cortexm_check_hw_wp(target *t, uint32_t *addr)
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{
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ADIv5_AP_t *ap = adiv5_target_ap(t);
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struct cortexm_priv *priv = ap->priv;
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struct cortexm_priv *priv = t->priv;
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unsigned i;
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for(i = 0; i < priv->hw_watchpoint_max; i++)
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@ -783,8 +810,7 @@ static int cortexm_check_hw_wp(target *t, uint32_t *addr)
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static bool cortexm_vector_catch(target *t, int argc, char *argv[])
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{
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ADIv5_AP_t *ap = adiv5_target_ap(t);
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struct cortexm_priv *priv = ap->priv;
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struct cortexm_priv *priv = t->priv;
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const char *vectors[] = {"reset", NULL, NULL, NULL, "mm", "nocp",
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"chk", "stat", "bus", "int", "hard"};
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uint32_t tmp = 0;
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@ -862,8 +888,7 @@ static bool cortexm_vector_catch(target *t, int argc, char *argv[])
|
|||
|
||||
static int cortexm_hostio_request(target *t)
|
||||
{
|
||||
ADIv5_AP_t *ap = adiv5_target_ap(t);
|
||||
struct cortexm_priv *priv = ap->priv;
|
||||
struct cortexm_priv *priv = t->priv;
|
||||
uint32_t arm_regs[t->regs_size];
|
||||
uint32_t params[4];
|
||||
|
||||
|
|
@ -964,8 +989,7 @@ static int cortexm_hostio_request(target *t)
|
|||
|
||||
static void cortexm_hostio_reply(target *t, int32_t retcode, uint32_t errcode)
|
||||
{
|
||||
ADIv5_AP_t *ap = adiv5_target_ap(t);
|
||||
struct cortexm_priv *priv = ap->priv;
|
||||
struct cortexm_priv *priv = t->priv;
|
||||
uint32_t arm_regs[t->regs_size];
|
||||
|
||||
DEBUG("syscall return ret=%d errno=%d\n", retcode, errcode);
|
||||
|
|
|
|||
|
|
@ -252,7 +252,7 @@ char variant_string[40];
|
|||
bool efm32_probe(target *t)
|
||||
{
|
||||
/* Read the IDCODE register from the SW-DP */
|
||||
ADIv5_AP_t *ap = adiv5_target_ap(t);
|
||||
ADIv5_AP_t *ap = cortexm_ap(t);
|
||||
uint32_t ap_idcode = ap->dp->idcode;
|
||||
|
||||
/* Check the idcode is silabs. See AN0062 Section 2.2 */
|
||||
|
|
|
|||
|
|
@ -22,7 +22,6 @@
|
|||
#define __ADIV5_H
|
||||
|
||||
#include "jtag_scan.h"
|
||||
#include "target.h"
|
||||
|
||||
#define ADIV5_APnDP 0x100
|
||||
#define ADIV5_DP_REG(x) (x)
|
||||
|
|
@ -144,14 +143,12 @@ typedef struct ADIv5_AP_s {
|
|||
uint32_t cfg;
|
||||
uint32_t base;
|
||||
uint32_t csw;
|
||||
|
||||
void *priv;
|
||||
void (*priv_free)(void *);
|
||||
} ADIv5_AP_t;
|
||||
|
||||
void adiv5_dp_init(ADIv5_DP_t *dp);
|
||||
void adiv5_dp_write(ADIv5_DP_t *dp, uint16_t addr, uint32_t value);
|
||||
|
||||
ADIv5_AP_t *adiv5_new_ap(ADIv5_DP_t *dp, uint8_t apsel);
|
||||
void adiv5_dp_ref(ADIv5_DP_t *dp);
|
||||
void adiv5_ap_ref(ADIv5_AP_t *ap);
|
||||
void adiv5_dp_unref(ADIv5_DP_t *dp);
|
||||
|
|
@ -163,10 +160,8 @@ uint32_t adiv5_ap_read(ADIv5_AP_t *ap, uint16_t addr);
|
|||
void adiv5_jtag_dp_handler(jtag_dev_t *dev);
|
||||
int adiv5_swdp_scan(void);
|
||||
|
||||
static inline ADIv5_AP_t *adiv5_target_ap(target *target)
|
||||
{
|
||||
return target->priv;
|
||||
}
|
||||
void adiv5_mem_read(ADIv5_AP_t *ap, void *dest, uint32_t src, size_t len);
|
||||
void adiv5_mem_write(ADIv5_AP_t *ap, uint32_t dest, const void *src, size_t len);
|
||||
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -20,6 +20,7 @@
|
|||
#define __CORTEXM_H
|
||||
|
||||
#include "target.h"
|
||||
#include "adiv5.h"
|
||||
|
||||
/* Private peripheral bus base address */
|
||||
#define CORTEXM_PPB_BASE 0xE0000000
|
||||
|
|
@ -155,6 +156,9 @@
|
|||
|
||||
#define CORTEXM_TOPT_INHIBIT_SRST (1 << 2)
|
||||
|
||||
bool cortexm_probe(ADIv5_AP_t *ap);
|
||||
ADIv5_AP_t *cortexm_ap(target *t);
|
||||
|
||||
bool cortexm_attach(target *t);
|
||||
void cortexm_detach(target *t);
|
||||
void cortexm_halt_resume(target *t, bool step);
|
||||
|
|
|
|||
|
|
@ -257,7 +257,6 @@ static inline void target_mem_write8(target *t, uint32_t addr, uint8_t value)
|
|||
/* Probe for various targets.
|
||||
* Actual functions implemented in their respective drivers.
|
||||
*/
|
||||
bool cortexm_probe(target *t);
|
||||
bool stm32f1_probe(target *t);
|
||||
bool stm32f4_probe(target *t);
|
||||
bool stm32l0_probe(target *t);
|
||||
|
|
|
|||
|
|
@ -28,6 +28,7 @@
|
|||
#include "morse.h"
|
||||
#include "jtag_scan.h"
|
||||
#include "gdb_packet.h"
|
||||
#include "target.h"
|
||||
#include "adiv5.h"
|
||||
#include "arm7tdmi.h"
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue