SAM4L: Add target driver for SAM4L
This commit adds a target driver for SAM4L and it depends on the extended reset change.
This commit is contained in:
Chuck McManis
parent
0aef6c6774
commit
469ecbf0f9
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@ -103,8 +103,9 @@
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/* Flash General Purpose Registers (low) */
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#define FLASHCALW_FGPFRLO (FLASHCALW_BASE + 0x18)
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static int sam4_flash_erase(struct target_flash *f, target_addr addr, size_t len);
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int sam4_flash_write(struct target_flash *f, target_addr dest,
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static void sam4l_extended_reset(target *t);
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static int sam4l_flash_erase(struct target_flash *f, target_addr addr, size_t len);
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static int sam4l_flash_write_buf(struct target_flash *f, target_addr dest,
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const void *src, size_t len);
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const struct command_s sam4l_cmds[] = {
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@ -171,18 +172,17 @@ static const size_t __nvp_size[16] = {
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* Populate a target_flash struct with the necessary function pointers
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* and constants to describe our flash.
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*/
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static void sam4_add_flash(target *t, uint32_t addr, size_t length)
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static void sam4l_add_flash(target *t, uint32_t addr, size_t length)
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{
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struct target_flash *f = calloc(1, sizeof(struct target_flash));
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f->start = addr;
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f->length = length;
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f->blocksize = 512;
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f->erase = sam4_flash_erase;
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f->erase = sam4l_flash_erase;
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f->write = target_flash_write_buffered;
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f->done = target_flash_done_buffered;
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f->write_buf = sam4_flash_write;
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f->write_buf = sam4l_flash_write_buf;
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f->buf_size = 512;;
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f->align = 512;
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f->erased = 0xff;
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/* add it into the target structures flash chain */
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target_add_flash(t, f);
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@ -220,7 +220,6 @@ static size_t sam_nvp_size(uint32_t idcode) {
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#define SMAP_EXTID (SMAP_BASE + 0xf4)
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#define SMAP_IDR (SMAP_BASE + 0xfc)
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static void sam4l_reset(target *t);
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/*
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* The probe function, look where the CIDR register should be, see if
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@ -230,37 +229,29 @@ static void sam4l_reset(target *t);
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*/
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bool sam4l_probe(target *t)
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{
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uint32_t reg;
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size_t ram_size, flash_size;
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DEBUG("\nSAM4L: Probe function called\n");
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t->idcode = target_mem_read32(t, SAM4L_CHIPID_CIDR);
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if (((t->idcode >> CHIPID_CIDR_ARCH_SHIFT) & CHIPID_CIDR_ARCH_MASK) == SAM4L_ARCH) {
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t->driver = "Atmel SAM4L";
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/* Check to see if our extended reset will fix this */
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#ifdef SAM4_DISABLE_SRST
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/* Check to see if our extended reset will fix this */
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t->target_options |= CORTEXM_TOPT_INHIBIT_SRST;
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#endif
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/* this option says we need to do "extra" stuff after reset */
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t->target_options |= CORTEXM_TOPT_EXTENDED_RESET;
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t->extended_reset = sam4l_reset;
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t->extended_reset = sam4l_extended_reset;
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ram_size = sam_ram_size(t->idcode);
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target_add_ram(t, 0x20000000, ram_size);
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flash_size = sam_nvp_size(t->idcode);
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sam4_add_flash(t, 0x0, flash_size);
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sam4l_add_flash(t, 0x0, flash_size);
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DEBUG("\nSAM4L: RAM = 0x%x (%dK), FLASH = 0x%x (%dK)\n",
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ram_size, ram_size / 1024, flash_size, flash_size / 1024);
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(unsigned int) ram_size, (unsigned int) (ram_size / 1024),
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(unsigned int) flash_size, (unsigned int)(flash_size / 1024));
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target_mem_write32(t, SMAP_CR, 0x1); /* enable SMAP */
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DEBUG("\nSAM4L: SMAP Enabled\n");
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DEBUG("\nSAM4L: Orig CHIPID = 0x%08lx\n", t->idcode);
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reg = target_mem_read32(t, SMAP_CHIPID);
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DEBUG("\nSAM4L: SMAP CHIPID = 0x%08lx\n", reg);
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reg = target_mem_read32(t, SMAP_SR);
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DEBUG("\nSAM4L: SMAP is %s\n", (reg & SMAP_SR_EN) ? "Enabled" : "Disabled");
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DEBUG("\nSAM4L: Debugger is %s\n", (reg & SMAP_SR_DBGP) ? "Present" : "Not Present");
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DEBUG("\nSAM4L: Core is %s\n", (reg & SMAP_SR_HCR) ? "In Reset" : "Running");
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sam4l_reset(t);
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reg = target_mem_read32(t, SMAP_SR);
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DEBUG("\nSAM4L: Core is %s\n", (reg & SMAP_SR_HCR) ? "In Reset" : "Running");
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/* enable SMAP if not, check for HCR and reset if set */
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sam4l_extended_reset(t);
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DEBUG("\nSAM4L: SAM4L Selected.\n");
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if (target_check_error(t)) {
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DEBUG("SAM4L: target_check_error returned true\n");
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@ -274,30 +265,34 @@ bool sam4l_probe(target *t)
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* We've been reset, make sure we take the core out of reset
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*/
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void
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sam4l_reset(target *t)
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sam4l_extended_reset(target *t)
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{
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uint32_t reg;
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int i;
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DEBUG("SAM4L: Extended Reset\n");
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/* enable SMAP in case we're dealing with a non-TCK SRST */
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target_mem_write32(t, SMAP_CR, 0x1); /* enable SMAP */
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reg = target_mem_read32(t, SMAP_SR);
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DEBUG("\nSAM4L: SMAP_SR has 0x%08lx\n", reg);
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DEBUG("\nSAM4L: SMAP_SR has 0x%08lx\n", (long unsigned int) reg);
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if ((reg & SMAP_SR_HCR) != 0) {
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/* write '1' bit to the status clear register */
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target_mem_write32(t, SMAP_SCR, SMAP_SR_HCR);
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i = 0;
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do {
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/* waiting 250 loops for it to reset is arbitrary, it should happen right away */
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for (i = 0; i < 250; i++) {
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reg = target_mem_read32(t, SMAP_SR);
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i++;
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} while (((reg & SMAP_SR_HCR) != 0) && (i < 100));
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if (i == 100) {
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DEBUG("\nSAM4L: Reset failed. SMAP_SR has 0x%08lx\n", reg);
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}
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/* not sure what to do if we can't reset that bit */
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if (i > 249) {
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DEBUG("\nSAM4L: Reset failed. SMAP_SR has 0x%08lx\n", (long unsigned int) reg);
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}
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}
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/* reset bus error if for some reason SMAP was disabled */
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target_check_error(t);
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}
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/*
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* sam4_flash_command
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* sam4l_flash_command
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*
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* Helper function, wait for the flash controller to be ready to receive a
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* command. Then send it the command, page number, and the authorization
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@ -307,13 +302,14 @@ sam4l_reset(target *t)
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* pointers.
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*/
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static int
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sam4_flash_command(target *t, uint32_t page, uint32_t cmd)
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sam4l_flash_command(target *t, uint32_t page, uint32_t cmd)
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{
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uint32_t cmd_reg;
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uint32_t status;
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int timeout;
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DEBUG("\nSAM4L: sam4_flash_command: FSR: 0x%08x, page = %d, command = %d\n",
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DEBUG("\nSAM4L: sam4l_flash_command: FSR: 0x%08x, page = %d, command = %d\n",
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(unsigned int)(FLASHCALW_FSR), (int) page, (int) cmd);
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/* wait for Flash controller ready */
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for (timeout = 0; timeout < FLASH_TIMEOUT; timeout++) {
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status = target_mem_read32(t, FLASHCALW_FSR);
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if (status & FLASHCALW_FSR_FRDY) {
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@ -321,14 +317,17 @@ sam4_flash_command(target *t, uint32_t page, uint32_t cmd)
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}
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}
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if (timeout == FLASH_TIMEOUT) {
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DEBUG("\nSAM4L: sam4_flash_command: Not ready! Status = 0x%08x\n", (unsigned int) status);
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DEBUG("\nSAM4L: sam4l_flash_command: Not ready! Status = 0x%08x\n", (unsigned int) status);
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return -1; /* Failed */
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}
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/* load up the new command */
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cmd_reg = (cmd & FLASHCALW_FCMD_CMD_MASK) |
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((page & FLASHCALW_FCMD_PAGEN_MASK) << FLASHCALW_FCMD_PAGEN_SHIFT) |
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(0xA5 << FLASHCALW_FCMD_KEY_SHIFT);
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DEBUG("\nSAM4L: sam4_flash_command: Wrting command word 0x%08x\n", (unsigned int) cmd_reg);
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DEBUG("\nSAM4L: sam4l_flash_command: Wrting command word 0x%08x\n", (unsigned int) cmd_reg);
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/* and kick it off */
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target_mem_write32(t, FLASHCALW_FCMD, cmd_reg);
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/* don't actually wait for it to finish, the next command will stall if it is not done */
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return 0;
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}
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@ -336,30 +335,31 @@ sam4_flash_command(target *t, uint32_t page, uint32_t cmd)
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* Write data from 'src' into flash using the algorithim provided by
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* Atmel in their data sheet.
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*/
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int
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sam4_flash_write(struct target_flash *f, target_addr addr, const void *src, size_t len)
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static int
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sam4l_flash_write_buf(struct target_flash *f, target_addr addr, const void *src, size_t len)
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{
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target *t = f->t;
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uint32_t *src_data = (uint32_t *)src;
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uint32_t ndx;
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uint16_t page;
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DEBUG("\nSAM4L: sam4_flash_write: addr = 0x%08lx, len %d\n", addr, len);
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/* This will fail with unaligned writes */
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DEBUG("\nSAM4L: sam4l_flash_write_buf: addr = 0x%08lx, len %d\n", (long unsigned int) addr, (int) len);
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/* This will fail with unaligned writes, the write_buf version */
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while (len) {
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page = addr / SAM4L_PAGE_SIZE;
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/* clear the page buffer */
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if (sam4_flash_command(t, 0, FLASH_CMD_CPB)) {
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if (sam4l_flash_command(t, 0, FLASH_CMD_CPB)) {
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return -1;
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}
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/* Fill it with data to write */
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target_mem_write(t, addr, src_data, SAM4L_PAGE_SIZE);
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#if 0
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/* Now fill page buffer with our 512 bytes of data */
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/* I did try to use target_mem_write however that resulted in the
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* last 64 bits (8 bytes) to be incorrect on even pages (0, 2, 4, ...)
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* since it works this way I've not investigated further.
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*/
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for (ndx = 0; ndx < SAM4L_PAGE_SIZE; ndx += 4) {
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/*
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target_mem_write32(t, addr, *src_data);
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addr += 4;
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*/
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/*
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* the page buffer overlaps flash, its only 512 bytes long
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* and no matter where you write it from it goes to the page
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@ -370,11 +370,11 @@ sam4_flash_write(struct target_flash *f, target_addr addr, const void *src, size
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target_mem_write32(t, addr+ndx, *src_data);
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src_data++;
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}
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#endif
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/* write the page */
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if (sam4_flash_command(t, page, FLASH_CMD_WP)) {
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if (sam4l_flash_command(t, page, FLASH_CMD_WP)) {
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return -1;
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}
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/* it should be done after one page, but in case it isn't */
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len -= SAM4L_PAGE_SIZE;
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addr += SAM4L_PAGE_SIZE;
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}
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@ -385,19 +385,22 @@ sam4_flash_write(struct target_flash *f, target_addr addr, const void *src, size
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* Erase flash across the addresses specified by addr and len
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*/
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static int
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sam4_flash_erase(struct target_flash *f, target_addr addr, size_t len)
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sam4l_flash_erase(struct target_flash *f, target_addr addr, size_t len)
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{
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target *t = f->t;
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uint16_t page;
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DEBUG("SAM4L: flash erase address 0x%08x for %d bytes\n",
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(unsigned int) addr, (unsigned int) len);
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/* force len to be an integral number of pages */
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/* len = (len + (SAM4_PAGE_SIZE - 1)) & ~SAM4_PAGE_SIZE; */
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/*
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* NB: if addr isn't aligned to a page boundary, or length
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* is not an even multiple of page sizes, we may end up
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* erasing data we didn't intend to.
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*/
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while (len) {
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page = addr / SAM4_PAGE_SIZE;
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if (sam4_flash_command(t, page, FLASH_CMD_EP)) {
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if (sam4l_flash_command(t, page, FLASH_CMD_EP)) {
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return -1;
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}
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len -= SAM4_PAGE_SIZE;
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