Started halt/resume for ARM7TDMI.
This commit is contained in:
Gareth McMullin
parent
fcdbf8efc8
commit
4c75ac524b
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@ -7,7 +7,7 @@ VPATH += $(HOST)
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BUILDDATE := `date +"%Y%m%d"`
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CFLAGS += -Wall -Wextra -Wno-pointer-sign -Wno-char-subscripts\
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-Os -std=gnu99 -g3 -DBUILDDATE=\"$(BUILDDATE)\"\
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-O0 -std=gnu99 -g3 -DBUILDDATE=\"$(BUILDDATE)\"\
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-I. -Iinclude -I$(HOST) \
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-DVERSION_SUFFIX=\"`../scripts/setlocalversion`\"
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@ -63,8 +63,8 @@ static const char arm7_driver_str[] = "ARM7TDMI";
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#define ARM7_SCANN_EICE 2
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/* EmbeddedICE-RT Register addresses */
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#define ARM7_EICE_DEBUG_STAT 0x00
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#define ARM7_EICE_DEBUG_CTRL 0x01
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#define ARM7_EICE_DEBUG_CTRL 0x00
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#define ARM7_EICE_DEBUG_STAT 0x01
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#define ARM7_EICE_ABORT_STAT 0x02
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#define ARM7_EICE_COMMS_CTRL 0x04
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#define ARM7_EICE_COMMS_DATA 0x05
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@ -75,6 +75,25 @@ static const char arm7_driver_str[] = "ARM7TDMI";
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#define ARM7_EICE_WATCH_CTRL(x) (0x0C + (8 * (x))
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#define ARM7_EICE_WATCH_CTRL_MASK(x) (0x0D + (8 * (x))
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/* Read/write bit in EmbeddedICE-RT scan chain */
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#define ARM7_EICE_READ (0uLL << 37)
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#define ARM7_EICE_WRITE (1uLL << 37)
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/* Debug Control Register bits */
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#define ARM7_EICE_DEBUG_CTRL_EICE_DISABLE (1 << 5)
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#define ARM7_EICE_DEBUG_CTRL_MONITOR (1 << 4)
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/* Bit 3 - Reserved */
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#define ARM7_EICE_DEBUG_CTRL_INTDIS (1 << 2)
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#define ARM7_EICE_DEBUG_CTRL_DBGRQ (1 << 1)
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#define ARM7_EICE_DEBUG_CTRL_DBGACK (1 << 0)
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/* Debug Status Register bits */
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#define ARM7_EICE_DEBUG_STAT_TBIT (1 << 4)
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#define ARM7_EICE_DEBUG_STAT_NMREQ (1 << 3)
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#define ARM7_EICE_DEBUG_STAT_INTDIS (1 << 2)
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#define ARM7_EICE_DEBUG_STAT_DBGRQ (1 << 1)
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#define ARM7_EICE_DEBUG_STAT_DBGACK (1 << 0)
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struct target_arm7_s {
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target t;
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jtag_dev_t *jtag;
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@ -123,20 +142,87 @@ void arm7tdmi_jtag_handler(jtag_dev_t *dev)
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target_list = t;
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}
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static void arm7_select_scanchain(struct target_arm7_s *target, uint8_t chain)
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{
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jtag_dev_write_ir(target->jtag, ARM7_IR_SCAN_N);
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jtag_dev_shift_dr(target->jtag, NULL, &chain, 4);
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jtag_dev_write_ir(target->jtag, ARM7_IR_INTEST);
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}
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static void arm7_eice_write(struct target_arm7_s *target,
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uint8_t addr, uint32_t value)
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{
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uint64_t val = ((uint64_t)addr << 32) | value | ARM7_EICE_WRITE;
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arm7_select_scanchain(target, ARM7_SCANN_EICE);
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jtag_dev_shift_dr(target->jtag, NULL, (uint8_t *)&val, 38);
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}
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static uint32_t arm7_eice_read(struct target_arm7_s *target, uint8_t addr)
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{
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uint64_t val = ((uint64_t)addr << 32) | ARM7_EICE_READ;
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arm7_select_scanchain(target, ARM7_SCANN_EICE);
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jtag_dev_shift_dr(target->jtag, NULL, (uint8_t *)&val, 38);
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jtag_dev_shift_dr(target->jtag, (uint8_t *)&val, (uint8_t *)&val, 38);
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return (uint32_t)val;
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}
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static void arm7_halt_request(struct target_s *target)
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{
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(void)target;
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struct target_arm7_s *t = (struct target_arm7_s *)target;
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arm7_eice_write(t, ARM7_EICE_DEBUG_CTRL, ARM7_EICE_DEBUG_CTRL_DBGRQ);
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}
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static int arm7_halt_wait(struct target_s *target)
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{
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(void)target;
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struct target_arm7_s *t = (struct target_arm7_s *)target;
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int stat = arm7_eice_read(t, ARM7_EICE_DEBUG_STAT);
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if(!(stat & ARM7_EICE_DEBUG_STAT_DBGACK))
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return 0;
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/* We are halted, so switch to ARM mode if needed. */
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if(stat & ARM7_EICE_DEBUG_STAT_TBIT) {
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/* This sequence switches to ARM mode:
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* STR R0, [R0] ; Save R0 before use
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* MOV R0, PC ; Copy PC into R0
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* STR R0, [R0] ; Now save the PC in R0
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* BX PC ; Jump into ARM state
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* MOV R8, R8 ; NOP
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* MOV R8, R8 ; NOP
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*/
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/* FIXME: Switch to ARM mode. */
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}
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/* FIXME: Get core register cache. */
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/* STM R0, {R0-R15} */
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return 1;
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}
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static void arm7_halt_resume(struct target_s *target, uint8_t step)
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{
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(void)target;
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(void)step;
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struct target_arm7_s *t = (struct target_arm7_s *)target;
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if(step) {
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/* FIXME: Set breakpoint on any instruction to single step. */
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}
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/* FIXME: Restore core registers. */
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/* LDM R0, {R0-R15} */
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/* Release DBGRQ */
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arm7_eice_write(t, ARM7_EICE_DEBUG_CTRL, 0);
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/* This sequence restores PC if no other instructions issued in
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* debug mode...
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* 0 E1A00000; MOV R0, R0
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* 1 E1A00000; MOV R0, R0
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* 0 EAFFFFFA; B -6
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* FIXME: Add this sequence and adjustment for other opcodes.
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*/
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jtag_dev_write_ir(t->jtag, ARM7_IR_RESTART);
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}
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