swdptap: Refactored swdptap_seq_out_parity and cleaned up
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@ -155,39 +155,17 @@ static void swdptap_seq_out(const uint32_t tms_states, const size_t clock_cycles
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swdptap_seq_out_no_delay(tms_states, clock_cycles);
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swdptap_seq_out_no_delay(tms_states, clock_cycles);
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}
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}
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static void swdptap_seq_out_parity(uint32_t tms_states, size_t ticks)
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static void swdptap_seq_out_parity(const uint32_t tms_states, const size_t clock_cycles)
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{
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{
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int parity = __builtin_popcount(tms_states);
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int parity = __builtin_popcount(tms_states);
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#ifdef DEBUG_SWD_BITS
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swdptap_seq_out(tms_states, clock_cycles);
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for (int i = 0; i < ticks; i++)
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gpio_set_val(SWDIO_PORT, SWDIO_PIN, parity & 1U);
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DEBUG("%d", (tms_states & (1 << i)) ? 1 : 0);
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#endif
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register volatile int32_t cnt;
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swdptap_turnaround(SWDIO_STATUS_DRIVE);
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gpio_set_val(SWDIO_PORT, SWDIO_PIN, tms_states & 1);
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tms_states >>= 1;
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if (swd_delay_cnt) {
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while (ticks--) {
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gpio_set(SWCLK_PORT, SWCLK_PIN);
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for(cnt = swd_delay_cnt; --cnt > 0;);
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gpio_set_val(SWDIO_PORT, SWDIO_PIN, tms_states & 1);
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tms_states >>= 1;
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gpio_clear(SWCLK_PORT, SWCLK_PIN);
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for(cnt = swd_delay_cnt; --cnt > 0;);
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}
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} else {
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while (ticks--) {
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gpio_set(SWCLK_PORT, SWCLK_PIN);
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gpio_set_val(SWDIO_PORT, SWDIO_PIN, tms_states & 1);
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tms_states >>= 1;
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gpio_clear(SWCLK_PORT, SWCLK_PIN);
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}
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}
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gpio_set_val(SWDIO_PORT, SWDIO_PIN, parity & 1);
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gpio_set(SWCLK_PORT, SWCLK_PIN);
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gpio_set(SWCLK_PORT, SWCLK_PIN);
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for(cnt = swd_delay_cnt; --cnt > 0;);
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for (volatile int32_t cnt = swd_delay_cnt - 2; cnt > 0; cnt--)
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continue;
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gpio_clear(SWCLK_PORT, SWCLK_PIN);
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gpio_clear(SWCLK_PORT, SWCLK_PIN);
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for(cnt = swd_delay_cnt; --cnt > 0;);
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for (volatile int32_t cnt = swd_delay_cnt - 2; cnt > 0; cnt--)
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continue;
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}
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}
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int swdptap_init(ADIv5_DP_t *dp)
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int swdptap_init(ADIv5_DP_t *dp)
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