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Added support for SAMD10/11/21, and list of tested SAM D devices 

This allows blackmagic to be used with the new Arduino Zero board via
the unpopulated SWD header on the east end of the board.
This commit is contained in:
Richard Meadows 2015-01-18 22:35:59 +00:00
parent 3726061773
commit 565795e168
3 changed files with 256 additions and 204 deletions
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2
src/cortexm.c
View File

@ -259,7 +259,7 @@ cortexm_probe(struct target_s *target)
PROBE(lpc43xx_probe); PROBE(lpc43xx_probe);
PROBE(sam3x_probe); PROBE(sam3x_probe);
PROBE(nrf51_probe); PROBE(nrf51_probe);
PROBE(samd20_probe); PROBE(samd_probe);
PROBE(lmi_probe); PROBE(lmi_probe);
PROBE(kinetis_probe); PROBE(kinetis_probe);
#undef PROBE #undef PROBE

2
src/include/target.h
View File

@ -224,7 +224,7 @@ bool lpc11xx_probe(struct target_s *target);
bool lpc43xx_probe(struct target_s *target); bool lpc43xx_probe(struct target_s *target);
bool sam3x_probe(struct target_s *target); bool sam3x_probe(struct target_s *target);
bool nrf51_probe(struct target_s *target); bool nrf51_probe(struct target_s *target);
bool samd20_probe(struct target_s *target); bool samd_probe(struct target_s *target);
bool kinetis_probe(struct target_s *target); bool kinetis_probe(struct target_s *target);
#endif #endif

462
src/samd20.c
View File

@ -17,9 +17,15 @@
* along with this program. If not, see <http://www.gnu.org/licenses/>. * along with this program. If not, see <http://www.gnu.org/licenses/>.
*/ */
/* This file implements Atmel SAM D20 target specific functions for /* This file implements Atmel SAM D target specific functions for
* detecting the device, providing the XML memory map and Flash memory * detecting the device, providing the XML memory map and Flash memory
* programming. * programming.
*
* Tested with
* * SAMD20E17A (rev C)
* * SAMD20J18A (rev B)
* * SAMD21J18A (rev B)
* *
*/ */
/* Refer to the SAM D20 Datasheet: /* Refer to the SAM D20 Datasheet:
* http://www.atmel.com/Images/Atmel-42129-SAM-D20_Datasheet.pdf * http://www.atmel.com/Images/Atmel-42129-SAM-D20_Datasheet.pdf
@ -38,26 +44,26 @@
#include "gdb_packet.h" #include "gdb_packet.h"
#include "cortexm.h" #include "cortexm.h"
static int samd20_flash_erase(struct target_s *target, uint32_t addr, int len); static int samd_flash_erase(struct target_s *target, uint32_t addr, int len);
static int samd20_flash_write(struct target_s *target, uint32_t dest, static int samd_flash_write(struct target_s *target, uint32_t dest,
const uint8_t *src, int len); const uint8_t *src, int len);
static bool samd20_cmd_erase_all(target *t); static bool samd_cmd_erase_all(target *t);
static bool samd20_cmd_lock_flash(target *t); static bool samd_cmd_lock_flash(target *t);
static bool samd20_cmd_unlock_flash(target *t); static bool samd_cmd_unlock_flash(target *t);
static bool samd20_cmd_read_userrow(target *t); static bool samd_cmd_read_userrow(target *t);
static bool samd20_cmd_serial(target *t); static bool samd_cmd_serial(target *t);
static bool samd20_cmd_mbist(target *t); static bool samd_cmd_mbist(target *t);
static bool samd20_cmd_ssb(target *t); static bool samd_cmd_ssb(target *t);
const struct command_s samd20_cmd_list[] = { const struct command_s samd_cmd_list[] = {
{"erase_mass", (cmd_handler)samd20_cmd_erase_all, "Erase entire flash memory"}, {"erase_mass", (cmd_handler)samd_cmd_erase_all, "Erase entire flash memory"},
{"lock_flash", (cmd_handler)samd20_cmd_lock_flash, "Locks flash against spurious commands"}, {"lock_flash", (cmd_handler)samd_cmd_lock_flash, "Locks flash against spurious commands"},
{"unlock_flash", (cmd_handler)samd20_cmd_unlock_flash, "Unlocks flash"}, {"unlock_flash", (cmd_handler)samd_cmd_unlock_flash, "Unlocks flash"},
{"user_row", (cmd_handler)samd20_cmd_read_userrow, "Prints user row from flash"}, {"user_row", (cmd_handler)samd_cmd_read_userrow, "Prints user row from flash"},
{"serial", (cmd_handler)samd20_cmd_serial, "Prints serial number"}, {"serial", (cmd_handler)samd_cmd_serial, "Prints serial number"},
{"mbist", (cmd_handler)samd20_cmd_mbist, "Runs the built-in memory test"}, {"mbist", (cmd_handler)samd_cmd_mbist, "Runs the built-in memory test"},
{"set_security_bit", (cmd_handler)samd20_cmd_ssb, "Sets the Security Bit"}, {"set_security_bit", (cmd_handler)samd_cmd_ssb, "Sets the Security Bit"},
{NULL, NULL, NULL} {NULL, NULL, NULL}
}; };
@ -65,7 +71,7 @@ const struct command_s samd20_cmd_list[] = {
* 256KB Flash Max., 32KB RAM Max. The smallest unit of erase is the * 256KB Flash Max., 32KB RAM Max. The smallest unit of erase is the
* one row = 256 bytes. * one row = 256 bytes.
*/ */
static const char samd20_xml_memory_map[] = "<?xml version=\"1.0\"?>" static const char samd_xml_memory_map[] = "<?xml version=\"1.0\"?>"
/* "<!DOCTYPE memory-map " /* "<!DOCTYPE memory-map "
" PUBLIC \"+//IDN gnu.org//DTD GDB Memory Map V1.0//EN\"" " PUBLIC \"+//IDN gnu.org//DTD GDB Memory Map V1.0//EN\""
" \"http://sourceware.org/gdb/gdb-memory-map.dtd\">"*/ " \"http://sourceware.org/gdb/gdb-memory-map.dtd\">"*/
@ -77,83 +83,85 @@ static const char samd20_xml_memory_map[] = "<?xml version=\"1.0\"?>"
"</memory-map>"; "</memory-map>";
/* Non-Volatile Memory Controller (NVMC) Parameters */ /* Non-Volatile Memory Controller (NVMC) Parameters */
#define SAMD20_ROW_SIZE 256 #define SAMD_ROW_SIZE 256
#define SAMD20_PAGE_SIZE 64 #define SAMD_PAGE_SIZE 64
/* -------------------------------------------------------------------------- */ /* -------------------------------------------------------------------------- */
/* Non-Volatile Memory Controller (NVMC) Registers */ /* Non-Volatile Memory Controller (NVMC) Registers */
/* -------------------------------------------------------------------------- */ /* -------------------------------------------------------------------------- */
#define SAMD20_NVMC 0x41004000 #define SAMD_NVMC 0x41004000
#define SAMD20_NVMC_CTRLA (SAMD20_NVMC + 0x0) #define SAMD_NVMC_CTRLA (SAMD_NVMC + 0x0)
#define SAMD20_NVMC_CTRLB (SAMD20_NVMC + 0x04) #define SAMD_NVMC_CTRLB (SAMD_NVMC + 0x04)
#define SAMD20_NVMC_PARAM (SAMD20_NVMC + 0x08) #define SAMD_NVMC_PARAM (SAMD_NVMC + 0x08)
#define SAMD20_NVMC_INTFLAG (SAMD20_NVMC + 0x14) #define SAMD_NVMC_INTFLAG (SAMD_NVMC + 0x14)
#define SAMD20_NVMC_STATUS (SAMD20_NVMC + 0x18) #define SAMD_NVMC_STATUS (SAMD_NVMC + 0x18)
#define SAMD20_NVMC_ADDRESS (SAMD20_NVMC + 0x1C) #define SAMD_NVMC_ADDRESS (SAMD_NVMC + 0x1C)
/* Control A Register (CTRLA) */ /* Control A Register (CTRLA) */
#define SAMD20_CTRLA_CMD_KEY 0xA500 #define SAMD_CTRLA_CMD_KEY 0xA500
#define SAMD20_CTRLA_CMD_ERASEROW 0x0002 #define SAMD_CTRLA_CMD_ERASEROW 0x0002
#define SAMD20_CTRLA_CMD_WRITEPAGE 0x0004 #define SAMD_CTRLA_CMD_WRITEPAGE 0x0004
#define SAMD20_CTRLA_CMD_ERASEAUXROW 0x0005 #define SAMD_CTRLA_CMD_ERASEAUXROW 0x0005
#define SAMD20_CTRLA_CMD_WRITEAUXPAGE 0x0006 #define SAMD_CTRLA_CMD_WRITEAUXPAGE 0x0006
#define SAMD20_CTRLA_CMD_LOCK 0x0040 #define SAMD_CTRLA_CMD_LOCK 0x0040
#define SAMD20_CTRLA_CMD_UNLOCK 0x0041 #define SAMD_CTRLA_CMD_UNLOCK 0x0041
#define SAMD20_CTRLA_CMD_PAGEBUFFERCLEAR 0x0044 #define SAMD_CTRLA_CMD_PAGEBUFFERCLEAR 0x0044
#define SAMD20_CTRLA_CMD_SSB 0x0045 #define SAMD_CTRLA_CMD_SSB 0x0045
#define SAMD20_CTRLA_CMD_INVALL 0x0046 #define SAMD_CTRLA_CMD_INVALL 0x0046
/* Interrupt Flag Register (INTFLAG) */ /* Interrupt Flag Register (INTFLAG) */
#define SAMD20_NVMC_READY (1 << 0) #define SAMD_NVMC_READY (1 << 0)
/* Non-Volatile Memory Calibration and Auxiliary Registers */ /* Non-Volatile Memory Calibration and Auxiliary Registers */
#define SAMD20_NVM_USER_ROW_LOW 0x00804000 #define SAMD_NVM_USER_ROW_LOW 0x00804000
#define SAMD20_NVM_USER_ROW_HIGH 0x00804004 #define SAMD_NVM_USER_ROW_HIGH 0x00804004
#define SAMD20_NVM_CALIBRATION 0x00806020 #define SAMD_NVM_CALIBRATION 0x00806020
#define SAMD20_NVM_SERIAL(n) (0x0080A00C + (0x30 * ((n + 3) / 4)) + \ #define SAMD_NVM_SERIAL(n) (0x0080A00C + (0x30 * ((n + 3) / 4)) + \
(0x4 * n)) (0x4 * n))
/* -------------------------------------------------------------------------- */ /* -------------------------------------------------------------------------- */
/* Device Service Unit (DSU) Registers */ /* Device Service Unit (DSU) Registers */
/* -------------------------------------------------------------------------- */ /* -------------------------------------------------------------------------- */
#define SAMD20_DSU 0x41002000 #define SAMD_DSU 0x41002000
#define SAMD20_DSU_EXT_ACCESS (SAMD20_DSU + 0x100) #define SAMD_DSU_EXT_ACCESS (SAMD_DSU + 0x100)
#define SAMD20_DSU_CTRLSTAT (SAMD20_DSU_EXT_ACCESS + 0x0) #define SAMD_DSU_CTRLSTAT (SAMD_DSU_EXT_ACCESS + 0x0)
#define SAMD20_DSU_ADDRESS (SAMD20_DSU_EXT_ACCESS + 0x4) #define SAMD_DSU_ADDRESS (SAMD_DSU_EXT_ACCESS + 0x4)
#define SAMD20_DSU_LENGTH (SAMD20_DSU_EXT_ACCESS + 0x8) #define SAMD_DSU_LENGTH (SAMD_DSU_EXT_ACCESS + 0x8)
#define SAMD20_DSU_DID (SAMD20_DSU_EXT_ACCESS + 0x018) #define SAMD_DSU_DID (SAMD_DSU_EXT_ACCESS + 0x018)
#define SAMD20_DSU_PID(n) (SAMD20_DSU + 0x1FE0 + \ #define SAMD_DSU_PID(n) (SAMD_DSU + 0x1FE0 + \
(0x4 * (n % 4)) - (0x10 * (n / 4))) (0x4 * (n % 4)) - (0x10 * (n / 4)))
#define SAMD20_DSU_CID(n) (SAMD20_DSU + 0x1FF0 + \ #define SAMD_DSU_CID(n) (SAMD_DSU + 0x1FF0 + \
(0x4 * (n % 4))) (0x4 * (n % 4)))
/* Control and Status Register (CTRLSTAT) */ /* Control and Status Register (CTRLSTAT) */
#define SAMD20_CTRL_CHIP_ERASE (1 << 4) #define SAMD_CTRL_CHIP_ERASE (1 << 4)
#define SAMD20_CTRL_MBIST (1 << 3) #define SAMD_CTRL_MBIST (1 << 3)
#define SAMD20_CTRL_CRC (1 << 2) #define SAMD_CTRL_CRC (1 << 2)
#define SAMD20_STATUSA_PERR (1 << 12) #define SAMD_STATUSA_PERR (1 << 12)
#define SAMD20_STATUSA_FAIL (1 << 11) #define SAMD_STATUSA_FAIL (1 << 11)
#define SAMD20_STATUSA_BERR (1 << 10) #define SAMD_STATUSA_BERR (1 << 10)
#define SAMD20_STATUSA_CRSTEXT (1 << 9) #define SAMD_STATUSA_CRSTEXT (1 << 9)
#define SAMD20_STATUSA_DONE (1 << 8) #define SAMD_STATUSA_DONE (1 << 8)
#define SAMD20_STATUSB_PROT (1 << 16) #define SAMD_STATUSB_PROT (1 << 16)
/* Device Identification Register (DID) */ /* Device Identification Register (DID) */
#define SAMD20_DID_MASK 0xFFBF0000 #define SAMD_DID_MASK 0xFFBC0000
#define SAMD20_DID_CONST_VALUE 0x10000000 #define SAMD_DID_CONST_VALUE 0x10000000
#define SAMD20_DID_DEVSEL_MASK 0x0F #define SAMD_DID_DEVSEL_MASK 0x0F
#define SAMD20_DID_DEVSEL_POS 0 #define SAMD_DID_DEVSEL_POS 0
#define SAMD20_DID_REVISION_MASK 0x0F #define SAMD_DID_REVISION_MASK 0x0F
#define SAMD20_DID_REVISION_POS 8 #define SAMD_DID_REVISION_POS 8
#define SAMD_DID_SERIES_MASK 0x03
#define SAMD_DID_SERIES_POS 16
/* Peripheral ID */ /* Peripheral ID */
#define SAMD20_PID_MASK 0x00F7FFFF #define SAMD_PID_MASK 0x00F7FFFF
#define SAMD20_PID_CONST_VALUE 0x0001FCD0 #define SAMD_PID_CONST_VALUE 0x0001FCD0
/* Component ID */ /* Component ID */
#define SAMD20_CID_VALUE 0xB105100D #define SAMD_CID_VALUE 0xB105100D
/* Utility */ /* Utility */
#define MINIMUM(a,b) ((a < b) ? a : b) #define MINIMUM(a,b) ((a < b) ? a : b)
@ -161,7 +169,7 @@ static const char samd20_xml_memory_map[] = "<?xml version=\"1.0\"?>"
/** /**
* Reads the SAM D20 Peripheral ID * Reads the SAM D20 Peripheral ID
*/ */
uint64_t samd20_read_pid(struct target_s *target) uint64_t samd_read_pid(struct target_s *target)
{ {
ADIv5_AP_t *ap = adiv5_target_ap(target); ADIv5_AP_t *ap = adiv5_target_ap(target);
uint64_t pid = 0; uint64_t pid = 0;
@ -169,14 +177,14 @@ uint64_t samd20_read_pid(struct target_s *target)
/* Five PID registers to read LSB first */ /* Five PID registers to read LSB first */
for (i = 0, j = 0; i < 5; i++, j += 8) for (i = 0, j = 0; i < 5; i++, j += 8)
pid |= (adiv5_ap_mem_read(ap, SAMD20_DSU_PID(i)) & 0xFF) << j; pid |= (adiv5_ap_mem_read(ap, SAMD_DSU_PID(i)) & 0xFF) << j;
return pid; return pid;
} }
/** /**
* Reads the SAM D20 Component ID * Reads the SAM D20 Component ID
*/ */
uint32_t samd20_read_cid(struct target_s *target) uint32_t samd_read_cid(struct target_s *target)
{ {
ADIv5_AP_t *ap = adiv5_target_ap(target); ADIv5_AP_t *ap = adiv5_target_ap(target);
uint64_t cid = 0; uint64_t cid = 0;
@ -184,7 +192,7 @@ uint32_t samd20_read_cid(struct target_s *target)
/* Four CID registers to read LSB first */ /* Four CID registers to read LSB first */
for (i = 0, j = 0; i < 4; i++, j += 8) for (i = 0, j = 0; i < 4; i++, j += 8)
cid |= (adiv5_ap_mem_read(ap, SAMD20_DSU_CID(i)) & 0xFF) << j; cid |= (adiv5_ap_mem_read(ap, SAMD_DSU_CID(i)) & 0xFF) << j;
return cid; return cid;
} }
@ -194,7 +202,7 @@ uint32_t samd20_read_cid(struct target_s *target)
* removes the target from extended reset where required. * removes the target from extended reset where required.
*/ */
static void static void
samd20_reset(struct target_s *target) samd_reset(struct target_s *target)
{ {
ADIv5_AP_t *ap = adiv5_target_ap(target); ADIv5_AP_t *ap = adiv5_target_ap(target);
@ -225,11 +233,11 @@ samd20_reset(struct target_s *target)
CORTEXM_AIRCR_VECTKEY | CORTEXM_AIRCR_SYSRESETREQ); CORTEXM_AIRCR_VECTKEY | CORTEXM_AIRCR_SYSRESETREQ);
/* Exit extended reset */ /* Exit extended reset */
if (adiv5_ap_mem_read(ap, SAMD20_DSU_CTRLSTAT) & if (adiv5_ap_mem_read(ap, SAMD_DSU_CTRLSTAT) &
SAMD20_STATUSA_CRSTEXT) { SAMD_STATUSA_CRSTEXT) {
/* Write bit to clear from extended reset */ /* Write bit to clear from extended reset */
adiv5_ap_mem_write(ap, SAMD20_DSU_CTRLSTAT, adiv5_ap_mem_write(ap, SAMD_DSU_CTRLSTAT,
SAMD20_STATUSA_CRSTEXT); SAMD_STATUSA_CRSTEXT);
} }
/* Poll for release from reset */ /* Poll for release from reset */
@ -256,11 +264,11 @@ samd20_revB_detach(struct target_s *target)
/* ---- Additional ---- */ /* ---- Additional ---- */
/* Exit extended reset */ /* Exit extended reset */
if (adiv5_ap_mem_read(ap, SAMD20_DSU_CTRLSTAT) & if (adiv5_ap_mem_read(ap, SAMD_DSU_CTRLSTAT) &
SAMD20_STATUSA_CRSTEXT) { SAMD_STATUSA_CRSTEXT) {
/* Write bit to clear from extended reset */ /* Write bit to clear from extended reset */
adiv5_ap_mem_write(ap, SAMD20_DSU_CTRLSTAT, adiv5_ap_mem_write(ap, SAMD_DSU_CTRLSTAT,
SAMD20_STATUSA_CRSTEXT); SAMD_STATUSA_CRSTEXT);
} }
} }
@ -278,24 +286,24 @@ samd20_revB_halt_resume(struct target_s *target, bool step)
/* ---- Additional ---- */ /* ---- Additional ---- */
/* Exit extended reset */ /* Exit extended reset */
if (adiv5_ap_mem_read(ap, SAMD20_DSU_CTRLSTAT) & if (adiv5_ap_mem_read(ap, SAMD_DSU_CTRLSTAT) &
SAMD20_STATUSA_CRSTEXT) { SAMD_STATUSA_CRSTEXT) {
/* Write bit to clear from extended reset */ /* Write bit to clear from extended reset */
adiv5_ap_mem_write(ap, SAMD20_DSU_CTRLSTAT, adiv5_ap_mem_write(ap, SAMD_DSU_CTRLSTAT,
SAMD20_STATUSA_CRSTEXT); SAMD_STATUSA_CRSTEXT);
} }
} }
/** /**
* Overload the default cortexm attach for when the samd20 is protected. * Overload the default cortexm attach for when the samd is protected.
* *
* If the samd20 is protected then the default cortexm attach will * If the samd is protected then the default cortexm attach will
* fail as the S_HALT bit in the DHCSR will never go high. This * fail as the S_HALT bit in the DHCSR will never go high. This
* function allows users to attach on a temporary basis so they can * function allows users to attach on a temporary basis so they can
* rescue the device. * rescue the device.
*/ */
static bool static bool
samd20_protected_attach(struct target_s *target) samd_protected_attach(struct target_s *target)
{ {
/** /**
* TODO: Notify the user that we're not really attached and * TODO: Notify the user that we're not really attached and
@ -310,62 +318,106 @@ samd20_protected_attach(struct target_s *target)
return true; return true;
} }
/**
char variant_string[40]; * Use the DSU Device Indentification Register to populate a struct
bool samd20_probe(struct target_s *target) * describing the SAM D device.
*/
struct samd_descr {
uint8_t series;
char revision;
char pin;
uint8_t mem;
char package[3];
};
struct samd_descr samd_parse_device_id(uint32_t did)
{ {
ADIv5_AP_t *ap = adiv5_target_ap(target); struct samd_descr samd;
uint32_t cid = samd20_read_cid(target); memset(samd.package, 0, 3);
uint32_t pid = samd20_read_pid(target);
/* Check the ARM Coresight Component and Perhiperal IDs */ uint8_t series = (did >> SAMD_DID_SERIES_POS)
if (cid == SAMD20_CID_VALUE && & SAMD_DID_SERIES_MASK;
(pid & SAMD20_PID_MASK) == SAMD20_PID_CONST_VALUE) { uint8_t revision = (did >> SAMD_DID_REVISION_POS)
& SAMD_DID_REVISION_MASK;
uint8_t devsel = (did >> SAMD_DID_DEVSEL_POS)
& SAMD_DID_DEVSEL_MASK;
/* Read the Device ID */ /* Series */
uint32_t did = adiv5_ap_mem_read(ap, SAMD20_DSU_DID); switch (series) {
case 0: samd.series = 20; break;
case 1: samd.series = 21; break;
case 2: samd.series = 10; break;
case 3: samd.series = 11; break;
}
/* Revision */
samd.revision = 'A' + revision;
/* If the Device ID matches */ switch (samd.series) {
if ((did & SAMD20_DID_MASK) == SAMD20_DID_CONST_VALUE) { case 20: /* SAM D20 */
case 21: /* SAM D21 */
uint8_t devsel = (did >> SAMD20_DID_DEVSEL_POS)
& SAMD20_DID_DEVSEL_MASK;
uint8_t revision = (did >> SAMD20_DID_REVISION_POS)
& SAMD20_DID_REVISION_MASK;
uint32_t ctrlstat = adiv5_ap_mem_read(ap, SAMD20_DSU_CTRLSTAT);
/* Pin Variant */
char pin_variant;
switch (devsel / 5) { switch (devsel / 5) {
case 0: pin_variant = 'J'; break; case 0: samd.pin = 'J'; break;
case 1: pin_variant = 'G'; break; case 1: samd.pin = 'G'; break;
case 2: pin_variant = 'E'; break; case 2: samd.pin = 'E'; break;
default: pin_variant = 'u'; break; default: samd.pin = 'u'; break;
}
samd.mem = 18 - (devsel % 5);
break;
case 10: /* SAM D10 */
case 11: /* SAM D11 */
switch (devsel / 3) {
case 0: samd.package[0] = 'M'; break;
case 1: samd.package[0] = 'S'; samd.package[1] = 'S'; break;
}
samd.pin = 'D';
samd.mem = 14 - (devsel % 3);
break;
} }
/* Mem Variant */ return samd;
uint8_t mem_variant = 18 - (devsel % 5); }
/* Revision */
char revision_variant = 'A' + revision; char variant_string[40];
bool samd_probe(struct target_s *target)
{
ADIv5_AP_t *ap = adiv5_target_ap(target);
uint32_t cid = samd_read_cid(target);
uint32_t pid = samd_read_pid(target);
/* Check the ARM Coresight Component and Perhiperal IDs */
if (cid == SAMD_CID_VALUE &&
(pid & SAMD_PID_MASK) == SAMD_PID_CONST_VALUE) {
/* Read the Device ID */
uint32_t did = adiv5_ap_mem_read(ap, SAMD_DSU_DID);
/* If the Device ID matches */
if ((did & SAMD_DID_MASK) == SAMD_DID_CONST_VALUE) {
uint32_t ctrlstat = adiv5_ap_mem_read(ap, SAMD_DSU_CTRLSTAT);
struct samd_descr samd = samd_parse_device_id(did);
/* Protected? */ /* Protected? */
int protected = (ctrlstat & SAMD20_STATUSB_PROT); int protected = (ctrlstat & SAMD_STATUSB_PROT);
/* Part String */ /* Part String */
if (protected) { if (protected) {
sprintf(variant_string, "Atmel SAMD20%c%dA (rev %c) (PROT=1)", sprintf(variant_string,
pin_variant, mem_variant, revision_variant); "Atmel SAMD%d%c%dA%s (rev %c) (PROT=1)",
samd.series, samd.pin, samd.mem,
samd.package, samd.revision);
} else { } else {
sprintf(variant_string, "Atmel SAMD20%c%dA (rev %c)", sprintf(variant_string,
pin_variant, mem_variant, revision_variant); "Atmel SAMD%d%c%dA%s (rev %c)",
samd.series, samd.pin, samd.mem,
samd.package, samd.revision);
} }
/* Setup Target */ /* Setup Target */
target->driver = variant_string; target->driver = variant_string;
target->reset = samd20_reset; target->reset = samd_reset;
if (revision_variant == 'B') { if (samd.series == 20 && samd.revision == 'B') {
/** /**
* These functions check for and * These functions check for and
* extended reset. Appears to be * extended reset. Appears to be
@ -377,29 +429,29 @@ bool samd20_probe(struct target_s *target)
if (protected) { if (protected) {
/** /**
* Overload the default cortexm attach * Overload the default cortexm attach
* for when the samd20 is protected. * for when the samd is protected.
* This function allows users to * This function allows users to
* attach on a temporary basis so they * attach on a temporary basis so they
* can rescue the device. * can rescue the device.
*/ */
target->attach = samd20_protected_attach; target->attach = samd_protected_attach;
} }
target->xml_mem_map = samd20_xml_memory_map; target->xml_mem_map = samd_xml_memory_map;
target->flash_erase = samd20_flash_erase; target->flash_erase = samd_flash_erase;
target->flash_write = samd20_flash_write; target->flash_write = samd_flash_write;
target_add_commands(target, samd20_cmd_list, "SAMD20"); target_add_commands(target, samd_cmd_list, "SAMD");
/* If we're not in reset here */ /* If we're not in reset here */
if (!connect_assert_srst) { if (!connect_assert_srst) {
/* We'll have to release the target from /* We'll have to release the target from
* extended reset to make attach possible */ * extended reset to make attach possible */
if (adiv5_ap_mem_read(ap, SAMD20_DSU_CTRLSTAT) & if (adiv5_ap_mem_read(ap, SAMD_DSU_CTRLSTAT) &
SAMD20_STATUSA_CRSTEXT) { SAMD_STATUSA_CRSTEXT) {
/* Write bit to clear from extended reset */ /* Write bit to clear from extended reset */
adiv5_ap_mem_write(ap, SAMD20_DSU_CTRLSTAT, adiv5_ap_mem_write(ap, SAMD_DSU_CTRLSTAT,
SAMD20_STATUSA_CRSTEXT); SAMD_STATUSA_CRSTEXT);
} }
} }
@ -413,51 +465,51 @@ bool samd20_probe(struct target_s *target)
/** /**
* Temporary (until next reset) flash memory locking / unlocking * Temporary (until next reset) flash memory locking / unlocking
*/ */
static void samd20_lock_current_address(struct target_s *target) static void samd_lock_current_address(struct target_s *target)
{ {
ADIv5_AP_t *ap = adiv5_target_ap(target); ADIv5_AP_t *ap = adiv5_target_ap(target);
/* Issue the unlock command */ /* Issue the unlock command */
adiv5_ap_mem_write(ap, SAMD20_NVMC_CTRLA, SAMD20_CTRLA_CMD_KEY | SAMD20_CTRLA_CMD_LOCK); adiv5_ap_mem_write(ap, SAMD_NVMC_CTRLA, SAMD_CTRLA_CMD_KEY | SAMD_CTRLA_CMD_LOCK);
} }
static void samd20_unlock_current_address(struct target_s *target) static void samd_unlock_current_address(struct target_s *target)
{ {
ADIv5_AP_t *ap = adiv5_target_ap(target); ADIv5_AP_t *ap = adiv5_target_ap(target);
/* Issue the unlock command */ /* Issue the unlock command */
adiv5_ap_mem_write(ap, SAMD20_NVMC_CTRLA, SAMD20_CTRLA_CMD_KEY | SAMD20_CTRLA_CMD_UNLOCK); adiv5_ap_mem_write(ap, SAMD_NVMC_CTRLA, SAMD_CTRLA_CMD_KEY | SAMD_CTRLA_CMD_UNLOCK);
} }
/** /**
* Erase flash row by row * Erase flash row by row
*/ */
static int samd20_flash_erase(struct target_s *target, uint32_t addr, int len) static int samd_flash_erase(struct target_s *target, uint32_t addr, int len)
{ {
ADIv5_AP_t *ap = adiv5_target_ap(target); ADIv5_AP_t *ap = adiv5_target_ap(target);
addr &= ~(SAMD20_ROW_SIZE - 1); addr &= ~(SAMD_ROW_SIZE - 1);
len &= ~(SAMD20_ROW_SIZE - 1); len &= ~(SAMD_ROW_SIZE - 1);
while (len) { while (len) {
/* Write address of first word in row to erase it */ /* Write address of first word in row to erase it */
/* Must be shifted right for 16-bit address, see Datasheet §20.8.8 Address */ /* Must be shifted right for 16-bit address, see Datasheet §20.8.8 Address */
adiv5_ap_mem_write(ap, SAMD20_NVMC_ADDRESS, addr >> 1); adiv5_ap_mem_write(ap, SAMD_NVMC_ADDRESS, addr >> 1);
/* Unlock */ /* Unlock */
samd20_unlock_current_address(target); samd_unlock_current_address(target);
/* Issue the erase command */ /* Issue the erase command */
adiv5_ap_mem_write(ap, SAMD20_NVMC_CTRLA, SAMD20_CTRLA_CMD_KEY | SAMD20_CTRLA_CMD_ERASEROW); adiv5_ap_mem_write(ap, SAMD_NVMC_CTRLA, SAMD_CTRLA_CMD_KEY | SAMD_CTRLA_CMD_ERASEROW);
/* Poll for NVM Ready */ /* Poll for NVM Ready */
while ((adiv5_ap_mem_read(ap, SAMD20_NVMC_INTFLAG) & SAMD20_NVMC_READY) == 0) while ((adiv5_ap_mem_read(ap, SAMD_NVMC_INTFLAG) & SAMD_NVMC_READY) == 0)
if(target_check_error(target)) if(target_check_error(target))
return -1; return -1;
/* Lock */ /* Lock */
samd20_lock_current_address(target); samd_lock_current_address(target);
addr += SAMD20_ROW_SIZE; addr += SAMD_ROW_SIZE;
len -= SAMD20_ROW_SIZE; len -= SAMD_ROW_SIZE;
} }
return 0; return 0;
@ -466,7 +518,7 @@ static int samd20_flash_erase(struct target_s *target, uint32_t addr, int len)
/** /**
* Write flash page by page * Write flash page by page
*/ */
static int samd20_flash_write(struct target_s *target, uint32_t dest, static int samd_flash_write(struct target_s *target, uint32_t dest,
const uint8_t *src, int len) const uint8_t *src, int len)
{ {
ADIv5_AP_t *ap = adiv5_target_ap(target); ADIv5_AP_t *ap = adiv5_target_ap(target);
@ -486,14 +538,14 @@ static int samd20_flash_write(struct target_s *target, uint32_t dest,
uint32_t end = (dest + len - 1) & ~0x3; uint32_t end = (dest + len - 1) & ~0x3;
/* The start address of the first page involved in the write */ /* The start address of the first page involved in the write */
uint32_t first_page = dest & ~(SAMD20_PAGE_SIZE - 1); uint32_t first_page = dest & ~(SAMD_PAGE_SIZE - 1);
/* The start address of the last page involved in the write */ /* The start address of the last page involved in the write */
uint32_t last_page = (dest + len - 1) & ~(SAMD20_PAGE_SIZE - 1); uint32_t last_page = (dest + len - 1) & ~(SAMD_PAGE_SIZE - 1);
uint32_t end_of_this_page; uint32_t end_of_this_page;
for (uint32_t page = first_page; page <= last_page; page += SAMD20_PAGE_SIZE) { for (uint32_t page = first_page; page <= last_page; page += SAMD_PAGE_SIZE) {
end_of_this_page = page + (SAMD20_PAGE_SIZE - 4); end_of_this_page = page + (SAMD_PAGE_SIZE - 4);
if (addr > page || (page == last_page && end < end_of_this_page)) { if (addr > page || (page == last_page && end < end_of_this_page)) {
/* Setup write */ /* Setup write */
@ -509,17 +561,17 @@ static int samd20_flash_write(struct target_s *target, uint32_t dest,
} }
/* Unlock */ /* Unlock */
samd20_unlock_current_address(target); samd_unlock_current_address(target);
/* Issue the write page command */ /* Issue the write page command */
adiv5_ap_mem_write(ap, SAMD20_NVMC_CTRLA, adiv5_ap_mem_write(ap, SAMD_NVMC_CTRLA,
SAMD20_CTRLA_CMD_KEY | SAMD20_CTRLA_CMD_WRITEPAGE); SAMD_CTRLA_CMD_KEY | SAMD_CTRLA_CMD_WRITEPAGE);
} else { } else {
/* Write first word to set address */ /* Write first word to set address */
adiv5_ap_mem_write(ap, addr, data[i]); addr += 4; i++; adiv5_ap_mem_write(ap, addr, data[i]); addr += 4; i++;
/* Unlock */ /* Unlock */
samd20_unlock_current_address(target); samd_unlock_current_address(target);
/* Set up write */ /* Set up write */
adiv5_ap_write(ap, ADIV5_AP_CSW, ap->csw | adiv5_ap_write(ap, ADIV5_AP_CSW, ap->csw |
@ -529,18 +581,18 @@ static int samd20_flash_write(struct target_s *target, uint32_t dest,
((uint32_t)ap->apsel << 24)|(ADIV5_AP_DRW & 0xF0)); ((uint32_t)ap->apsel << 24)|(ADIV5_AP_DRW & 0xF0));
/* Full, automatic page write */ /* Full, automatic page write */
for (; addr < page + SAMD20_PAGE_SIZE; addr += 4, i++) { for (; addr < page + SAMD_PAGE_SIZE; addr += 4, i++) {
adiv5_dp_write_ap(ap->dp, ADIV5_AP_DRW, data[i]); adiv5_dp_write_ap(ap->dp, ADIV5_AP_DRW, data[i]);
} }
} }
/* Poll for NVM Ready */ /* Poll for NVM Ready */
while ((adiv5_ap_mem_read(ap, SAMD20_NVMC_INTFLAG) & SAMD20_NVMC_READY) == 0) while ((adiv5_ap_mem_read(ap, SAMD_NVMC_INTFLAG) & SAMD_NVMC_READY) == 0)
if(target_check_error(target)) if(target_check_error(target))
return -1; return -1;
/* Lock */ /* Lock */
samd20_lock_current_address(target); samd_lock_current_address(target);
} }
return 0; return 0;
@ -549,32 +601,32 @@ static int samd20_flash_write(struct target_s *target, uint32_t dest,
/** /**
* Uses the Device Service Unit to erase the entire flash * Uses the Device Service Unit to erase the entire flash
*/ */
static bool samd20_cmd_erase_all(target *t) static bool samd_cmd_erase_all(target *t)
{ {
ADIv5_AP_t *ap = adiv5_target_ap(t); ADIv5_AP_t *ap = adiv5_target_ap(t);
/* Clear the DSU status bits */ /* Clear the DSU status bits */
adiv5_ap_mem_write(ap, SAMD20_DSU_CTRLSTAT, adiv5_ap_mem_write(ap, SAMD_DSU_CTRLSTAT,
(SAMD20_STATUSA_DONE | SAMD20_STATUSA_PERR | SAMD20_STATUSA_FAIL)); (SAMD_STATUSA_DONE | SAMD_STATUSA_PERR | SAMD_STATUSA_FAIL));
/* Erase all */ /* Erase all */
adiv5_ap_mem_write(ap, SAMD20_DSU_CTRLSTAT, SAMD20_CTRL_CHIP_ERASE); adiv5_ap_mem_write(ap, SAMD_DSU_CTRLSTAT, SAMD_CTRL_CHIP_ERASE);
/* Poll for DSU Ready */ /* Poll for DSU Ready */
uint32_t status; uint32_t status;
while (((status = adiv5_ap_mem_read(ap, SAMD20_DSU_CTRLSTAT)) & while (((status = adiv5_ap_mem_read(ap, SAMD_DSU_CTRLSTAT)) &
(SAMD20_STATUSA_DONE | SAMD20_STATUSA_PERR | SAMD20_STATUSA_FAIL)) == 0) (SAMD_STATUSA_DONE | SAMD_STATUSA_PERR | SAMD_STATUSA_FAIL)) == 0)
if(target_check_error(t)) if(target_check_error(t))
return false; return false;
/* Test the protection error bit in Status A */ /* Test the protection error bit in Status A */
if (status & SAMD20_STATUSA_PERR) { if (status & SAMD_STATUSA_PERR) {
gdb_outf("Erase failed due to a protection error.\n"); gdb_outf("Erase failed due to a protection error.\n");
return true; return true;
} }
/* Test the fail bit in Status A */ /* Test the fail bit in Status A */
if (status & SAMD20_STATUSA_FAIL) { if (status & SAMD_STATUSA_FAIL) {
gdb_outf("Erase failed.\n"); gdb_outf("Erase failed.\n");
return true; return true;
} }
@ -591,22 +643,22 @@ static bool samd20_cmd_erase_all(target *t)
* *
* 0x0000 = Lock, 0xFFFF = Unlock (default) * 0x0000 = Lock, 0xFFFF = Unlock (default)
*/ */
static bool samd20_set_flashlock(target *t, uint16_t value) static bool samd_set_flashlock(target *t, uint16_t value)
{ {
ADIv5_AP_t *ap = adiv5_target_ap(t); ADIv5_AP_t *ap = adiv5_target_ap(t);
uint32_t high = adiv5_ap_mem_read(ap, SAMD20_NVM_USER_ROW_HIGH); uint32_t high = adiv5_ap_mem_read(ap, SAMD_NVM_USER_ROW_HIGH);
uint32_t low = adiv5_ap_mem_read(ap, SAMD20_NVM_USER_ROW_LOW); uint32_t low = adiv5_ap_mem_read(ap, SAMD_NVM_USER_ROW_LOW);
/* Write address of a word in the row to erase it */ /* Write address of a word in the row to erase it */
/* Must be shifted right for 16-bit address, see Datasheet §20.8.8 Address */ /* Must be shifted right for 16-bit address, see Datasheet §20.8.8 Address */
adiv5_ap_mem_write(ap, SAMD20_NVMC_ADDRESS, SAMD20_NVM_USER_ROW_LOW >> 1); adiv5_ap_mem_write(ap, SAMD_NVMC_ADDRESS, SAMD_NVM_USER_ROW_LOW >> 1);
/* Issue the erase command */ /* Issue the erase command */
adiv5_ap_mem_write(ap, SAMD20_NVMC_CTRLA, SAMD20_CTRLA_CMD_KEY | SAMD20_CTRLA_CMD_ERASEAUXROW); adiv5_ap_mem_write(ap, SAMD_NVMC_CTRLA, SAMD_CTRLA_CMD_KEY | SAMD_CTRLA_CMD_ERASEAUXROW);
/* Poll for NVM Ready */ /* Poll for NVM Ready */
while ((adiv5_ap_mem_read(ap, SAMD20_NVMC_INTFLAG) & SAMD20_NVMC_READY) == 0) while ((adiv5_ap_mem_read(ap, SAMD_NVMC_INTFLAG) & SAMD_NVMC_READY) == 0)
if(target_check_error(t)) if(target_check_error(t))
return -1; return -1;
@ -614,44 +666,44 @@ static bool samd20_set_flashlock(target *t, uint16_t value)
high = (high & 0x0000FFFF) | ((value << 16) & 0xFFFF0000); high = (high & 0x0000FFFF) | ((value << 16) & 0xFFFF0000);
/* Write back */ /* Write back */
adiv5_ap_mem_write(ap, SAMD20_NVM_USER_ROW_LOW, low); adiv5_ap_mem_write(ap, SAMD_NVM_USER_ROW_LOW, low);
adiv5_ap_mem_write(ap, SAMD20_NVM_USER_ROW_HIGH, high); adiv5_ap_mem_write(ap, SAMD_NVM_USER_ROW_HIGH, high);
/* Issue the page write command */ /* Issue the page write command */
adiv5_ap_mem_write(ap, SAMD20_NVMC_CTRLA, adiv5_ap_mem_write(ap, SAMD_NVMC_CTRLA,
SAMD20_CTRLA_CMD_KEY | SAMD20_CTRLA_CMD_WRITEAUXPAGE); SAMD_CTRLA_CMD_KEY | SAMD_CTRLA_CMD_WRITEAUXPAGE);
return true; return true;
} }
static bool samd20_cmd_lock_flash(target *t) static bool samd_cmd_lock_flash(target *t)
{ {
return samd20_set_flashlock(t, 0x0000); return samd_set_flashlock(t, 0x0000);
} }
static bool samd20_cmd_unlock_flash(target *t) static bool samd_cmd_unlock_flash(target *t)
{ {
return samd20_set_flashlock(t, 0xFFFF); return samd_set_flashlock(t, 0xFFFF);
} }
static bool samd20_cmd_read_userrow(target *t) static bool samd_cmd_read_userrow(target *t)
{ {
ADIv5_AP_t *ap = adiv5_target_ap(t); ADIv5_AP_t *ap = adiv5_target_ap(t);
gdb_outf("User Row: 0x%08x%08x\n", gdb_outf("User Row: 0x%08x%08x\n",
adiv5_ap_mem_read(ap, SAMD20_NVM_USER_ROW_HIGH), adiv5_ap_mem_read(ap, SAMD_NVM_USER_ROW_HIGH),
adiv5_ap_mem_read(ap, SAMD20_NVM_USER_ROW_LOW)); adiv5_ap_mem_read(ap, SAMD_NVM_USER_ROW_LOW));
return true; return true;
} }
/** /**
* Reads the 128-bit serial number from the NVM * Reads the 128-bit serial number from the NVM
*/ */
static bool samd20_cmd_serial(target *t) static bool samd_cmd_serial(target *t)
{ {
ADIv5_AP_t *ap = adiv5_target_ap(t); ADIv5_AP_t *ap = adiv5_target_ap(t);
gdb_outf("Serial Number: 0x"); gdb_outf("Serial Number: 0x");
for (uint32_t i = 0; i < 4; i++) { for (uint32_t i = 0; i < 4; i++) {
gdb_outf("%08x", adiv5_ap_mem_read(ap, SAMD20_NVM_SERIAL(i))); gdb_outf("%08x", adiv5_ap_mem_read(ap, SAMD_NVM_SERIAL(i)));
} }
gdb_outf("\n"); gdb_outf("\n");
@ -661,15 +713,15 @@ static bool samd20_cmd_serial(target *t)
/** /**
* Returns the size (in bytes) of the current SAM D20's flash memory. * Returns the size (in bytes) of the current SAM D20's flash memory.
*/ */
static uint32_t samd20_flash_size(target *t) static uint32_t samd_flash_size(target *t)
{ {
ADIv5_AP_t *ap = adiv5_target_ap(t); ADIv5_AP_t *ap = adiv5_target_ap(t);
/* Read the Device ID */ /* Read the Device ID */
uint32_t did = adiv5_ap_mem_read(ap, SAMD20_DSU_DID); uint32_t did = adiv5_ap_mem_read(ap, SAMD_DSU_DID);
/* Mask off the device select bits */ /* Mask off the device select bits */
uint8_t devsel = did & SAMD20_DID_DEVSEL_MASK; uint8_t devsel = did & SAMD_DID_DEVSEL_MASK;
/* Shift the maximum flash size (256KB) down as appropriate */ /* Shift the maximum flash size (256KB) down as appropriate */
return (0x40000 >> (devsel % 5)); return (0x40000 >> (devsel % 5));
@ -677,37 +729,37 @@ static uint32_t samd20_flash_size(target *t)
/** /**
* Runs the Memory Built In Self Test (MBIST) * Runs the Memory Built In Self Test (MBIST)
*/ */
static bool samd20_cmd_mbist(target *t) static bool samd_cmd_mbist(target *t)
{ {
ADIv5_AP_t *ap = adiv5_target_ap(t); ADIv5_AP_t *ap = adiv5_target_ap(t);
/* Write the memory parameters to the DSU */ /* Write the memory parameters to the DSU */
adiv5_ap_mem_write(ap, SAMD20_DSU_ADDRESS, 0); adiv5_ap_mem_write(ap, SAMD_DSU_ADDRESS, 0);
adiv5_ap_mem_write(ap, SAMD20_DSU_LENGTH, samd20_flash_size(t)); adiv5_ap_mem_write(ap, SAMD_DSU_LENGTH, samd_flash_size(t));
/* Clear the fail bit */ /* Clear the fail bit */
adiv5_ap_mem_write(ap, SAMD20_DSU_CTRLSTAT, SAMD20_STATUSA_FAIL); adiv5_ap_mem_write(ap, SAMD_DSU_CTRLSTAT, SAMD_STATUSA_FAIL);
/* Write the MBIST command */ /* Write the MBIST command */
adiv5_ap_mem_write(ap, SAMD20_DSU_CTRLSTAT, SAMD20_CTRL_MBIST); adiv5_ap_mem_write(ap, SAMD_DSU_CTRLSTAT, SAMD_CTRL_MBIST);
/* Poll for DSU Ready */ /* Poll for DSU Ready */
uint32_t status; uint32_t status;
while (((status = adiv5_ap_mem_read(ap, SAMD20_DSU_CTRLSTAT)) & while (((status = adiv5_ap_mem_read(ap, SAMD_DSU_CTRLSTAT)) &
(SAMD20_STATUSA_DONE | SAMD20_STATUSA_PERR | SAMD20_STATUSA_FAIL)) == 0) (SAMD_STATUSA_DONE | SAMD_STATUSA_PERR | SAMD_STATUSA_FAIL)) == 0)
if(target_check_error(t)) if(target_check_error(t))
return false; return false;
/* Test the protection error bit in Status A */ /* Test the protection error bit in Status A */
if (status & SAMD20_STATUSA_PERR) { if (status & SAMD_STATUSA_PERR) {
gdb_outf("MBIST not run due to protection error.\n"); gdb_outf("MBIST not run due to protection error.\n");
return true; return true;
} }
/* Test the fail bit in Status A */ /* Test the fail bit in Status A */
if (status & SAMD20_STATUSA_FAIL) { if (status & SAMD_STATUSA_FAIL) {
gdb_outf("MBIST Fail @ 0x%08x\n", gdb_outf("MBIST Fail @ 0x%08x\n",
adiv5_ap_mem_read(ap, SAMD20_DSU_ADDRESS)); adiv5_ap_mem_read(ap, SAMD_DSU_ADDRESS));
} else { } else {
gdb_outf("MBIST Passed!\n"); gdb_outf("MBIST Passed!\n");
} }
@ -717,15 +769,15 @@ static bool samd20_cmd_mbist(target *t)
/** /**
* Sets the security bit * Sets the security bit
*/ */
static bool samd20_cmd_ssb(target *t) static bool samd_cmd_ssb(target *t)
{ {
ADIv5_AP_t *ap = adiv5_target_ap(t); ADIv5_AP_t *ap = adiv5_target_ap(t);
/* Issue the ssb command */ /* Issue the ssb command */
adiv5_ap_mem_write(ap, SAMD20_NVMC_CTRLA, SAMD20_CTRLA_CMD_KEY | SAMD20_CTRLA_CMD_SSB); adiv5_ap_mem_write(ap, SAMD_NVMC_CTRLA, SAMD_CTRLA_CMD_KEY | SAMD_CTRLA_CMD_SSB);
/* Poll for NVM Ready */ /* Poll for NVM Ready */
while ((adiv5_ap_mem_read(ap, SAMD20_NVMC_INTFLAG) & SAMD20_NVMC_READY) == 0) while ((adiv5_ap_mem_read(ap, SAMD_NVMC_INTFLAG) & SAMD_NVMC_READY) == 0)
if(target_check_error(t)) if(target_check_error(t))
return -1; return -1;