adiv5: Cleaned up a couple of the debug prints
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parent
7c14b62419
commit
57fec4d0b6
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@ -443,7 +443,7 @@ static bool cortexm_prepare(ADIv5_AP_t *ap)
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}
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}
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/* Return true if we find a debuggable device.*/
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/* Return true if we find a debuggable device.*/
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static void adiv5_component_probe(ADIv5_AP_t *ap, uint32_t addr, const size_t recursion, const size_t num_entry)
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static void adiv5_component_probe(ADIv5_AP_t *ap, uint32_t addr, const size_t recursion, const uint32_t num_entry)
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{
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{
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(void)num_entry;
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(void)num_entry;
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@ -474,14 +474,13 @@ static void adiv5_component_probe(ADIv5_AP_t *ap, uint32_t addr, const size_t re
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/* CIDR preamble sanity check */
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/* CIDR preamble sanity check */
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if ((cidr & ~CID_CLASS_MASK) != CID_PREAMBLE) {
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if ((cidr & ~CID_CLASS_MASK) != CID_PREAMBLE) {
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DEBUG_WARN("%s%d 0x%08" PRIx32 ": 0x%08" PRIx32 " <- does not match preamble (0x%X)\n", indent + 1, num_entry,
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DEBUG_WARN("%s%" PRIu32 " 0x%08" PRIx32 ": 0x%08" PRIx32 " <- does not match preamble (0x%lX)\n", indent + 1,
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addr, cidr, CID_PREAMBLE);
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num_entry, addr, cidr, CID_PREAMBLE);
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return;
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return;
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}
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}
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/* Extract Component ID class nibble */
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/* Extract Component ID class nibble */
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const uint32_t cid_class = (cidr & CID_CLASS_MASK) >> CID_CLASS_SHIFT;
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const uint32_t cid_class = (cidr & CID_CLASS_MASK) >> CID_CLASS_SHIFT;
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const uint64_t pidr = adiv5_ap_read_pidr(ap, addr);
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const uint64_t pidr = adiv5_ap_read_pidr(ap, addr);
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uint16_t designer_code;
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uint16_t designer_code;
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@ -561,8 +560,8 @@ static void adiv5_component_probe(ADIv5_AP_t *ap, uint32_t addr, const size_t re
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} else {
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} else {
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if (designer_code != JEP106_MANUFACTURER_ARM) {
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if (designer_code != JEP106_MANUFACTURER_ARM) {
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/* non arm components not supported currently */
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/* non arm components not supported currently */
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DEBUG_WARN("%s0x%" PRIx32 ": 0x%02" PRIx32 "%08" PRIx32 " Non ARM component ignored\n", indent, addr,
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DEBUG_WARN("%s0x%" PRIx32 ": 0x%08" PRIx32 "%08" PRIx32 " Non ARM component ignored\n", indent, addr,
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(uint32_t)(pidr >> 32), (uint32_t)pidr);
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(uint32_t)(pidr >> 32U), (uint32_t)pidr);
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return;
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return;
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}
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}
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@ -586,10 +585,10 @@ static void adiv5_component_probe(ADIv5_AP_t *ap, uint32_t addr, const size_t re
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arm_component_lut[i].arch_id != arch_id)
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arm_component_lut[i].arch_id != arch_id)
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continue;
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continue;
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DEBUG_INFO("%s%d 0x%" PRIx32 ": %s - %s %s (PIDR = 0x%02" PRIx32 "%08" PRIx32 " DEVTYPE = 0x%02" PRIx8
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DEBUG_INFO("%s%" PRIu32 " 0x%" PRIx32 ": %s - %s %s (PIDR = 0x%08" PRIx32 "%08" PRIx32
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" ARCHID = 0x%04" PRIx16 ")\n",
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" DEVTYPE = 0x%02x ARCHID = 0x%04x)\n",
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indent + 1, num_entry, addr, cidc_debug_strings[cid_class], arm_component_lut[i].type,
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indent + 1, num_entry, addr, cidc_debug_strings[cid_class], arm_component_lut[i].type,
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arm_component_lut[i].full, (uint32_t)(pidr >> 32), (uint32_t)pidr, dev_type, arch_id);
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arm_component_lut[i].full, (uint32_t)(pidr >> 32U), (uint32_t)pidr, dev_type, arch_id);
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/* Perform sanity check, if we know what to expect as * component ID class. */
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/* Perform sanity check, if we know what to expect as * component ID class. */
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if (arm_component_lut[i].cidc != cidc_unknown && cid_class != arm_component_lut[i].cidc) {
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if (arm_component_lut[i].cidc != cidc_unknown && cid_class != arm_component_lut[i].cidc) {
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@ -612,9 +611,9 @@ static void adiv5_component_probe(ADIv5_AP_t *ap, uint32_t addr, const size_t re
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break;
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break;
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}
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}
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if (arm_component_lut[i].arch == aa_end) {
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if (arm_component_lut[i].arch == aa_end) {
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DEBUG_WARN("%s%d 0x%" PRIx32 ": %s - Unknown (PIDR = 0x%02" PRIx32 "%08" PRIx32 " DEVTYPE = 0x%02" PRIx8
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DEBUG_WARN("%s%" PRIu32 " 0x%" PRIx32 ": %s - Unknown (PIDR = 0x%08" PRIx32 "%08" PRIx32
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" ARCHID = 0x%04" PRIx16 ")\n",
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" DEVTYPE = 0x%02x ARCHID = 0x%04x)\n",
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indent, num_entry, addr, cidc_debug_strings[cid_class], (uint32_t)(pidr >> 32), (uint32_t)pidr,
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indent, num_entry, addr, cidc_debug_strings[cid_class], (uint32_t)(pidr >> 32U), (uint32_t)pidr,
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dev_type, arch_id);
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dev_type, arch_id);
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}
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}
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}
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}
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