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target/adi: rename missleading idcode variable

This commit is contained in:
Rafael Silva 2022-07-29 15:57:47 +01:00 committed by Rachel Mant
parent a9229a869b
commit 58025feec2
9 changed files with 33 additions and 29 deletions
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4
src/platforms/hosted/jlink_adiv5_swdp.c
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@ -173,10 +173,10 @@ int jlink_swdp_scan(bmp_info_t *info)
return 0; return 0;
volatile struct exception e; volatile struct exception e;
TRY_CATCH (e, EXCEPTION_ALL) { TRY_CATCH (e, EXCEPTION_ALL) {
dp->idcode = jlink_adiv5_swdp_low_access(dp, 1, ADIV5_DP_IDCODE, 0); dp->debug_port_id = jlink_adiv5_swdp_low_access(dp, ADIV5_LOW_READ, ADIV5_DP_DPIDR, 0);
} }
if (e.type) { if (e.type) {
DEBUG_WARN("DP not responding for IDCODE! Reset stuck low?\n"); DEBUG_WARN("DP not responding for DPIDR! Reset stuck low?\n");
free(dp); free(dp);
return 0; return 0;
} }

4
src/platforms/hosted/stlinkv2.c
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@ -1077,14 +1077,14 @@ int stlink_enter_debug_swd(bmp_info_t *info, ADIv5_DP_t *dp)
stlink_send_recv_retry(cmd, 16, data, 2); stlink_send_recv_retry(cmd, 16, data, 2);
if (stlink_usb_error_check(data, true)) if (stlink_usb_error_check(data, true))
exit( -1); exit( -1);
dp->idcode = stlink_read_coreid(); dp->debug_port_id = stlink_read_coreid();
dp->dp_read = stlink_dp_read; dp->dp_read = stlink_dp_read;
dp->error = stlink_dp_error; dp->error = stlink_dp_error;
dp->low_access = stlink_dp_low_access; dp->low_access = stlink_dp_low_access;
dp->abort = stlink_dp_abort; dp->abort = stlink_dp_abort;
stlink_dp_error(dp); stlink_dp_error(dp);
if ((dp->idcode & ADIV5_DP_DPIDR_VERSION_MASK) == ADIV5_DP_DPIDR_VERSION_DPv2) { if ((dp->debug_port_id & ADIV5_DP_DPIDR_VERSION_MASK) == ADIV5_DP_DPIDR_VERSION_DPv2) {
adiv5_dp_write(dp, ADIV5_DP_SELECT, 2); adiv5_dp_write(dp, ADIV5_DP_SELECT, 2);
dp->targetid = adiv5_dp_read(dp, ADIV5_DP_CTRLSTAT); dp->targetid = adiv5_dp_read(dp, ADIV5_DP_CTRLSTAT);
adiv5_dp_write(dp, ADIV5_DP_SELECT, 0); adiv5_dp_write(dp, ADIV5_DP_SELECT, 0);

21
src/target/adiv5.c
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@ -332,7 +332,7 @@ static uint32_t cortexm_initial_halt(ADIv5_AP_t *ap)
const uint32_t dhcsr_ctl = CORTEXM_DHCSR_DBGKEY | CORTEXM_DHCSR_C_DEBUGEN | CORTEXM_DHCSR_C_HALT; const uint32_t dhcsr_ctl = CORTEXM_DHCSR_DBGKEY | CORTEXM_DHCSR_C_DEBUGEN | CORTEXM_DHCSR_C_HALT;
const uint32_t dhcsr_valid = CORTEXM_DHCSR_S_HALT | CORTEXM_DHCSR_C_DEBUGEN; const uint32_t dhcsr_valid = CORTEXM_DHCSR_S_HALT | CORTEXM_DHCSR_C_DEBUGEN;
const bool use_low_access = !(ap->dp->idcode & ADIV5_DP_DPIDR_MINDP); const bool use_low_access = !(ap->dp->debug_port_id & ADIV5_DP_DPIDR_MINDP);
platform_timeout halt_timeout; platform_timeout halt_timeout;
platform_timeout_set(&halt_timeout, cortexm_wait_timeout); platform_timeout_set(&halt_timeout, cortexm_wait_timeout);
@ -682,25 +682,24 @@ static void rp_rescue_setup(ADIv5_DP_t *dp)
void adiv5_dp_init(ADIv5_DP_t *dp) void adiv5_dp_init(ADIv5_DP_t *dp)
{ {
/* Check IDCODE for a valid manufacturer and sensible PARTNO */ /* Check DPIDR for a valid manufacturer and sensible PARTNO */
/* TODO: this needs clarification, as DPIDR != IDCODE */ if ((dp->debug_port_id & ADIV5_DP_DPIDR_DESIGNER_MASK) == 0 ||
if ((dp->idcode & ADIV5_DP_DPIDR_DESIGNER_MASK) == 0 || (dp->debug_port_id & ADIV5_DP_DPIDR_PARTNO_MASK) == ADIV5_DP_DPIDR_PARTNO_MASK) {
(dp->idcode & ADIV5_DP_DPIDR_PARTNO_MASK) == ADIV5_DP_DPIDR_PARTNO_MASK) { DEBUG_WARN("Invalid DP DPIDR %08" PRIx32 "\n", dp->debug_port_id);
DEBUG_WARN("Invalid DP DPIDR %08" PRIx32 "\n", dp->idcode);
free(dp); free(dp);
return; return;
} }
/* TODO: this could with a non 'magic number' */ /* TODO: this could with a non 'magic number' */
if (dp->idcode == 0x10212927) { if (dp->debug_port_id == 0x10212927) {
rp_rescue_setup(dp); rp_rescue_setup(dp);
return; return;
} }
DEBUG_INFO("DPIDR 0x%08" PRIx32 " (v%d %srev%d)\n", dp->idcode, DEBUG_INFO("DPIDR 0x%08" PRIx32 " (v%d %srev%d)\n", dp->debug_port_id,
(uint8_t)((dp->idcode & ADIV5_DP_DPIDR_VERSION_MASK) >> ADIV5_DP_DPIDR_VERSION_OFFSET), (uint8_t)((dp->debug_port_id & ADIV5_DP_DPIDR_VERSION_MASK) >> ADIV5_DP_DPIDR_VERSION_OFFSET),
(dp->idcode & ADIV5_DP_DPIDR_MINDP) ? "MINDP " : "", (dp->debug_port_id & ADIV5_DP_DPIDR_MINDP) ? "MINDP " : "",
(uint8_t)((dp->idcode & ADIV5_DP_DPIDR_REVISION_MASK) >> ADIV5_DP_DPIDR_REVISION_OFFSET)); (uint8_t)((dp->debug_port_id & ADIV5_DP_DPIDR_REVISION_MASK) >> ADIV5_DP_DPIDR_REVISION_OFFSET));
#if PC_HOSTED == 1 #if PC_HOSTED == 1
platform_adiv5_dp_defaults(dp); platform_adiv5_dp_defaults(dp);

4
src/target/adiv5.h
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@ -38,7 +38,7 @@
#define ADIV5_DP_BANK4 0x40U #define ADIV5_DP_BANK4 0x40U
/* ADIv5 DP Register addresses */ /* ADIv5 DP Register addresses */
#define ADIV5_DP_IDCODE ADIV5_DP_REG(0x0U) #define ADIV5_DP_DPIDR ADIV5_DP_REG(0x0U)
#define ADIV5_DP_ABORT ADIV5_DP_REG(0x0U) #define ADIV5_DP_ABORT ADIV5_DP_REG(0x0U)
#define ADIV5_DP_CTRLSTAT ADIV5_DP_REG(0x4U) #define ADIV5_DP_CTRLSTAT ADIV5_DP_REG(0x4U)
#define ADIV5_DP_TARGETID (ADIV5_DP_BANK2 | ADIV5_DP_REG(0x4U)) #define ADIV5_DP_TARGETID (ADIV5_DP_BANK2 | ADIV5_DP_REG(0x4U))
@ -204,7 +204,7 @@ typedef struct ADIv5_AP_s ADIv5_AP_t;
typedef struct ADIv5_DP_s { typedef struct ADIv5_DP_s {
int refcnt; int refcnt;
uint32_t idcode; uint32_t debug_port_id;
uint32_t targetid; /* Contains IDCODE for DPv2 devices.*/ uint32_t targetid; /* Contains IDCODE for DPv2 devices.*/
void (*seq_out)(uint32_t tms_states, size_t clock_cycles); void (*seq_out)(uint32_t tms_states, size_t clock_cycles);

7
src/target/adiv5_jtagdp.c
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@ -48,7 +48,12 @@ void adiv5_jtag_dp_handler(uint8_t jd_index)
} }
dp->dp_jd_index = jd_index; dp->dp_jd_index = jd_index;
dp->idcode = jtag_devs[jd_index].jd_idcode; /* From the ADI spec :
* The architecture does not require that the TAP IDCODE
* register value and the DPIDR (ADIv5) value are the same
* should read DPIDR here
*/
dp->debug_port_id = jtag_devs[jd_index].jd_idcode;
if ((PC_HOSTED == 0 ) || (!platform_jtag_dp_init(dp))) { if ((PC_HOSTED == 0 ) || (!platform_jtag_dp_init(dp))) {
dp->dp_read = fw_adiv5_jtagdp_read; dp->dp_read = fw_adiv5_jtagdp_read;
dp->error = adiv5_jtagdp_error; dp->error = adiv5_jtagdp_error;

16
src/target/adiv5_swdp.c
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@ -93,7 +93,7 @@ int adiv5_swdp_scan(uint32_t targetid)
* 0x1a Arm CoreSight SW-DP activation sequence * 0x1a Arm CoreSight SW-DP activation sequence
* 20 bits start of reset another reset sequence*/ * 20 bits start of reset another reset sequence*/
initial_dp->seq_out(0x1a0, 12); initial_dp->seq_out(0x1a0, 12);
uint32_t idcode = 0; uint32_t dpidr = 0;
volatile uint32_t target_id = 0; volatile uint32_t target_id = 0;
bool scan_multidrop = true; bool scan_multidrop = true;
if (!targetid || !initial_dp->dp_low_write) { if (!targetid || !initial_dp->dp_low_write) {
@ -102,7 +102,7 @@ int adiv5_swdp_scan(uint32_t targetid)
dp_line_reset(initial_dp); dp_line_reset(initial_dp);
TRY_CATCH (e, EXCEPTION_ALL) { TRY_CATCH (e, EXCEPTION_ALL) {
idcode = initial_dp->dp_read(initial_dp, ADIV5_DP_IDCODE); dpidr = initial_dp->dp_read(initial_dp, ADIV5_DP_DPIDR);
} }
if (e.type || initial_dp->fault) { if (e.type || initial_dp->fault) {
scan_multidrop = false; scan_multidrop = false;
@ -114,14 +114,14 @@ int adiv5_swdp_scan(uint32_t targetid)
initial_dp->fault = 0; initial_dp->fault = 0;
TRY_CATCH (e, EXCEPTION_ALL) { TRY_CATCH (e, EXCEPTION_ALL) {
idcode = initial_dp->dp_read(initial_dp, ADIV5_DP_IDCODE); dpidr = initial_dp->dp_read(initial_dp, ADIV5_DP_DPIDR);
} }
if (e.type || initial_dp->fault) { if (e.type || initial_dp->fault) {
DEBUG_WARN("No usable DP found\n"); DEBUG_WARN("No usable DP found\n");
return -1; return -1;
} }
} }
if ((idcode & ADIV5_DP_DPIDR_VERSION_MASK) == ADIV5_DP_DPIDR_VERSION_DPv2) { if ((dpidr & ADIV5_DP_DPIDR_VERSION_MASK) == ADIV5_DP_DPIDR_VERSION_DPv2) {
scan_multidrop = true; scan_multidrop = true;
/* Read TargetID. Can be done with device in WFI, sleep or reset!*/ /* Read TargetID. Can be done with device in WFI, sleep or reset!*/
adiv5_dp_write(initial_dp, ADIV5_DP_SELECT, 2); adiv5_dp_write(initial_dp, ADIV5_DP_SELECT, 2);
@ -153,7 +153,7 @@ int adiv5_swdp_scan(uint32_t targetid)
dp_targetid = (i << 28U) | (target_id & 0x0fffffffU); dp_targetid = (i << 28U) | (target_id & 0x0fffffffU);
initial_dp->dp_low_write(initial_dp, ADIV5_DP_TARGETSEL, dp_targetid); initial_dp->dp_low_write(initial_dp, ADIV5_DP_TARGETSEL, dp_targetid);
TRY_CATCH (e, EXCEPTION_ALL) { TRY_CATCH (e, EXCEPTION_ALL) {
idcode = initial_dp->dp_read(initial_dp, ADIV5_DP_IDCODE); dpidr = initial_dp->dp_read(initial_dp, ADIV5_DP_DPIDR);
} }
if (e.type || initial_dp->fault) { if (e.type || initial_dp->fault) {
continue; continue;
@ -167,7 +167,7 @@ int adiv5_swdp_scan(uint32_t targetid)
continue; continue;
} }
memcpy(dp, initial_dp, sizeof(ADIv5_DP_t)); memcpy(dp, initial_dp, sizeof(ADIv5_DP_t));
dp->idcode = idcode; dp->debug_port_id = dpidr;
dp->targetid = dp_targetid; dp->targetid = dp_targetid;
adiv5_dp_init(dp); adiv5_dp_init(dp);
} }
@ -186,13 +186,13 @@ uint32_t firmware_swdp_read(ADIv5_DP_t *dp, uint16_t addr)
uint32_t firmware_swdp_error(ADIv5_DP_t *dp) uint32_t firmware_swdp_error(ADIv5_DP_t *dp)
{ {
if ((dp->fault && (dp->idcode & ADIV5_DP_DPIDR_VERSION_MASK) == ADIV5_DP_DPIDR_VERSION_DPv2) && dp->dp_low_write) { if ((dp->fault && (dp->debug_port_id & ADIV5_DP_DPIDR_VERSION_MASK) == ADIV5_DP_DPIDR_VERSION_DPv2) && dp->dp_low_write) {
/* On protocoll error target gets deselected. /* On protocoll error target gets deselected.
* With DP Change, another target needs selection. * With DP Change, another target needs selection.
* => Reselect with right target! */ * => Reselect with right target! */
dp_line_reset(dp); dp_line_reset(dp);
dp->dp_low_write(dp, ADIV5_DP_TARGETSEL, dp->targetid); dp->dp_low_write(dp, ADIV5_DP_TARGETSEL, dp->targetid);
dp->dp_read(dp, ADIV5_DP_IDCODE); dp->dp_read(dp, ADIV5_DP_DPIDR);
/* Exception here is unexpected, so do not catch */ /* Exception here is unexpected, so do not catch */
} }
uint32_t err, clr = 0; uint32_t err, clr = 0;

2
src/target/efm32.c
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@ -540,7 +540,7 @@ bool efm32_probe(target *t)
/* Read the IDCODE register from the SW-DP */ /* Read the IDCODE register from the SW-DP */
ADIv5_AP_t *ap = cortexm_ap(t); ADIv5_AP_t *ap = cortexm_ap(t);
uint32_t ap_idcode = ap->dp->idcode; uint32_t ap_idcode = ap->dp->debug_port_id;
/* Check the idcode. See AN0062 Section 2.2 */ /* Check the idcode. See AN0062 Section 2.2 */
if (ap_idcode == 0x2BA01477) { if (ap_idcode == 0x2BA01477) {

2
src/target/lpc17xx.c
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@ -66,7 +66,7 @@ lpc17xx_probe(target *t)
{ {
/* Read the IDCODE register from the SW-DP */ /* Read the IDCODE register from the SW-DP */
ADIv5_AP_t *ap = cortexm_ap(t); ADIv5_AP_t *ap = cortexm_ap(t);
uint32_t ap_idcode = ap->dp->idcode; uint32_t ap_idcode = ap->dp->debug_port_id;
if (ap_idcode == LPC17xx_JTAG_IDCODE || ap_idcode == LPC17xx_SWDP_IDCODE) { if (ap_idcode == LPC17xx_JTAG_IDCODE || ap_idcode == LPC17xx_SWDP_IDCODE) {
/* LPC176x/5x family. See UM10360.pdf 33.7 JTAG TAP Identification*/ /* LPC176x/5x family. See UM10360.pdf 33.7 JTAG TAP Identification*/

2
src/target/stm32l4.c
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@ -515,7 +515,7 @@ bool stm32l4_probe(target *t)
idcode = (ap->dp->targetid >> 16) & 0xfff; idcode = (ap->dp->targetid >> 16) & 0xfff;
} else { } else {
uint32_t idcode_reg = STM32L4_DBGMCU_IDCODE_PHYS; uint32_t idcode_reg = STM32L4_DBGMCU_IDCODE_PHYS;
if (ap->dp->idcode == 0x0Be12477) if (ap->dp->debug_port_id == 0x0Be12477)
idcode_reg = STM32L5_DBGMCU_IDCODE_PHYS; idcode_reg = STM32L5_DBGMCU_IDCODE_PHYS;
idcode = target_mem_read32(t, idcode_reg) & 0xfff; idcode = target_mem_read32(t, idcode_reg) & 0xfff;
DEBUG_INFO("Idcode %08" PRIx32 "\n", idcode); DEBUG_INFO("Idcode %08" PRIx32 "\n", idcode);