Whitespace.
This commit is contained in:
Gareth McMullin
parent
1366c32f89
commit
5c337c9aa7
70
src/samd.c
70
src/samd.c
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@ -59,7 +59,7 @@ const struct command_s samd_cmd_list[] = {
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{"user_row", (cmd_handler)samd_cmd_read_userrow, "Prints user row from flash"},
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{"serial", (cmd_handler)samd_cmd_serial, "Prints serial number"},
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{"mbist", (cmd_handler)samd_cmd_mbist, "Runs the built-in memory test"},
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{"set_security_bit", (cmd_handler)samd_cmd_ssb, "Sets the Security Bit"},
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{"set_security_bit", (cmd_handler)samd_cmd_ssb, "Sets the Security Bit"},
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{NULL, NULL, NULL}
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};
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@ -222,14 +222,14 @@ samd_reset(struct target_s *target)
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* or SYSRESETREQ: 0x05FA0004 (system reset)
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*/
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target_mem_write32(target, CORTEXM_AIRCR,
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CORTEXM_AIRCR_VECTKEY | CORTEXM_AIRCR_SYSRESETREQ);
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CORTEXM_AIRCR_VECTKEY | CORTEXM_AIRCR_SYSRESETREQ);
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/* Exit extended reset */
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if (target_mem_read32(target, SAMD_DSU_CTRLSTAT) &
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SAMD_STATUSA_CRSTEXT) {
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/* Write bit to clear from extended reset */
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target_mem_write32(target, SAMD_DSU_CTRLSTAT,
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SAMD_STATUSA_CRSTEXT);
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SAMD_STATUSA_CRSTEXT);
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}
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/* Poll for release from reset */
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@ -301,10 +301,10 @@ samd_protected_attach(struct target_s *target)
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* regain access to the chip.
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*/
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/* Patch back in the normal cortexm attach for next time */
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target->attach = cortexm_attach;
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/* Patch back in the normal cortexm attach for next time */
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target->attach = cortexm_attach;
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/* Allow attach this time */
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/* Allow attach this time */
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return true;
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}
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@ -387,11 +387,11 @@ bool samd_probe(struct target_s *target)
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SAMD_DSU_CTRLSTAT);
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struct samd_descr samd = samd_parse_device_id(did);
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/* Protected? */
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int protected = (ctrlstat & SAMD_STATUSB_PROT);
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/* Protected? */
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int protected = (ctrlstat & SAMD_STATUSB_PROT);
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/* Part String */
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if (protected) {
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if (protected) {
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sprintf(variant_string,
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"Atmel SAMD%d%c%dA%s (rev %c) (PROT=1)",
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samd.series, samd.pin, samd.mem,
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@ -401,7 +401,7 @@ bool samd_probe(struct target_s *target)
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"Atmel SAMD%d%c%dA%s (rev %c)",
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samd.series, samd.pin, samd.mem,
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samd.package, samd.revision);
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}
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}
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/* Setup Target */
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target->driver = variant_string;
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@ -489,7 +489,7 @@ static int samd_flash_erase(struct target_s *target, uint32_t addr, size_t len)
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SAMD_CTRLA_CMD_KEY | SAMD_CTRLA_CMD_ERASEROW);
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/* Poll for NVM Ready */
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while ((target_mem_read32(target, SAMD_NVMC_INTFLAG) & SAMD_NVMC_READY) == 0)
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if(target_check_error(target))
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if (target_check_error(target))
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return -1;
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/* Lock */
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@ -534,22 +534,22 @@ static int samd_flash_write(struct target_s *target, uint32_t dest,
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length = MINIMUM(end + 4, next_page) - addr;
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/* Write within a single page. This may be part or all of the page */
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target_mem_write(target, addr, &data[i], length);
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addr += length; i += (length >> 2);
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target_mem_write(target, addr, &data[i], length);
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addr += length; i += (length >> 2);
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/* If MANW=0 (default) we may have triggered an automatic
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* write. Ignore this */
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/* If MANW=0 (default) we may have triggered an automatic
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* write. Ignore this */
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/* Unlock */
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samd_unlock_current_address(target);
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/* Unlock */
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samd_unlock_current_address(target);
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/* Issue the write page command */
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target_mem_write32(target, SAMD_NVMC_CTRLA,
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SAMD_CTRLA_CMD_KEY | SAMD_CTRLA_CMD_WRITEPAGE);
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/* Issue the write page command */
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target_mem_write32(target, SAMD_NVMC_CTRLA,
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SAMD_CTRLA_CMD_KEY | SAMD_CTRLA_CMD_WRITEPAGE);
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/* Poll for NVM Ready */
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while ((target_mem_read32(target, SAMD_NVMC_INTFLAG) & SAMD_NVMC_READY) == 0)
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if(target_check_error(target))
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if (target_check_error(target))
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return -1;
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/* Lock */
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@ -564,9 +564,10 @@ static int samd_flash_write(struct target_s *target, uint32_t dest,
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*/
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static bool samd_cmd_erase_all(target *t)
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{
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/* Clear the DSU status bits */
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/* Clear the DSU status bits */
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target_mem_write32(t, SAMD_DSU_CTRLSTAT,
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(SAMD_STATUSA_DONE | SAMD_STATUSA_PERR | SAMD_STATUSA_FAIL));
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SAMD_STATUSA_DONE | SAMD_STATUSA_PERR |
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SAMD_STATUSA_FAIL);
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/* Erase all */
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target_mem_write32(t, SAMD_DSU_CTRLSTAT, SAMD_CTRL_CHIP_ERASE);
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@ -575,7 +576,7 @@ static bool samd_cmd_erase_all(target *t)
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uint32_t status;
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while (((status = target_mem_read32(t, SAMD_DSU_CTRLSTAT)) &
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(SAMD_STATUSA_DONE | SAMD_STATUSA_PERR | SAMD_STATUSA_FAIL)) == 0)
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if(target_check_error(t))
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if (target_check_error(t))
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return false;
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/* Test the protection error bit in Status A */
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@ -617,7 +618,7 @@ static bool samd_set_flashlock(target *t, uint16_t value)
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/* Poll for NVM Ready */
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while ((target_mem_read32(t, SAMD_NVMC_INTFLAG) & SAMD_NVMC_READY) == 0)
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if(target_check_error(t))
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if (target_check_error(t))
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return -1;
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/* Modify the high byte of the user row */
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@ -631,16 +632,19 @@ static bool samd_set_flashlock(target *t, uint16_t value)
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target_mem_write32(t, SAMD_NVMC_CTRLA,
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SAMD_CTRLA_CMD_KEY | SAMD_CTRLA_CMD_WRITEAUXPAGE);
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return true;
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return true;
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}
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static bool samd_cmd_lock_flash(target *t)
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{
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return samd_set_flashlock(t, 0x0000);
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}
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static bool samd_cmd_unlock_flash(target *t)
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{
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return samd_set_flashlock(t, 0xFFFF);
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}
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static bool samd_cmd_read_userrow(target *t)
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{
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gdb_outf("User Row: 0x%08x%08x\n",
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@ -649,6 +653,7 @@ static bool samd_cmd_read_userrow(target *t)
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return true;
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}
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/**
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* Reads the 128-bit serial number from the NVM
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*/
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@ -664,6 +669,7 @@ static bool samd_cmd_serial(target *t)
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return true;
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}
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/**
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* Returns the size (in bytes) of the current SAM D20's flash memory.
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*/
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@ -678,6 +684,7 @@ static uint32_t samd_flash_size(target *t)
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/* Shift the maximum flash size (256KB) down as appropriate */
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return (0x40000 >> (devsel % 5));
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}
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/**
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* Runs the Memory Built In Self Test (MBIST)
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*/
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@ -697,7 +704,7 @@ static bool samd_cmd_mbist(target *t)
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uint32_t status;
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while (((status = target_mem_read32(t, SAMD_DSU_CTRLSTAT)) &
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(SAMD_STATUSA_DONE | SAMD_STATUSA_PERR | SAMD_STATUSA_FAIL)) == 0)
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if(target_check_error(t))
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if (target_check_error(t))
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return false;
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/* Test the protection error bit in Status A */
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@ -709,7 +716,7 @@ static bool samd_cmd_mbist(target *t)
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/* Test the fail bit in Status A */
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if (status & SAMD_STATUSA_FAIL) {
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gdb_outf("MBIST Fail @ 0x%08x\n",
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target_mem_read32(t, SAMD_DSU_ADDRESS));
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target_mem_read32(t, SAMD_DSU_ADDRESS));
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} else {
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gdb_outf("MBIST Passed!\n");
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}
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@ -725,9 +732,9 @@ static bool samd_cmd_ssb(target *t)
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target_mem_write32(t, SAMD_NVMC_CTRLA,
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SAMD_CTRLA_CMD_KEY | SAMD_CTRLA_CMD_SSB);
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/* Poll for NVM Ready */
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while ((target_mem_read32(t, SAMD_NVMC_INTFLAG) & SAMD_NVMC_READY) == 0)
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if(target_check_error(t))
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/* Poll for NVM Ready */
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while ((target_mem_read32(t, SAMD_NVMC_INTFLAG) & SAMD_NVMC_READY) == 0)
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if (target_check_error(t))
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return -1;
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gdb_outf("Set the security bit! "
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@ -735,3 +742,4 @@ static bool samd_cmd_ssb(target *t)
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return true;
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}
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