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misc: Updated comments and READMEs to properly reflect pinouts and function

This commit is contained in:
dragonmux 2022-06-15 21:44:04 -04:00 committed by Piotr Esden-Tempski
parent 2eaa579965
commit 5edf549b48
18 changed files with 78 additions and 89 deletions
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16
src/platforms/96b_carbon/Readme.md
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@ -12,14 +12,14 @@ The order matches that of the SWD pins for easy hook up.
JTAG/SWD JTAG/SWD
-------- --------
* LS-02 (PB12): TDO/TRACESWO * LS-02 (PB12): TDO/TRACESWO
* LS-04 (PB15): TDI * LS-04 (PB15): TDI
* LS-06 (PB14): TMS/SWDIO * LS-06 (PB14): TMS/SWDIO
* LS-08 (PB13): TCK/SWCLK * LS-08 (PB13): TCK/SWCLK
* LS-10 : GND * LS-10 : GND
* LS-12 : Vcc * LS-12 : Vcc
* LS-14 (PC3) : TRST (optional test reset) * LS-14 (PC3) : TRST (optional Test Reset)
* LS-16 (PC5) : SRST (system reset) * LS-16 (PC5) : nRST (nRST / System Reset)
LEDs LEDs
---- ----

25
src/platforms/96b_carbon/platform.h
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@ -33,21 +33,21 @@
#define PLATFORM_HAS_TRACESWO #define PLATFORM_HAS_TRACESWO
#define PLATFORM_IDENT "(Carbon)" #define PLATFORM_IDENT "(Carbon)"
#
/* Important pin mappings for Carbon implementation: /* Important pin mappings for Carbon implementation:
* *
* LED0 = PA15 (Green USR2 : Idle)) * LED0 = PA15 (Green USR2 : Idle))
* LED1 = PD5 (Green USR1 : UART) * LED1 = PD5 (Green USR1 : UART)
* LED2 = PB5 (Blue BT : Error) * LED2 = PB5 (Blue BT : Error)
* *
* TDO = PB12 (LS-02) * TDO = PB12 (LS-02)
* TDI = PB15 (LS-04) * TDI = PB15 (LS-04)
* TMS/SWDIO = PB14 (LS-06) The pinout for the programmer allows a Carbon to * TMS/SWDIO = PB14 (LS-06) The pinout for the programmer allows a Carbon to
* TCK/SWCLK = PB13 (LS-08) program another Carbon (either the STM32 or the * TCK/SWCLK = PB13 (LS-08) program another Carbon (either the STM32 or the
* GND (LS-10) nRF51) with adjacent pins from LS-06 to LS-12. * GND (LS-10) nRF51) with adjacent pins from LS-06 to LS-12.
* VCC (LS-12) The order matches the SWD pins for easy hook up. * VCC (LS-12) The order matches the SWD pins for easy hook up.
* nTRST = PC3 (LS-14) * nTRST = PC3 (LS-14)
* nSRST = PC5 (LS-16) * nRST = PC5 (LS-16)
*/ */
/* Hardware definitions... */ /* Hardware definitions... */
@ -162,4 +162,3 @@ static inline int platform_hwversion(void)
#define snprintf sniprintf #define snprintf sniprintf
#endif #endif

12
src/platforms/blackpillv2/Readme.md
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@ -7,12 +7,12 @@ https://github.com/WeActTC/MiniSTM32F4x1
## Connections: ## Connections:
* JTAG/SWD * JTAG/SWD
* PA1: TDI * PA1: TDI
* PA13: TMS/SWDIO * PA13: TMS/SWDIO
* PA14: TCK/SWCLK * PA14: TCK/SWCLK
* PB3: TDO/TRACESWO * PB3: TDO/TRACESWO
* PB5: TRST * PB5: TRST
* PB4: SRST * PB4: nRST
* USB USART * USB USART
* PB6: USART1 TX (usbuart_xxx) * PB6: USART1 TX (usbuart_xxx)

12
src/platforms/blackpillv2/platform.h
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@ -34,12 +34,12 @@
#define PLATFORM_IDENT "(BlackPillV2) " #define PLATFORM_IDENT "(BlackPillV2) "
/* Important pin mappings for STM32 implementation: /* Important pin mappings for STM32 implementation:
* JTAG/SWD * JTAG/SWD
* PA1: TDI<br> * PA1: TDI
* PA13: TMS/SWDIO<br> * PA13: TMS/SWDIO
* PA14: TCK/SWCLK<br> * PA14: TCK/SWCLK
* PB3: TDO/TRACESWO<br> * PB3: TDO/TRACESWO
* PB5: TRST<br> * PB5: TRST
* PB4: SRST<br> * PB4: nRST
* USB USART * USB USART
* PB6: USART1 TX * PB6: USART1 TX
* PB7: USART1 RX * PB7: USART1 RX

28
src/platforms/f072/Readme
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@ -6,19 +6,15 @@ bootloder unconditional.
Connections: Connections:
==================== ====================
PA0: User button to force system bootloader entry with reset * PA0: User button to force system bootloader entry with reset
PA2/PA3 eventual connected to the STLINK/ STM32F103C8 * PA2/PA3 eventual connected to the STLINK/ STM32F103C8
* PA0: TDI
PA0: TDI * PA1: TMS/SWDIO
PA1: TMS/SWDIO * PA7: TCK/SWCLK
PA7: TCK/SWCLK * PA6: TDO/TRACESWO
PA6: TDO/TRACESWO * PA5: TRST
* PB5: LED green
PA5: TRST * PB6: LED yellow
* PB7: LED red
PB5: LED green * PB0: VTARGET
PB6: LED yellow * PB1: VUSB
PB7: LED red
PB0: VTARGET
PB1: VUSB

2
src/platforms/f072/platform.h
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@ -48,7 +48,7 @@
* TMS = PA1 (input for SWDP) * TMS = PA1 (input for SWDP)
* TCK = PA7/SWCLK * TCK = PA7/SWCLK
* TDO = PA6 (input for TRACESWO * TDO = PA6 (input for TRACESWO
* nSRST = PA5 * nRST = PA5
* *
* Force DFU mode button: BOOT0 * Force DFU mode button: BOOT0
*/ */

2
src/platforms/f3/platform.h
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@ -48,7 +48,7 @@
* TMS = PA1 (input for SWDP) * TMS = PA1 (input for SWDP)
* TCK = PA7/SWCLK * TCK = PA7/SWCLK
* TDO = PA6 (input for TRACESWO * TDO = PA6 (input for TRACESWO
* nSRST = PA5 * nRST = PA5
* *
* Force DFU mode button: BOOT0 * Force DFU mode button: BOOT0
*/ */

18
src/platforms/f4discovery/Readme.md
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@ -4,20 +4,14 @@ Allows the use of the STM32F407 Discovery board main cpu as a Black Magic Probe.
## Connections: ## Connections:
PC2: TDI<br> * PC2: TDI
PC4: TMS/SWDIO<br> * PC4: TMS/SWDIO
PC5: TCK/SWCLK<br> * PC5: TCK/SWCLK
PC6: TDO/TRACESWO<br> * PC6: TDO/TRACESWO
* PC1: TRST
PC1: TRST<br> * PC8: nRST
PC8: SRST<br>
How to Flash with dfu How to Flash with dfu
========================================
* After build:
* 1) `apt install dfu-util`
* 2) Force the F4 into system bootloader mode by jumpering "BOOT0" to "3V3" and "PB2/BOOT1" to "GND" and reset (RESET button). System bootloader should appear.
* 3) `dfu-util -a 0 --dfuse-address 0x08000000 -D blackmagic.bin`
To exit from dfu mode press a "key" and "reset", release reset. BMP firmware should appear To exit from dfu mode press a "key" and "reset", release reset. BMP firmware should appear

14
src/platforms/f4discovery/platform.h
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@ -40,13 +40,13 @@
* LED2 = PD12 (Red LED : Error) * LED2 = PD12 (Red LED : Error)
* LED3 = PD15 (Blue LED : Bootloader active) * LED3 = PD15 (Blue LED : Bootloader active)
* *
* nTRST = PC1 * nTRST = PC1
* SRST_OUT = PC8 * nRST_OUT = PC8
* TDI = PC2 * TDI = PC2
* TMS = PC4 (input for SWDP) * TMS = PC4 (input for SWDP)
* TCK = PC5/SWCLK * TCK = PC5/SWCLK
* TDO = PC6 (input for TRACESWO * TDO = PC6 (input for TRACESWO
* nSRST = * nRST = PC8
* *
* Force DFU mode button: PA0 * Force DFU mode button: PA0
*/ */

12
src/platforms/hydrabus/Readme.md
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@ -3,12 +3,12 @@ Connections
* PA0: User button to force system bootloader entry with reset (enter USB DFU) * PA0: User button to force system bootloader entry with reset (enter USB DFU)
* JTAG/SWD * JTAG/SWD
* PC0: TMS/SWDIO * PC0: TMS/SWDIO
* PC1: TCK/SWCLK * PC1: TCK/SWCLK
* PC2: TDI * PC2: TDI
* PC3: TDO/TRACESWO * PC3: TDO/TRACESWO
* PC4: SRST (NRST/System Reset) * PC4: NRST (NRST / System Reset)
* PC5: TRST (optional Test Reset) * PC5: TRST (optional Test Reset)
* Green Led(ULED/PA4): Indicator that system bootloader is entered via BMP * Green Led(ULED/PA4): Indicator that system bootloader is entered via BMP

2
src/platforms/hydrabus/platform.h
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@ -45,7 +45,7 @@
* TCK = PC1 (SWCLK) * TCK = PC1 (SWCLK)
* TDO = PC2 (input for TRACESWO) * TDO = PC2 (input for TRACESWO)
* TDI = PC3 * TDI = PC3
* nSRST = PC4 (nRST /RESET / System Reset) * nRST = PC4 (nRST / nRESET / "System Reset")
* nTRST = PC5 (Test Reset optional) * nTRST = PC5 (Test Reset optional)
* *
* USB VBUS detect: PB13 * USB VBUS detect: PB13

4
src/platforms/native/platform.h
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@ -57,7 +57,7 @@ int usbuart_debug_write(const char *buf, size_t len);
* nTRST = PB1 (output) [blackmagic] * nTRST = PB1 (output) [blackmagic]
* PWR_BR = PB1 (output) [blackmagic_mini] -- supply power to the target, active low * PWR_BR = PB1 (output) [blackmagic_mini] -- supply power to the target, active low
* TMS_DIR = PA1 (output) [blackmagic_mini v2.1] -- choose direction of the TCK pin, input low, output high * TMS_DIR = PA1 (output) [blackmagic_mini v2.1] -- choose direction of the TCK pin, input low, output high
* SRST_OUT = PA2 (output) -- Hardware 5 and older * nRST_OUT = PA2 (output) -- Hardware 5 and older
* = PA9 (output) -- Hardware 6 and newer * = PA9 (output) -- Hardware 6 and newer
* TDI = PA3 (output) -- Hardware 5 and older * TDI = PA3 (output) -- Hardware 5 and older
* = PA7 (output) -- Hardware 6 and newer * = PA7 (output) -- Hardware 6 and newer
@ -68,7 +68,7 @@ int usbuart_debug_write(const char *buf, size_t len);
* Hardware 4 has a normally open jumper between TDO and TRACESWO * Hardware 4 has a normally open jumper between TDO and TRACESWO
* Hardware 5 has hardwired connection between TDO and TRACESWO * Hardware 5 has hardwired connection between TDO and TRACESWO
* = PA10 (input) -- Hardware 6 and newer * = PA10 (input) -- Hardware 6 and newer
* nSRST = PA7 (input) -- Hardware 5 and older * nRST = PA7 (input) -- Hardware 5 and older
* = PC13 (input) -- Hardware 6 and newer * = PC13 (input) -- Hardware 6 and newer
* *
* USB_PU = PA8 (output) * USB_PU = PA8 (output)

2
src/platforms/swlink/README.md
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@ -8,7 +8,7 @@
| JTCK/SWCLK | PA14 | CN5/4 | P2/3 | | JTCK/SWCLK | PA14 | CN5/4 | P2/3 |
| JTDI | PA15 | CN5/6 | P4/11 (38) | | JTDI | PA15 | CN5/6 | P4/11 (38) |
| JTDO | PB3 | CN5/3 | P4/10 (39) | | JTDO | PB3 | CN5/3 | P4/10 (39) |
| SRST | PB4 | CN5/8 | P4/9 (40) | | nRST | PB4 | CN5/8 | P4/9 (40) |
| UART1_TX | PB6 | CN7/4 | P4/7 (42) | | UART1_TX | PB6 | CN7/4 | P4/7 (42) |
| UART1_RX | PB7 | CN7/2 | P4/6 (43) | | UART1_RX | PB7 | CN7/2 | P4/6 (43) |
| SWO/RX2 | PA3 | NA(*1) | P3/8 (13) | | SWO/RX2 | PA3 | NA(*1) | P3/8 (13) |

2
src/target/cortexm.c
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@ -751,7 +751,7 @@ static void cortexm_reset(target *t)
} }
uint32_t dhcsr = target_mem_read32(t, CORTEXM_DHCSR); uint32_t dhcsr = target_mem_read32(t, CORTEXM_DHCSR);
if ((dhcsr & CORTEXM_DHCSR_S_RESET_ST) == 0) { if ((dhcsr & CORTEXM_DHCSR_S_RESET_ST) == 0) {
/* No reset seen yet, maybe as SRST is not connected, or device has /* No reset seen yet, maybe as nRST is not connected, or device has
* CORTEXM_TOPT_INHIBIT_SRST set. * CORTEXM_TOPT_INHIBIT_SRST set.
* Trigger reset by AIRCR.*/ * Trigger reset by AIRCR.*/
target_mem_write32(t, CORTEXM_AIRCR, target_mem_write32(t, CORTEXM_AIRCR,

2
src/target/efm32.c
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@ -949,7 +949,7 @@ static bool efm32_cmd_bootloader(target *t, int argc, const char **argv)
* to boot from this. If you have just unlocked the device the * to boot from this. If you have just unlocked the device the
* bootloader could be anything (even garbage, if the bootloader * bootloader could be anything (even garbage, if the bootloader
* wasn't used before the DEVICEERASE). Therefore you may want to * wasn't used before the DEVICEERASE). Therefore you may want to
* connect under srst and use the bootloader command to disable it. * connect under nrst and use the bootloader command to disable it.
* *
* It is possible to lock the AAP itself by clearing the AAP Lock Word * It is possible to lock the AAP itself by clearing the AAP Lock Word
* (ALW). In this case the part is unrecoverable (unless you glitch * (ALW). In this case the part is unrecoverable (unless you glitch

4
src/target/lmi.c
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@ -88,8 +88,8 @@ bool lmi_probe(target *t)
t->driver = lmi_driver_str; t->driver = lmi_driver_str;
target_add_ram(t, 0x20000000, 0x10000); target_add_ram(t, 0x20000000, 0x10000);
lmi_add_flash(t, 0x80000); lmi_add_flash(t, 0x80000);
/* On Tiva targets, asserting SRST results in the debug /* On Tiva targets, asserting nRST results in the debug
* logic also being reset. We can't assert SRST and must * logic also being reset. We can't assert nRST and must
* only use the AIRCR SYSRESETREQ. */ * only use the AIRCR SYSRESETREQ. */
t->target_options |= CORTEXM_TOPT_INHIBIT_SRST; t->target_options |= CORTEXM_TOPT_INHIBIT_SRST;
return true; return true;

2
src/target/sam4l.c
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@ -262,7 +262,7 @@ sam4l_extended_reset(target *t)
int i; int i;
DEBUG_INFO("SAM4L: Extended Reset\n"); DEBUG_INFO("SAM4L: Extended Reset\n");
/* enable SMAP in case we're dealing with a non-TCK SRST */ /* enable SMAP in case we're dealing with a non-JTAG reset */
target_mem_write32(t, SMAP_CR, 0x1); /* enable SMAP */ target_mem_write32(t, SMAP_CR, 0x1); /* enable SMAP */
reg = target_mem_read32(t, SMAP_SR); reg = target_mem_read32(t, SMAP_SR);
DEBUG_INFO("\nSAM4L: SMAP_SR has 0x%08lx\n", (long unsigned int) reg); DEBUG_INFO("\nSAM4L: SMAP_SR has 0x%08lx\n", (long unsigned int) reg);

8
src/target/samd.c
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@ -227,7 +227,7 @@ static const struct samd_part samd_l22_parts[] = {
void samd_reset(target *t) void samd_reset(target *t)
{ {
/** /**
* SRST is not asserted here as it appears to reset the adiv5 * nRST is not asserted here as it appears to reset the adiv5
* logic, meaning that subsequent adiv5_* calls PLATFORM_FATAL_ERROR. * logic, meaning that subsequent adiv5_* calls PLATFORM_FATAL_ERROR.
* *
* This is ok as normally you can just connect the debugger and go, * This is ok as normally you can just connect the debugger and go,
@ -238,14 +238,14 @@ void samd_reset(target *t)
* See the SAM D20 datasheet §12.6 Debug Operation for more * See the SAM D20 datasheet §12.6 Debug Operation for more
* details. * details.
* *
* jtagtap_srst(true); * jtagtap_nrst(true);
* jtagtap_srst(false); * jtagtap_nrst(false);
*/ */
/* Read DHCSR here to clear S_RESET_ST bit before reset */ /* Read DHCSR here to clear S_RESET_ST bit before reset */
target_mem_read32(t, CORTEXM_DHCSR); target_mem_read32(t, CORTEXM_DHCSR);
/* Request system reset from NVIC: SRST doesn't work correctly */ /* Request System Reset from NVIC: nRST doesn't work correctly */
/* This could be VECTRESET: 0x05FA0001 (reset only core) /* This could be VECTRESET: 0x05FA0001 (reset only core)
* or SYSRESETREQ: 0x05FA0004 (system reset) * or SYSRESETREQ: 0x05FA0004 (system reset)
*/ */