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stlink: Check nRST line level when setting SRST. 

Problem: On some boards flashing hanged.
Cause: Releasing SRST caused a slow rise of nRST and flashing
started while the target still was in reset.
Attention: platform_delay(ms) only resolved 0.1 s.
Nucleo-P boards have SRST unconnected to target nRST by default.
This commit is contained in:
Uwe Bonnes 2018-03-27 12:48:32 +02:00 committed by Gareth McMullin
parent 63967346cd
commit 6127a6431e
2 changed files with 21 additions and 4 deletions
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6
src/platforms/stlink/Readme
View File

@ -9,3 +9,9 @@ ID Pins PC13/14 unconnected PC 13 pulled low
LED STLINK PA8, active High PA9, Dual Led LED STLINK PA8, active High PA9, Dual Led
MCO Out NA PA8 MCO Out NA PA8
RESET(Target) T_JRST(PB1) NRST (PB0) RESET(Target) T_JRST(PB1) NRST (PB0)
On the NucleoXXXP boards, e.g. NUCLEO-L4R5ZI (144 pin) or
NUCLEO-L452RE-P (64 pins), by default nRst is not connected. To reach the
target nRST pin with the "mon connect_srst enable" option, the right NRST
jumper must be placed. On Nucleo144-P boards it is JP3, on NUCLEO64-P
boards it is JP4.

19
src/platforms/stlink/platform.c
View File

@ -90,10 +90,21 @@ void platform_init(void)
void platform_srst_set_val(bool assert) void platform_srst_set_val(bool assert)
{ {
if (assert) uint32_t crl = GPIOB_CRL;
gpio_clear(SRST_PORT, srst_pin); uint32_t shift = (srst_pin == GPIO0) ? 0 : 4;
else uint32_t mask = 0xf << shift;
gpio_set(SRST_PORT, srst_pin); crl &= ~mask;
if (assert) {
/* Set SRST as Open-Drain, 50 Mhz, low.*/
GPIOB_BRR = srst_pin;
GPIOB_CRL = crl | (7 << shift);
} else {
/* Set SRST as input, pull-up.
* SRST might be unconnected, e.g on Nucleo-P!*/
GPIOB_CRL = crl | (8 << shift);
GPIOB_BSRR = srst_pin;
}
while (gpio_get(SRST_PORT, srst_pin) == assert) {};
} }
bool platform_srst_get_val() bool platform_srst_get_val()