[adiv5] Improvements in ADIv5
* Reference latest version of the ARM specification * ROM tables - more debug information, including printing SYSMEM bit * MEM-AP - reject when Debug Base Address entry is not present/invalid. These would only have errored in adiv5_component_probe. * Fix maximum number of entries in Class 0x1 ROM Table to 960. See ARM IHI 0031E Table D3-1 ROM Table register summary. * Resolve note in STM32H7 driver with explaination blackmagic PR #474
This commit is contained in:
Richard Meadows
UweBonnes
parent
703f88a969
commit
61e9607594
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@ -18,8 +18,10 @@
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/* This file implements the transport generic functions of the
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* ARM Debug Interface v5 Architecure Specification, ARM doc IHI0031A.
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/* This file implements the transport generic functions.
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* See the following ARM Reference Documents:
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*
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* ARM Debug Interface v5 Architecure Specification, ARM IHI 0031E
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*/
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#include "general.h"
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#include "target.h"
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@ -287,8 +289,22 @@ static bool adiv5_component_probe(ADIv5_AP_t *ap, uint32_t addr)
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/* Extract Component ID class nibble */
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uint32_t cid_class = (cidr & CID_CLASS_MASK) >> CID_CLASS_SHIFT;
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if (cid_class == cidc_romtab) { /* ROM table, probe recursively */
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for (int i = 0; i < 256; i++) {
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/* ROM table */
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if (cid_class == cidc_romtab) {
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/* Check SYSMEM bit */
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#ifdef ENABLE_DEBUG
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uint32_t memtype = adiv5_mem_read32(ap, addr | ADIV5_ROM_MEMTYPE) &
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ADIV5_ROM_MEMTYPE_SYSMEM;
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if (adiv5_dp_error(ap->dp)) {
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DEBUG("Fault reading ROM table entry\n");
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}
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DEBUG("\nROM: Table BASE=0x%"PRIx32" SYSMEM=0x%"PRIx32"\n",
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addr, memtype);
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#endif
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for (int i = 0; i < 960; i++) {
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uint32_t entry = adiv5_mem_read32(ap, addr + i*4);
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if (adiv5_dp_error(ap->dp)) {
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DEBUG("Fault reading ROM table entry\n");
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@ -297,11 +313,19 @@ static bool adiv5_component_probe(ADIv5_AP_t *ap, uint32_t addr)
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if (entry == 0)
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break;
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if ((entry & 1) == 0)
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if (!(entry & ADIV5_ROM_ROMENTRY_PRESENT)) {
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DEBUG("%d Entry 0x%"PRIx32" -> Not present\n", i, entry);
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continue;
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}
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res |= adiv5_component_probe(ap, addr + (entry & ~0xfff));
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DEBUG("%d Entry 0x%"PRIx32" -> 0x%"PRIx32"\n",
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i, entry, addr + (entry & ADIV5_ROM_ROMENTRY_OFFSET));
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/* Probe recursively */
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res |= adiv5_component_probe(ap,
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addr + (entry & ADIV5_ROM_ROMENTRY_OFFSET));
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}
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DEBUG("ROM: Table END\n\n");
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} else {
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/* Check if the component was designed by ARM, we currently do not support,
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* any components by other designers.
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@ -320,10 +344,10 @@ static bool adiv5_component_probe(ADIv5_AP_t *ap, uint32_t addr)
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int i;
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for (i = 0; pidr_pn_bits[i].arch != aa_end; i++) {
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if (pidr_pn_bits[i].part_number == part_number) {
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DEBUG("0x%"PRIx32": %s - %s %s\n", addr,
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DEBUG("0x%"PRIx32": %s - %s %s (PIDR = 0x%"PRIx64")\n", addr,
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cidc_debug_strings[cid_class],
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pidr_pn_bits[i].type,
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pidr_pn_bits[i].full);
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pidr_pn_bits[i].full, pidr);
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/* Perform sanity check, if we know what to expect as component ID
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* class.
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*/
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@ -366,8 +390,9 @@ ADIv5_AP_t *adiv5_new_ap(ADIv5_DP_t *dp, uint8_t apsel)
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tmpap.dp = dp;
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tmpap.apsel = apsel;
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tmpap.idr = adiv5_ap_read(&tmpap, ADIV5_AP_IDR);
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tmpap.base = adiv5_ap_read(&tmpap, ADIV5_AP_BASE);
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if(!tmpap.idr) /* IDR Invalid - Should we not continue here? */
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if(!tmpap.idr) /* IDR Invalid */
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return NULL;
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/* It's valid to so create a heap copy */
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@ -459,7 +484,11 @@ void adiv5_dp_init(ADIv5_DP_t *dp)
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extern void nrf51_mdm_probe(ADIv5_AP_t *);
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nrf51_mdm_probe(ap);
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if (ap->base == 0xffffffff) {
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/* Check the Debug Base Address register. See ADIv5
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* Specification C2.6.1 */
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if (!(ap->base & ADIV5_AP_BASE_PRESENT) ||
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(ap->base == 0xffffffff)) {
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/* Debug Base Address not present in this MEM-AP */
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/* No debug entries... useless AP */
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adiv5_ap_unref(ap);
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continue;
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@ -106,6 +106,18 @@
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#define ADIV5_AP_CSW_SIZE_WORD (2u << 0)
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#define ADIV5_AP_CSW_SIZE_MASK (7u << 0)
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/* AP Debug Base Address Register (BASE) */
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#define ADIV5_AP_BASE_BASEADDR (0xFFFFF000u)
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#define ADIV5_AP_BASE_PRESENT (1u << 0)
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/* ADIv5 Class 0x1 ROM Table Registers */
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#define ADIV5_ROM_MEMTYPE 0xFCC
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#define ADIV5_ROM_MEMTYPE_SYSMEM (1u << 0)
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#define ADIV5_ROM_ROMENTRY_PRESENT (1u << 0)
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#define ADIV5_ROM_ROMENTRY_OFFSET (0xFFFFF000u)
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/* Constants to make RnW parameters more clear in code */
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#define ADIV5_LOW_WRITE 0
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#define ADIV5_LOW_READ 1
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@ -190,4 +202,3 @@ void adiv5_mem_write_sized(ADIv5_AP_t *ap, uint32_t dest, const void *src,
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size_t len, enum align align);
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#endif
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@ -129,7 +129,8 @@ enum stm32h7_regs
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#define OPTKEY2 0x4C5D6E7F
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#define DBGMCU_IDCODE 0x5c001000
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/* Access via 0xe00e1000 does not show device! */
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/* Access from processor address space.
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* Access via the APB-D is at 0xe00e1000 */
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#define DBGMCU_IDC (DBGMCU_IDCODE + 0)
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#define DBGMCU_CR (DBGMCU_IDCODE + 4)
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#define DBGSLEEP_D1 (1 << 0)
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