Consistently name target var 't' in cortexm.
This commit is contained in:
Gareth McMullin
parent
bda4279028
commit
64c79e1d03
279
src/cortexm.c
279
src/cortexm.c
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@ -60,23 +60,23 @@ const struct command_s cortexm_cmd_list[] = {
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#define SIGSEGV 11
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#define SIGLOST 29
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static int cortexm_regs_read(struct target_s *target, void *data);
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static int cortexm_regs_write(struct target_s *target, const void *data);
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static int cortexm_pc_write(struct target_s *target, const uint32_t val);
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static uint32_t cortexm_pc_read(struct target_s *target);
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static int cortexm_regs_read(target *t, void *data);
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static int cortexm_regs_write(target *t, const void *data);
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static int cortexm_pc_write(target *t, const uint32_t val);
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static uint32_t cortexm_pc_read(target *t);
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static void cortexm_reset(struct target_s *target);
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static int cortexm_halt_wait(struct target_s *target);
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static void cortexm_halt_request(struct target_s *target);
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static int cortexm_fault_unwind(struct target_s *target);
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static void cortexm_reset(target *t);
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static int cortexm_halt_wait(target *t);
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static void cortexm_halt_request(target *t);
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static int cortexm_fault_unwind(target *t);
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static int cortexm_set_hw_bp(struct target_s *target, uint32_t addr);
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static int cortexm_clear_hw_bp(struct target_s *target, uint32_t addr);
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static int cortexm_set_hw_bp(target *t, uint32_t addr);
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static int cortexm_clear_hw_bp(target *t, uint32_t addr);
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static int cortexm_set_hw_wp(struct target_s *target, uint8_t type, uint32_t addr, uint8_t len);
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static int cortexm_clear_hw_wp(struct target_s *target, uint8_t type, uint32_t addr, uint8_t len);
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static int cortexm_set_hw_wp(target *t, uint8_t type, uint32_t addr, uint8_t len);
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static int cortexm_clear_hw_wp(target *t, uint8_t type, uint32_t addr, uint8_t len);
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static int cortexm_check_hw_wp(struct target_s *target, uint32_t *addr);
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static int cortexm_check_hw_wp(target *t, uint32_t *addr);
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#define CORTEXM_MAX_WATCHPOINTS 4 /* architecture says up to 15, no implementation has > 4 */
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#define CORTEXM_MAX_BREAKPOINTS 6 /* architecture says up to 127, no implementation has > 6 */
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@ -207,42 +207,41 @@ static const char tdesc_cortex_mf[] =
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#define REG_PSP 18
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#define REG_SPECIAL 19
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bool
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cortexm_probe(struct target_s *target)
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bool cortexm_probe(target *t)
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{
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target->driver = cortexm_driver_str;
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t->driver = cortexm_driver_str;
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target->attach = cortexm_attach;
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target->detach = cortexm_detach;
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t->attach = cortexm_attach;
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t->detach = cortexm_detach;
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/* Should probe here to make sure it's Cortex-M3 */
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target->tdesc = tdesc_cortex_m;
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target->regs_read = cortexm_regs_read;
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target->regs_write = cortexm_regs_write;
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target->pc_write = cortexm_pc_write;
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target->pc_read = cortexm_pc_read;
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t->tdesc = tdesc_cortex_m;
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t->regs_read = cortexm_regs_read;
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t->regs_write = cortexm_regs_write;
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t->pc_write = cortexm_pc_write;
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t->pc_read = cortexm_pc_read;
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target->reset = cortexm_reset;
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target->halt_request = cortexm_halt_request;
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target->halt_wait = cortexm_halt_wait;
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target->halt_resume = cortexm_halt_resume;
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target->regs_size = sizeof(regnum_cortex_m);
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t->reset = cortexm_reset;
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t->halt_request = cortexm_halt_request;
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t->halt_wait = cortexm_halt_wait;
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t->halt_resume = cortexm_halt_resume;
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t->regs_size = sizeof(regnum_cortex_m);
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target->hostio_reply = cortexm_hostio_reply;
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t->hostio_reply = cortexm_hostio_reply;
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target_add_commands(target, cortexm_cmd_list, cortexm_driver_str);
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target_add_commands(t, cortexm_cmd_list, cortexm_driver_str);
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/* Probe for FP extension */
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uint32_t cpacr = target_mem_read32(target, CORTEXM_CPACR);
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uint32_t cpacr = target_mem_read32(t, CORTEXM_CPACR);
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cpacr |= 0x00F00000; /* CP10 = 0b11, CP11 = 0b11 */
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target_mem_write32(target, CORTEXM_CPACR, cpacr);
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if (target_mem_read32(target, CORTEXM_CPACR) == cpacr) {
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target->target_options |= TOPT_FLAVOUR_V7MF;
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target->regs_size += sizeof(regnum_cortex_mf);
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target->tdesc = tdesc_cortex_mf;
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target_mem_write32(t, CORTEXM_CPACR, cpacr);
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if (target_mem_read32(t, CORTEXM_CPACR) == cpacr) {
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t->target_options |= TOPT_FLAVOUR_V7MF;
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t->regs_size += sizeof(regnum_cortex_mf);
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t->tdesc = tdesc_cortex_mf;
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}
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ADIv5_AP_t *ap = adiv5_target_ap(target);
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ADIv5_AP_t *ap = adiv5_target_ap(t);
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struct cortexm_priv *priv = calloc(1, sizeof(*priv));
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ap->priv = priv;
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ap->priv_free = free;
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@ -252,7 +251,7 @@ cortexm_probe(struct target_s *target)
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CORTEXM_DEMCR_VC_CORERESET;
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#define PROBE(x) \
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do { if ((x)(target)) return true; else target_check_error(target); } while (0)
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do { if ((x)(t)) return true; else target_check_error(t); } while (0)
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PROBE(stm32f1_probe);
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PROBE(stm32f4_probe);
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@ -270,62 +269,62 @@ cortexm_probe(struct target_s *target)
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return true;
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}
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bool cortexm_attach(struct target_s *target)
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bool cortexm_attach(target *t)
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{
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ADIv5_AP_t *ap = adiv5_target_ap(target);
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ADIv5_AP_t *ap = adiv5_target_ap(t);
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struct cortexm_priv *priv = ap->priv;
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unsigned i;
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uint32_t r;
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int tries;
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/* Clear any pending fault condition */
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target_check_error(target);
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target_check_error(t);
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target_halt_request(target);
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target_halt_request(t);
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tries = 10;
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while(!connect_assert_srst && !target_halt_wait(target) && --tries)
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while(!connect_assert_srst && !target_halt_wait(t) && --tries)
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platform_delay(2);
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if(!tries)
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return false;
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/* Request halt on reset */
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target_mem_write32(target, CORTEXM_DEMCR, priv->demcr);
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target_mem_write32(t, CORTEXM_DEMCR, priv->demcr);
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/* Reset DFSR flags */
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target_mem_write32(target, CORTEXM_DFSR, CORTEXM_DFSR_RESETALL);
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target_mem_write32(t, CORTEXM_DFSR, CORTEXM_DFSR_RESETALL);
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/* size the break/watchpoint units */
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priv->hw_breakpoint_max = CORTEXM_MAX_BREAKPOINTS;
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r = target_mem_read32(target, CORTEXM_FPB_CTRL);
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r = target_mem_read32(t, CORTEXM_FPB_CTRL);
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if (((r >> 4) & 0xf) < priv->hw_breakpoint_max) /* only look at NUM_COMP1 */
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priv->hw_breakpoint_max = (r >> 4) & 0xf;
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priv->hw_watchpoint_max = CORTEXM_MAX_WATCHPOINTS;
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r = target_mem_read32(target, CORTEXM_DWT_CTRL);
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r = target_mem_read32(t, CORTEXM_DWT_CTRL);
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if ((r >> 28) > priv->hw_watchpoint_max)
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priv->hw_watchpoint_max = r >> 28;
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/* Clear any stale breakpoints */
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for(i = 0; i < priv->hw_breakpoint_max; i++) {
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target_mem_write32(target, CORTEXM_FPB_COMP(i), 0);
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target_mem_write32(t, CORTEXM_FPB_COMP(i), 0);
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priv->hw_breakpoint[i] = 0;
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}
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/* Clear any stale watchpoints */
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for(i = 0; i < priv->hw_watchpoint_max; i++) {
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target_mem_write32(target, CORTEXM_DWT_FUNC(i), 0);
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target_mem_write32(t, CORTEXM_DWT_FUNC(i), 0);
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priv->hw_watchpoint[i].type = 0;
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}
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/* Flash Patch Control Register: set ENABLE */
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target_mem_write32(target, CORTEXM_FPB_CTRL,
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target_mem_write32(t, CORTEXM_FPB_CTRL,
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CORTEXM_FPB_CTRL_KEY | CORTEXM_FPB_CTRL_ENABLE);
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target->set_hw_bp = cortexm_set_hw_bp;
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target->clear_hw_bp = cortexm_clear_hw_bp;
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t->set_hw_bp = cortexm_set_hw_bp;
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t->clear_hw_bp = cortexm_clear_hw_bp;
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/* Data Watchpoint and Trace */
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target->set_hw_wp = cortexm_set_hw_wp;
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target->clear_hw_wp = cortexm_clear_hw_wp;
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target->check_hw_wp = cortexm_check_hw_wp;
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t->set_hw_wp = cortexm_set_hw_wp;
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t->clear_hw_wp = cortexm_clear_hw_wp;
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t->check_hw_wp = cortexm_check_hw_wp;
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if(connect_assert_srst)
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jtagtap_srst(false);
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@ -333,28 +332,27 @@ bool cortexm_attach(struct target_s *target)
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return true;
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}
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void cortexm_detach(struct target_s *target)
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void cortexm_detach(target *t)
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{
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ADIv5_AP_t *ap = adiv5_target_ap(target);
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ADIv5_AP_t *ap = adiv5_target_ap(t);
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struct cortexm_priv *priv = ap->priv;
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unsigned i;
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/* Clear any stale breakpoints */
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for(i = 0; i < priv->hw_breakpoint_max; i++)
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target_mem_write32(target, CORTEXM_FPB_COMP(i), 0);
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target_mem_write32(t, CORTEXM_FPB_COMP(i), 0);
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/* Clear any stale watchpoints */
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for(i = 0; i < priv->hw_watchpoint_max; i++)
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target_mem_write32(target, CORTEXM_DWT_FUNC(i), 0);
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target_mem_write32(t, CORTEXM_DWT_FUNC(i), 0);
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/* Disable debug */
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target_mem_write32(target, CORTEXM_DHCSR, CORTEXM_DHCSR_DBGKEY);
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target_mem_write32(t, CORTEXM_DHCSR, CORTEXM_DHCSR_DBGKEY);
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}
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static int
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cortexm_regs_read(struct target_s *target, void *data)
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static int cortexm_regs_read(target *t, void *data)
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{
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ADIv5_AP_t *ap = adiv5_target_ap(target);
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ADIv5_AP_t *ap = adiv5_target_ap(t);
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uint32_t *regs = data;
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unsigned i;
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@ -375,7 +373,7 @@ cortexm_regs_read(struct target_s *target, void *data)
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regnum_cortex_m[i]);
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*regs++ = adiv5_dp_read(ap->dp, ADIV5_AP_DB(2));
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}
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if (target->target_options & TOPT_FLAVOUR_V7MF)
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if (t->target_options & TOPT_FLAVOUR_V7MF)
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for(i = 0; i < sizeof(regnum_cortex_mf) / 4; i++) {
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adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE,
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ADIV5_AP_DB(1),
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@ -386,10 +384,9 @@ cortexm_regs_read(struct target_s *target, void *data)
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return 0;
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}
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static int
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cortexm_regs_write(struct target_s *target, const void *data)
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static int cortexm_regs_write(target *t, const void *data)
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{
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ADIv5_AP_t *ap = adiv5_target_ap(target);
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ADIv5_AP_t *ap = adiv5_target_ap(t);
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const uint32_t *regs = data;
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unsigned i;
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@ -412,7 +409,7 @@ cortexm_regs_write(struct target_s *target, const void *data)
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adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, ADIV5_AP_DB(1),
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0x10000 | regnum_cortex_m[i]);
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}
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if (target->target_options & TOPT_FLAVOUR_V7MF)
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if (t->target_options & TOPT_FLAVOUR_V7MF)
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for(i = 0; i < sizeof(regnum_cortex_mf) / 4; i++) {
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adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE,
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ADIV5_AP_DB(2), *regs++);
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@ -424,55 +421,51 @@ cortexm_regs_write(struct target_s *target, const void *data)
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return 0;
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}
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static uint32_t
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cortexm_pc_read(struct target_s *target)
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static uint32_t cortexm_pc_read(target *t)
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{
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target_mem_write32(target, CORTEXM_DCRSR, 0x0F);
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return target_mem_read32(target, CORTEXM_DCRDR);
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target_mem_write32(t, CORTEXM_DCRSR, 0x0F);
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return target_mem_read32(t, CORTEXM_DCRDR);
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return 0;
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}
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static int
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cortexm_pc_write(struct target_s *target, const uint32_t val)
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static int cortexm_pc_write(target *t, const uint32_t val)
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{
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target_mem_write32(target, CORTEXM_DCRDR, val);
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target_mem_write32(target, CORTEXM_DCRSR, CORTEXM_DCRSR_REGWnR | 0x0F);
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target_mem_write32(t, CORTEXM_DCRDR, val);
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target_mem_write32(t, CORTEXM_DCRSR, CORTEXM_DCRSR_REGWnR | 0x0F);
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return 0;
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}
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/* The following three routines implement target halt/resume
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* using the core debug registers in the NVIC. */
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static void
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cortexm_reset(struct target_s *target)
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static void cortexm_reset(target *t)
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{
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jtagtap_srst(true);
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jtagtap_srst(false);
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/* Read DHCSR here to clear S_RESET_ST bit before reset */
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target_mem_read32(target, CORTEXM_DHCSR);
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target_mem_read32(t, CORTEXM_DHCSR);
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/* Request system reset from NVIC: SRST doesn't work correctly */
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/* This could be VECTRESET: 0x05FA0001 (reset only core)
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* or SYSRESETREQ: 0x05FA0004 (system reset)
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*/
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target_mem_write32(target, CORTEXM_AIRCR,
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target_mem_write32(t, CORTEXM_AIRCR,
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CORTEXM_AIRCR_VECTKEY | CORTEXM_AIRCR_SYSRESETREQ);
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/* Poll for release from reset */
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while (target_mem_read32(target, CORTEXM_DHCSR) & CORTEXM_DHCSR_S_RESET_ST);
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while (target_mem_read32(t, CORTEXM_DHCSR) & CORTEXM_DHCSR_S_RESET_ST);
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/* Reset DFSR flags */
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target_mem_write32(target, CORTEXM_DFSR, CORTEXM_DFSR_RESETALL);
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target_mem_write32(t, CORTEXM_DFSR, CORTEXM_DFSR_RESETALL);
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}
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static void
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cortexm_halt_request(struct target_s *target)
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static void cortexm_halt_request(target *t)
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{
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volatile struct exception e;
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TRY_CATCH (e, EXCEPTION_TIMEOUT) {
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target_mem_write32(target, CORTEXM_DHCSR, CORTEXM_DHCSR_DBGKEY |
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target_mem_write32(t, CORTEXM_DHCSR, CORTEXM_DHCSR_DBGKEY |
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CORTEXM_DHCSR_C_HALT |
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CORTEXM_DHCSR_C_DEBUGEN);
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}
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@ -481,10 +474,9 @@ cortexm_halt_request(struct target_s *target)
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}
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}
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static int
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cortexm_halt_wait(struct target_s *target)
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static int cortexm_halt_wait(target *t)
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{
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ADIv5_AP_t *ap = adiv5_target_ap(target);
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ADIv5_AP_t *ap = adiv5_target_ap(t);
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struct cortexm_priv *priv = ap->priv;
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uint32_t dhcsr = 0;
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@ -492,7 +484,7 @@ cortexm_halt_wait(struct target_s *target)
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TRY_CATCH (e, EXCEPTION_ALL) {
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/* If this times out because the target is in WFI then
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* the target is still running. */
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dhcsr = target_mem_read32(target, CORTEXM_DHCSR);
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dhcsr = target_mem_read32(t, CORTEXM_DHCSR);
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}
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switch (e.type) {
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case EXCEPTION_ERROR:
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@ -509,10 +501,10 @@ cortexm_halt_wait(struct target_s *target)
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return 0;
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/* We've halted. Let's find out why. */
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uint32_t dfsr = target_mem_read32(target, CORTEXM_DFSR);
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target_mem_write32(target, CORTEXM_DFSR, dfsr); /* write back to reset */
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uint32_t dfsr = target_mem_read32(t, CORTEXM_DFSR);
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target_mem_write32(t, CORTEXM_DFSR, dfsr); /* write back to reset */
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if ((dfsr & CORTEXM_DFSR_VCATCH) && cortexm_fault_unwind(target))
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if ((dfsr & CORTEXM_DFSR_VCATCH) && cortexm_fault_unwind(t))
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return SIGSEGV;
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/* Remember if we stopped on a breakpoint */
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@ -520,13 +512,13 @@ cortexm_halt_wait(struct target_s *target)
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if (priv->on_bkpt) {
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/* If we've hit a programmed breakpoint, check for semihosting
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* call. */
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uint32_t pc = cortexm_pc_read(target);
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uint32_t pc = cortexm_pc_read(t);
|
||||
uint16_t bkpt_instr;
|
||||
bkpt_instr = target_mem_read16(target, pc);
|
||||
bkpt_instr = target_mem_read16(t, pc);
|
||||
if (bkpt_instr == 0xBEAB) {
|
||||
int n = cortexm_hostio_request(target);
|
||||
int n = cortexm_hostio_request(t);
|
||||
if (n > 0) {
|
||||
target_halt_resume(target, priv->stepping);
|
||||
target_halt_resume(t, priv->stepping);
|
||||
return 0;
|
||||
} else if (n < 0) {
|
||||
return -1;
|
||||
|
|
@ -544,9 +536,9 @@ cortexm_halt_wait(struct target_s *target)
|
|||
|
||||
}
|
||||
|
||||
void cortexm_halt_resume(struct target_s *target, bool step)
|
||||
void cortexm_halt_resume(target *t, bool step)
|
||||
{
|
||||
ADIv5_AP_t *ap = adiv5_target_ap(target);
|
||||
ADIv5_AP_t *ap = adiv5_target_ap(t);
|
||||
struct cortexm_priv *priv = ap->priv;
|
||||
uint32_t dhcsr = CORTEXM_DHCSR_DBGKEY | CORTEXM_DHCSR_C_DEBUGEN;
|
||||
|
||||
|
|
@ -555,42 +547,42 @@ void cortexm_halt_resume(struct target_s *target, bool step)
|
|||
|
||||
/* Disable interrupts while single stepping... */
|
||||
if(step != priv->stepping) {
|
||||
target_mem_write32(target, CORTEXM_DHCSR, dhcsr | CORTEXM_DHCSR_C_HALT);
|
||||
target_mem_write32(t, CORTEXM_DHCSR, dhcsr | CORTEXM_DHCSR_C_HALT);
|
||||
priv->stepping = step;
|
||||
}
|
||||
|
||||
if (priv->on_bkpt) {
|
||||
uint32_t pc = cortexm_pc_read(target);
|
||||
if ((target_mem_read16(target, pc) & 0xFF00) == 0xBE00)
|
||||
cortexm_pc_write(target, pc + 2);
|
||||
uint32_t pc = cortexm_pc_read(t);
|
||||
if ((target_mem_read16(t, pc) & 0xFF00) == 0xBE00)
|
||||
cortexm_pc_write(t, pc + 2);
|
||||
}
|
||||
|
||||
target_mem_write32(target, CORTEXM_DHCSR, dhcsr);
|
||||
target_mem_write32(t, CORTEXM_DHCSR, dhcsr);
|
||||
}
|
||||
|
||||
static int cortexm_fault_unwind(struct target_s *target)
|
||||
static int cortexm_fault_unwind(target *t)
|
||||
{
|
||||
uint32_t hfsr = target_mem_read32(target, CORTEXM_HFSR);
|
||||
uint32_t cfsr = target_mem_read32(target, CORTEXM_CFSR);
|
||||
target_mem_write32(target, CORTEXM_HFSR, hfsr);/* write back to reset */
|
||||
target_mem_write32(target, CORTEXM_CFSR, cfsr);/* write back to reset */
|
||||
uint32_t hfsr = target_mem_read32(t, CORTEXM_HFSR);
|
||||
uint32_t cfsr = target_mem_read32(t, CORTEXM_CFSR);
|
||||
target_mem_write32(t, CORTEXM_HFSR, hfsr);/* write back to reset */
|
||||
target_mem_write32(t, CORTEXM_CFSR, cfsr);/* write back to reset */
|
||||
/* We check for FORCED in the HardFault Status Register or
|
||||
* for a configurable fault to avoid catching core resets */
|
||||
if((hfsr & CORTEXM_HFSR_FORCED) || cfsr) {
|
||||
/* Unwind exception */
|
||||
uint32_t regs[target->regs_size / 4];
|
||||
uint32_t regs[t->regs_size / 4];
|
||||
uint32_t stack[8];
|
||||
uint32_t retcode, framesize;
|
||||
/* Read registers for post-exception stack pointer */
|
||||
target_regs_read(target, regs);
|
||||
target_regs_read(t, regs);
|
||||
/* save retcode currently in lr */
|
||||
retcode = regs[REG_LR];
|
||||
bool spsel = retcode & (1<<2);
|
||||
bool fpca = !(retcode & (1<<4));
|
||||
/* Read stack for pre-exception registers */
|
||||
uint32_t sp = spsel ? regs[REG_PSP] : regs[REG_MSP];
|
||||
target_mem_read(target, stack, sp, sizeof(stack));
|
||||
if (target_check_error(target))
|
||||
target_mem_read(t, stack, sp, sizeof(stack));
|
||||
if (target_check_error(t))
|
||||
return 0;
|
||||
regs[REG_LR] = stack[5]; /* restore LR to pre-exception state */
|
||||
regs[REG_PC] = stack[6]; /* restore PC to pre-exception state */
|
||||
|
|
@ -616,22 +608,22 @@ static int cortexm_fault_unwind(struct target_s *target)
|
|||
/* Reset exception state to allow resuming from restored
|
||||
* state.
|
||||
*/
|
||||
target_mem_write32(target, CORTEXM_AIRCR,
|
||||
target_mem_write32(t, CORTEXM_AIRCR,
|
||||
CORTEXM_AIRCR_VECTKEY | CORTEXM_AIRCR_VECTCLRACTIVE);
|
||||
|
||||
/* Write pre-exception registers back to core */
|
||||
target_regs_write(target, regs);
|
||||
target_regs_write(t, regs);
|
||||
|
||||
return 1;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
int cortexm_run_stub(struct target_s *target, uint32_t loadaddr,
|
||||
int cortexm_run_stub(target *t, uint32_t loadaddr,
|
||||
const uint16_t *stub, uint32_t stublen,
|
||||
uint32_t r0, uint32_t r1, uint32_t r2, uint32_t r3)
|
||||
{
|
||||
uint32_t regs[target->regs_size / 4];
|
||||
uint32_t regs[t->regs_size / 4];
|
||||
|
||||
memset(regs, 0, sizeof(regs));
|
||||
regs[0] = r0;
|
||||
|
|
@ -642,19 +634,19 @@ int cortexm_run_stub(struct target_s *target, uint32_t loadaddr,
|
|||
regs[16] = 0x1000000;
|
||||
regs[19] = 0;
|
||||
|
||||
target_mem_write(target, loadaddr, stub, stublen);
|
||||
cortexm_regs_write(target, regs);
|
||||
target_mem_write(t, loadaddr, stub, stublen);
|
||||
cortexm_regs_write(t, regs);
|
||||
|
||||
if (target_check_error(target))
|
||||
if (target_check_error(t))
|
||||
return -1;
|
||||
|
||||
/* Execute the stub */
|
||||
cortexm_halt_resume(target, 0);
|
||||
while (!cortexm_halt_wait(target))
|
||||
cortexm_halt_resume(t, 0);
|
||||
while (!cortexm_halt_wait(t))
|
||||
;
|
||||
|
||||
uint32_t pc = cortexm_pc_read(target);
|
||||
uint16_t bkpt_instr = target_mem_read16(target, pc);
|
||||
uint32_t pc = cortexm_pc_read(t);
|
||||
uint16_t bkpt_instr = target_mem_read16(t, pc);
|
||||
if (bkpt_instr >> 8 != 0xbe)
|
||||
return -2;
|
||||
|
||||
|
|
@ -664,10 +656,9 @@ int cortexm_run_stub(struct target_s *target, uint32_t loadaddr,
|
|||
/* The following routines implement hardware breakpoints.
|
||||
* The Flash Patch and Breakpoint (FPB) system is used. */
|
||||
|
||||
static int
|
||||
cortexm_set_hw_bp(struct target_s *target, uint32_t addr)
|
||||
static int cortexm_set_hw_bp(target *t, uint32_t addr)
|
||||
{
|
||||
ADIv5_AP_t *ap = adiv5_target_ap(target);
|
||||
ADIv5_AP_t *ap = adiv5_target_ap(t);
|
||||
struct cortexm_priv *priv = ap->priv;
|
||||
uint32_t val = addr & 0x1FFFFFFC;
|
||||
unsigned i;
|
||||
|
|
@ -682,15 +673,14 @@ cortexm_set_hw_bp(struct target_s *target, uint32_t addr)
|
|||
|
||||
priv->hw_breakpoint[i] = addr | 1;
|
||||
|
||||
target_mem_write32(target, CORTEXM_FPB_COMP(i), val);
|
||||
target_mem_write32(t, CORTEXM_FPB_COMP(i), val);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
cortexm_clear_hw_bp(struct target_s *target, uint32_t addr)
|
||||
static int cortexm_clear_hw_bp(target *t, uint32_t addr)
|
||||
{
|
||||
ADIv5_AP_t *ap = adiv5_target_ap(target);
|
||||
ADIv5_AP_t *ap = adiv5_target_ap(t);
|
||||
struct cortexm_priv *priv = ap->priv;
|
||||
unsigned i;
|
||||
|
||||
|
|
@ -701,7 +691,7 @@ cortexm_clear_hw_bp(struct target_s *target, uint32_t addr)
|
|||
|
||||
priv->hw_breakpoint[i] = 0;
|
||||
|
||||
target_mem_write32(target, CORTEXM_FPB_COMP(i), 0);
|
||||
target_mem_write32(t, CORTEXM_FPB_COMP(i), 0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -710,9 +700,9 @@ cortexm_clear_hw_bp(struct target_s *target, uint32_t addr)
|
|||
* The Data Watch and Trace (DWT) system is used. */
|
||||
|
||||
static int
|
||||
cortexm_set_hw_wp(struct target_s *target, uint8_t type, uint32_t addr, uint8_t len)
|
||||
cortexm_set_hw_wp(target *t, uint8_t type, uint32_t addr, uint8_t len)
|
||||
{
|
||||
ADIv5_AP_t *ap = adiv5_target_ap(target);
|
||||
ADIv5_AP_t *ap = adiv5_target_ap(t);
|
||||
struct cortexm_priv *priv = ap->priv;
|
||||
unsigned i;
|
||||
|
||||
|
|
@ -734,7 +724,7 @@ cortexm_set_hw_wp(struct target_s *target, uint8_t type, uint32_t addr, uint8_t
|
|||
|
||||
for(i = 0; i < priv->hw_watchpoint_max; i++)
|
||||
if((priv->hw_watchpoint[i].type == 0) &&
|
||||
((target_mem_read32(target, CORTEXM_DWT_FUNC(i)) & 0xF) == 0))
|
||||
((target_mem_read32(t, CORTEXM_DWT_FUNC(i)) & 0xF) == 0))
|
||||
break;
|
||||
|
||||
if(i == priv->hw_watchpoint_max) return -2;
|
||||
|
|
@ -743,18 +733,18 @@ cortexm_set_hw_wp(struct target_s *target, uint8_t type, uint32_t addr, uint8_t
|
|||
priv->hw_watchpoint[i].addr = addr;
|
||||
priv->hw_watchpoint[i].size = len;
|
||||
|
||||
target_mem_write32(target, CORTEXM_DWT_COMP(i), addr);
|
||||
target_mem_write32(target, CORTEXM_DWT_MASK(i), len);
|
||||
target_mem_write32(target, CORTEXM_DWT_FUNC(i), type |
|
||||
((target->target_options & TOPT_FLAVOUR_V6M) ? 0: CORTEXM_DWT_FUNC_DATAVSIZE_WORD));
|
||||
target_mem_write32(t, CORTEXM_DWT_COMP(i), addr);
|
||||
target_mem_write32(t, CORTEXM_DWT_MASK(i), len);
|
||||
target_mem_write32(t, CORTEXM_DWT_FUNC(i), type |
|
||||
((t->target_options & TOPT_FLAVOUR_V6M) ? 0: CORTEXM_DWT_FUNC_DATAVSIZE_WORD));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
cortexm_clear_hw_wp(struct target_s *target, uint8_t type, uint32_t addr, uint8_t len)
|
||||
cortexm_clear_hw_wp(target *t, uint8_t type, uint32_t addr, uint8_t len)
|
||||
{
|
||||
ADIv5_AP_t *ap = adiv5_target_ap(target);
|
||||
ADIv5_AP_t *ap = adiv5_target_ap(t);
|
||||
struct cortexm_priv *priv = ap->priv;
|
||||
unsigned i;
|
||||
|
||||
|
|
@ -783,22 +773,21 @@ cortexm_clear_hw_wp(struct target_s *target, uint8_t type, uint32_t addr, uint8_
|
|||
|
||||
priv->hw_watchpoint[i].type = 0;
|
||||
|
||||
target_mem_write32(target, CORTEXM_DWT_FUNC(i), 0);
|
||||
target_mem_write32(t, CORTEXM_DWT_FUNC(i), 0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
cortexm_check_hw_wp(struct target_s *target, uint32_t *addr)
|
||||
static int cortexm_check_hw_wp(target *t, uint32_t *addr)
|
||||
{
|
||||
ADIv5_AP_t *ap = adiv5_target_ap(target);
|
||||
ADIv5_AP_t *ap = adiv5_target_ap(t);
|
||||
struct cortexm_priv *priv = ap->priv;
|
||||
unsigned i;
|
||||
|
||||
for(i = 0; i < priv->hw_watchpoint_max; i++)
|
||||
/* if SET and MATCHED then break */
|
||||
if(priv->hw_watchpoint[i].type &&
|
||||
(target_mem_read32(target, CORTEXM_DWT_FUNC(i)) &
|
||||
(target_mem_read32(t, CORTEXM_DWT_FUNC(i)) &
|
||||
CORTEXM_DWT_FUNC_MATCHED))
|
||||
break;
|
||||
|
||||
|
|
|
|||
|
|
@ -116,39 +116,39 @@ struct target_s {
|
|||
target_destroy_callback destroy_callback;
|
||||
|
||||
/* Attach/Detach funcitons */
|
||||
bool (*attach)(struct target_s *target);
|
||||
void (*detach)(struct target_s *target);
|
||||
int (*check_error)(struct target_s *target);
|
||||
bool (*attach)(target *t);
|
||||
void (*detach)(target *t);
|
||||
int (*check_error)(target *t);
|
||||
|
||||
/* Memory access functions */
|
||||
void (*mem_read)(struct target_s *target, void *dest, uint32_t src,
|
||||
void (*mem_read)(target *t, void *dest, uint32_t src,
|
||||
size_t len);
|
||||
void (*mem_write)(struct target_s *target, uint32_t dest,
|
||||
void (*mem_write)(target *t, uint32_t dest,
|
||||
const void *src, size_t len);
|
||||
|
||||
/* Register access functions */
|
||||
int regs_size;
|
||||
const char *tdesc;
|
||||
int (*regs_read)(struct target_s *target, void *data);
|
||||
int (*regs_write)(struct target_s *target, const void *data);
|
||||
int (*regs_read)(target *t, void *data);
|
||||
int (*regs_write)(target *t, const void *data);
|
||||
|
||||
uint32_t (*pc_read)(struct target_s *target);
|
||||
int (*pc_write)(struct target_s *target, const uint32_t val);
|
||||
uint32_t (*pc_read)(target *t);
|
||||
int (*pc_write)(target *t, const uint32_t val);
|
||||
|
||||
/* Halt/resume functions */
|
||||
void (*reset)(struct target_s *target);
|
||||
void (*halt_request)(struct target_s *target);
|
||||
int (*halt_wait)(struct target_s *target);
|
||||
void (*halt_resume)(struct target_s *target, bool step);
|
||||
void (*reset)(target *t);
|
||||
void (*halt_request)(target *t);
|
||||
int (*halt_wait)(target *t);
|
||||
void (*halt_resume)(target *t, bool step);
|
||||
|
||||
/* Break-/watchpoint functions */
|
||||
int (*set_hw_bp)(struct target_s *target, uint32_t addr);
|
||||
int (*clear_hw_bp)(struct target_s *target, uint32_t addr);
|
||||
int (*set_hw_bp)(target *t, uint32_t addr);
|
||||
int (*clear_hw_bp)(target *t, uint32_t addr);
|
||||
|
||||
int (*set_hw_wp)(struct target_s *target, uint8_t type, uint32_t addr, uint8_t len);
|
||||
int (*clear_hw_wp)(struct target_s *target, uint8_t type, uint32_t addr, uint8_t len);
|
||||
int (*set_hw_wp)(target *t, uint8_t type, uint32_t addr, uint8_t len);
|
||||
int (*clear_hw_wp)(target *t, uint8_t type, uint32_t addr, uint8_t len);
|
||||
|
||||
int (*check_hw_wp)(struct target_s *target, uint32_t *addr);
|
||||
int (*check_hw_wp)(target *t, uint32_t *addr);
|
||||
|
||||
/* target-defined options */
|
||||
unsigned target_options;
|
||||
|
|
@ -156,8 +156,8 @@ struct target_s {
|
|||
|
||||
/* Flash memory access functions */
|
||||
const char *xml_mem_map;
|
||||
int (*flash_erase)(struct target_s *target, uint32_t addr, size_t len);
|
||||
int (*flash_write)(struct target_s *target, uint32_t dest,
|
||||
int (*flash_erase)(target *t, uint32_t addr, size_t len);
|
||||
int (*flash_write)(target *t, uint32_t dest,
|
||||
const uint8_t *src, size_t len);
|
||||
|
||||
/* Host I/O support */
|
||||
|
|
@ -226,18 +226,18 @@ static inline void target_mem_write8(target *t, uint32_t addr, uint8_t value)
|
|||
/* Probe for various targets.
|
||||
* Actual functions implemented in their respective drivers.
|
||||
*/
|
||||
bool cortexm_probe(struct target_s *target);
|
||||
bool stm32f1_probe(struct target_s *target);
|
||||
bool stm32f4_probe(struct target_s *target);
|
||||
bool stm32l0_probe(struct target_s *target);
|
||||
bool stm32l1_probe(struct target_s *target);
|
||||
bool lmi_probe(struct target_s *target);
|
||||
bool lpc11xx_probe(struct target_s *target);
|
||||
bool lpc43xx_probe(struct target_s *target);
|
||||
bool sam3x_probe(struct target_s *target);
|
||||
bool nrf51_probe(struct target_s *target);
|
||||
bool samd_probe(struct target_s *target);
|
||||
bool kinetis_probe(struct target_s *target);
|
||||
bool cortexm_probe(target *t);
|
||||
bool stm32f1_probe(target *t);
|
||||
bool stm32f4_probe(target *t);
|
||||
bool stm32l0_probe(target *t);
|
||||
bool stm32l1_probe(target *t);
|
||||
bool lmi_probe(target *t);
|
||||
bool lpc11xx_probe(target *t);
|
||||
bool lpc43xx_probe(target *t);
|
||||
bool sam3x_probe(target *t);
|
||||
bool nrf51_probe(target *t);
|
||||
bool samd_probe(target *t);
|
||||
bool kinetis_probe(target *t);
|
||||
|
||||
#endif
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue