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stm32h7/f7: Write DBGMCU_CR only on attach. 

Split probe/attach for STM32H7.
This commit is contained in:
Uwe Bonnes 2018-09-10 22:06:17 +02:00 committed by Gareth McMullin
parent 8575d3e7a6
commit 6633f74d95
2 changed files with 18 additions and 11 deletions
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3
src/target/stm32f4.c
View File

@ -204,8 +204,6 @@ bool stm32f4_probe(target *t)
case ID_STM32F74X: /* F74x RM0385 Rev.4 */
case ID_STM32F76X: /* F76x F77x RM0410 */
case ID_STM32F72X: /* F72x F73x RM0431 */
target_mem_write32(t, DBGMCU_CR, DBG_SLEEP);
/* fallthrough */
case ID_STM32F40X:
case ID_STM32F42X: /* 427/437 */
case ID_STM32F46X: /* 469/479 */
@ -285,6 +283,7 @@ static bool stm32f4_attach(target *t)
target_mem_map_free(t);
uint32_t flashsize = target_mem_read32(t, flashsize_base) & 0xffff;
if (is_f7) {
target_mem_write32(t, DBGMCU_CR, DBG_SLEEP);
target_add_ram(t, 0x00000000, 0x4000); /* 16 k ITCM Ram */
target_add_ram(t, 0x20000000, 0x20000); /* 128 k DTCM Ram */
target_add_ram(t, 0x20020000, 0x60000); /* 384 k Ram */

26
src/target/stm32h7.c
View File

@ -172,16 +172,30 @@ static void stm32h7_add_flash(target *t,
target_add_flash(t, f);
}
static bool stm32h7_attach(target *t)
{
if (!cortexm_attach(t))
return false;
/* RM0433 Rev 4 is not really clear, what bits are needed.
* Set all possible relevant bits for now. */
target_mem_write32(t, DBGMCU_CR, DBGSLEEP_D1 | D1DBGCKEN);
/* If IWDG runs as HARDWARE watchdog (44.3.4) erase
* will be aborted by the Watchdog and erase fails!
* Setting IWDG_KR to 0xaaaa does not seem to help!*/
uint32_t optsr = target_mem_read32(t, FPEC1_BASE + FLASH_OPTSR);
if (!(optsr & FLASH_OPTSR_IWDG1_SW))
tc_printf(t, "Hardware IWDG running. Expect failure. Set IWDG1_SW!");
return true;
}
bool stm32h7_probe(target *t)
{
ADIv5_AP_t *ap = cortexm_ap(t);
uint32_t idcode = (ap->dp->targetid >> 16) & 0xfff;
if (idcode == ID_STM32H74x) {
/* RM0433 Rev 4 is not really clear, what bits are needed.
* Set all possible relevant bits for now. */
target_mem_write32(t, DBGMCU_CR, DBGSLEEP_D1 | D1DBGCKEN);
t->idcode = idcode;
t->driver = stm32h74_driver_str;
t->attach = stm32h7_attach;
target_add_commands(t, stm32h7_cmd_list, stm32h74_driver_str);
target_add_ram(t, 0x00000000, 0x10000); /* ITCM Ram, 64 k */
target_add_ram(t, 0x20000000, 0x20000); /* DTCM Ram, 128 k */
@ -192,12 +206,6 @@ bool stm32h7_probe(target *t)
target_add_ram(t, 0x38000000, 0x01000); /* AHB SRAM4, 32 k */
stm32h7_add_flash(t, 0x8000000, 0x100000, FLASH_SECTOR_SIZE);
stm32h7_add_flash(t, 0x8100000, 0x100000, FLASH_SECTOR_SIZE);
/* If IWDG runs as HARDWARE watchdog (44.3.4) erase
* will be aborted by the Watchdog and erase fails!
* Setting IWDG_KR to 0xaaaa does not seem to help!*/
uint32_t optsr = target_mem_read32(t, FPEC1_BASE + FLASH_OPTSR);
if (!(optsr & FLASH_OPTSR_IWDG1_SW))
tc_printf(t, "Hardware IWDG running. Expect failure. Set IWDG1_SW!");
return true;
}
return false;