Correction of #445 attach-detach problem
Memory map is now completely freed and rebuilt in the separate attach function. It was previoulsy split beween probe and attach and never released, causing problems when reattaching to the same target.
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newbrain
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da62cbaa3d
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6887628eaa
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@ -124,6 +124,108 @@ struct stm32l4_flash {
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uint32_t bank1_start;
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};
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enum ID_STM32L4 {
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ID_STM32L41 = 0x464u, /* RM0394, Rev.4 */
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ID_STM32L43 = 0x435u, /* RM0394, Rev.4 */
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ID_STM32L45 = 0x462u, /* RM0394, Rev.4 */
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ID_STM32L47 = 0x415u, /* RM0351, Rev.5 */
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ID_STM32L49 = 0x461u, /* RM0351, Rev.5 */
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ID_STM32L4R = 0x470u, /* RM0432, Rev.5 */
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ID_STM32G07 = 0x460u, /* RM0444/454, Rev.1 */
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};
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enum FAM_STM32L4 {
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FAM_STM32L4xx = 1,
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FAM_STM32L4Rx = 2,
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FAM_STM32G0x = 3,
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FAM_STM32WBxx = 4,
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};
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#define DUAL_BANK 0x80u
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#define RAM_COUNT_MSK 0x07u
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struct stm32l4_info {
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char designator[10];
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uint16_t sram1;
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uint16_t sram2;
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uint16_t sram3;
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enum ID_STM32L4 idcode;
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enum FAM_STM32L4 family;
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uint8_t flags;
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};
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struct stm32l4_info const L4info[] = {
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{
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.idcode = ID_STM32L41,
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.family = FAM_STM32L4xx,
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.designator = "STM32L41x",
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.sram1 = 32,
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.sram2 = 8,
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.flags = 2,
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},
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{
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.idcode = ID_STM32L43,
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.family = FAM_STM32L4xx,
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.designator = "STM32L43x",
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.sram1 = 48,
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.sram2 = 16,
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.flags = 2,
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},
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{
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.idcode = ID_STM32L45,
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.family = FAM_STM32L4xx,
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.designator = "STM32L45x",
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.sram1 = 128,
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.sram2 = 32,
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.flags = 2,
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},
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{
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.idcode = ID_STM32L47,
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.family = FAM_STM32L4xx,
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.designator = "STM32L47x",
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.sram1 = 96,
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.sram2 = 32,
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.flags = 2 | DUAL_BANK,
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},
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{
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.idcode = ID_STM32L49,
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.family = FAM_STM32L4xx,
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.designator = "STM32L49x",
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.sram1 = 256,
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.sram2 = 64,
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.flags = 2 | DUAL_BANK,
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},
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{
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.idcode = ID_STM32L4R,
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.family = FAM_STM32L4Rx,
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.designator = "STM32L4Rx",
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.sram1 = 192,
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.sram2 = 64,
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.sram3 = 384,
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.flags = 3 | DUAL_BANK,
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},
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{
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.idcode = ID_STM32G07,
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.family = FAM_STM32G0x,
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.designator = "STM32G07",
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.sram1 = 36,
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.flags = 1,
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},
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{
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/* Terminator */
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.idcode = 0,
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},
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};
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/* Retrieve chip basic information, just add to the vector to extend */
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static struct stm32l4_info const * stm32l4_get_chip_info(uint32_t idcode) {
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struct stm32l4_info const *p = L4info;
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while (p->idcode && (p->idcode != idcode))
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p++;
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return p;
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}
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static void stm32l4_add_flash(target *t,
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uint32_t addr, size_t length, size_t blocksize,
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uint32_t bank1_start)
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@ -141,61 +243,61 @@ static void stm32l4_add_flash(target *t,
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target_add_flash(t, f);
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}
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enum ID_STM32L4 {
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ID_STM32L43 = 0x435, /* RM0394, Rev.4 */
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ID_STM32L45 = 0x462, /* RM0394, Rev.4 */
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ID_STM32L41 = 0x464, /* RM0394, Rev.4 */
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ID_STM32L47 = 0x415, /* RM0351, Rev.5 */
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ID_STM32G07 = 0x460, /* RM0444/454, Rev.1 */
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ID_STM32L49 = 0x461, /* RM0351, Rev.5 */
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ID_STM32L4R = 0x470, /* RM0432, Rev.5 */
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};
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static bool stm32l4_attach(target *t)
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{
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if (!cortexm_attach(t))
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return false;
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bool dual_bank = false;
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uint32_t idcodereg = STM32L4_DBGMCU_IDCODE_PHYS;
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uint32_t size = 0;
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/* Retrive chip information, no need to check return */
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struct stm32l4_info const *chip = stm32l4_get_chip_info(t->idcode);
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uint32_t idcodereg = (chip->family == FAM_STM32G0x)
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? STM32G0_DBGMCU_IDCODE_PHYS
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: STM32L4_DBGMCU_IDCODE_PHYS;
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switch(t->idcode) {
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case ID_STM32L47:
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case ID_STM32L49:
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case ID_STM32L4R:
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dual_bank = true;
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break;
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case ID_STM32G07:
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idcodereg = STM32G0_DBGMCU_IDCODE_PHYS;
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break;
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}
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/* Save DBGMCU_CR to restore it when detaching*/
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uint32_t dbgmcu_cr = target_mem_read32(t, DBGMCU_CR(idcodereg));
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t->target_storage = dbgmcu_cr;
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/* Enable debugging during all low power modes*/
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target_mem_write32(t, DBGMCU_CR(idcodereg), DBGMCU_CR_DBG_SLEEP | DBGMCU_CR_DBG_STANDBY | DBGMCU_CR_DBG_STOP);
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size = (target_mem_read32(t, FLASH_SIZE_REG) & 0xffff);
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if (dual_bank) {
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uint32_t options = target_mem_read32(t, FLASH_OPTR);
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if (t->idcode == ID_STM32L4R) {
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/* rm0432 Rev. 2 does not mention 1 MB devices or explain DB1M.*/
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if (options & OR_DBANK) {
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stm32l4_add_flash(t, 0x08000000, 0x00100000, 0x1000, 0x08100000);
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stm32l4_add_flash(t, 0x08100000, 0x00100000, 0x1000, 0x08100000);
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} else
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stm32l4_add_flash(t, 0x08000000, 0x00200000, 0x2000, -1);
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/* Free previously loaded memory map */
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target_mem_map_free(t);
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/* Add RAM to memory map */
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if (chip->family == FAM_STM32G0x) {
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target_add_ram(t, 0x20000000, chip->sram1 << 10);
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} else {
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target_add_ram(t, 0x10000000, chip->sram2 << 10);
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/* All L4 beside L47 alias SRAM2 after SRAM1.*/
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uint32_t ramsize = (t->idcode == ID_STM32L47)?
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chip->sram1 : (chip->sram1 + chip->sram2 + chip->sram3);
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target_add_ram(t, 0x20000000, ramsize << 10);
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}
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/* Add the flash to memory map. */
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uint32_t size = target_mem_read16(t, FLASH_SIZE_REG);
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uint32_t options = target_mem_read32(t, FLASH_OPTR);
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if (chip->family == FAM_STM32L4Rx) {
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/* rm0432 Rev. 2 does not mention 1 MB devices or explain DB1M.*/
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if (options & OR_DBANK) {
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stm32l4_add_flash(t, 0x08000000, 0x00100000, 0x1000, 0x08100000);
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stm32l4_add_flash(t, 0x08100000, 0x00100000, 0x1000, 0x08100000);
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} else
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stm32l4_add_flash(t, 0x08000000, 0x00200000, 0x2000, -1);
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} else if (chip->flags & DUAL_BANK) {
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if (options & OR_DUALBANK) {
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uint32_t banksize = size << 9;
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stm32l4_add_flash(t, 0x08000000 , banksize, 0x0800, 0x08000000 + banksize);
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stm32l4_add_flash(t, 0x08000000 + banksize, banksize, 0x0800, 0x08000000 + banksize);
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} else {
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if (options & OR_DUALBANK) {
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uint32_t banksize = size << 9;
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stm32l4_add_flash(t, 0x08000000 , banksize, 0x0800, 0x08000000 + banksize);
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stm32l4_add_flash(t, 0x08000000 + banksize, banksize, 0x0800, 0x08000000 + banksize);
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} else {
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uint32_t banksize = size << 10;
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stm32l4_add_flash(t, 0x08000000 , banksize, 0x0800, -1);
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}
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uint32_t banksize = size << 10;
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stm32l4_add_flash(t, 0x08000000 , banksize, 0x0800, -1);
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}
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} else
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stm32l4_add_flash(t, 0x08000000, size << 10, 0x800, -1);
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@ -218,71 +320,22 @@ static void stm32l4_detach(target *t)
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bool stm32l4_probe(target *t)
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{
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const char* designator = NULL;
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bool is_stm32g0 = false;
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uint16_t sram1_size = 0;
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uint16_t sram2_size = 0;
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uint16_t sram3_size = 0;
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uint32_t idcode_reg = STM32L4_DBGMCU_IDCODE_PHYS;
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ADIv5_AP_t *ap = cortexm_ap(t);
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if (ap->dp->idcode == 0x0BC11477)
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idcode_reg = STM32G0_DBGMCU_IDCODE_PHYS;
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uint32_t idcode = target_mem_read32(t, idcode_reg) & 0xfff;
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switch(idcode) {
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case ID_STM32G07:
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designator = "STM32G07";
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is_stm32g0 = true;
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sram1_size = 36;
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break;
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case ID_STM32L41:
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designator = "STM32L41x";
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sram1_size = 32;
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sram2_size = 8;
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break;
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case ID_STM32L43:
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designator = "STM32L43x";
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sram1_size = 48;
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sram2_size = 16;
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break;
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case ID_STM32L45:
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designator = "STM32L45x";
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sram1_size = 128;
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sram2_size = 32;
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break;
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case ID_STM32L47:
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designator = "STM32L47x";
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sram1_size = 96;
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sram2_size = 32;
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break;
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case ID_STM32L49:
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designator = "STM32L49x";
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sram1_size = 256;
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sram2_size = 64;
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break;
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case ID_STM32L4R:
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designator = "STM32L4Rx";
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sram1_size = 192;
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sram2_size = 64;
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sram3_size = 384;
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break;
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default:
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struct stm32l4_info const *chip = stm32l4_get_chip_info(idcode);
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if( !chip->idcode ) /* Not found */
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return false;
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}
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t->idcode = idcode;
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t->driver = designator;
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t->driver = chip->designator;
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t->attach = stm32l4_attach;
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t->detach = stm32l4_detach;
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if (is_stm32g0) {
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target_add_ram(t, 0x20000000, sram1_size << 10);
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} else {
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target_add_ram(t, 0x10000000, sram2_size << 10);
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/* All L4 beside L47 alias SRAM2 after SRAM1.*/
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uint32_t ramsize = (idcode == ID_STM32L47)?
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sram1_size : (sram1_size + sram2_size + sram3_size);
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target_add_ram(t, 0x20000000, ramsize << 10);
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}
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target_add_commands(t, stm32l4_cmd_list, designator);
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target_add_commands(t, stm32l4_cmd_list, chip->designator);
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return true;
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}
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@ -413,7 +466,7 @@ static const uint8_t g0_i2offset[7] = {
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static bool stm32l4_option_write(
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target *t,const uint32_t *values, int len, const uint8_t *i2offset)
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{
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tc_printf(t, "Device will loose connection. Rescan!\n");
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tc_printf(t, "Device will lose connection. Rescan!\n");
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stm32l4_flash_unlock(t);
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target_mem_write32(t, FLASH_OPTKEYR, OPTKEY1);
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target_mem_write32(t, FLASH_OPTKEYR, OPTKEY2);
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@ -459,7 +512,7 @@ static bool stm32l4_cmd_option(target *t, int argc, char *argv[])
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const uint8_t *i2offset = l4_i2offset;
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if (t->idcode == 0x435) {/* L43x */
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len = 5;
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} else if (t->idcode == 0x460) {/* G07x */
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} else if (t->idcode == ID_STM32G07) {/* G07x */
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i2offset = g0_i2offset;
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len = 7;
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} else {
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