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pc-stlinkv2: CPU register read and write must be done with the AP set. 

FIXME: Writing CPU registers on M4 of STM32H745 seems not to work.
This commit is contained in:
Uwe Bonnes 2019-08-19 16:26:21 +02:00
parent e52e2f56c5
commit 6bf4fd3598
3 changed files with 25 additions and 22 deletions
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23
src/platforms/pc-stlinkv2/stlinkv2.c
View File

@ -1197,37 +1197,40 @@ void stlink_writemem32(ADIv5_AP_t *ap, uint32_t addr, size_t len,
write_retry(cmd, 16, (void*)buffer, len); write_retry(cmd, 16, (void*)buffer, len);
} }
void stlink_regs_read(void *data) void stlink_regs_read(ADIv5_AP_t *ap, void *data)
{ {
uint8_t cmd[16] = {STLINK_DEBUG_COMMAND, STLINK_DEBUG_APIV2_READALLREGS}; uint8_t cmd[16] = {STLINK_DEBUG_COMMAND, STLINK_DEBUG_APIV2_READALLREGS,
ap->apsel};
uint8_t res[88]; uint8_t res[88];
DEBUG_STLINK("Read all core registers\n"); DEBUG_STLINK("AP %d: Read all core registers\n", ap->apsel);
send_recv(cmd, 16, res, 88); send_recv(cmd, 16, res, 88);
stlink_usb_error_check(res, true); stlink_usb_error_check(res, true);
memcpy(data, res + 4, 84); memcpy(data, res + 4, 84);
} }
uint32_t stlink_reg_read(int num) uint32_t stlink_reg_read(ADIv5_AP_t *ap, int num)
{ {
uint8_t cmd[16] = {STLINK_DEBUG_COMMAND, STLINK_DEBUG_APIV2_READREG, num}; uint8_t cmd[16] = {STLINK_DEBUG_COMMAND, STLINK_DEBUG_APIV2_READREG, num,
ap->apsel};
uint8_t res[8]; uint8_t res[8];
send_recv(cmd, 16, res, 8); send_recv(cmd, 16, res, 8);
stlink_usb_error_check(res, true); stlink_usb_error_check(res, true);
uint32_t ret = res[0] | res[1] << 8 | res[2] << 16 | res[3] << 24; uint32_t ret = res[0] | res[1] << 8 | res[2] << 16 | res[3] << 24;
DEBUG_STLINK("Read reg %02" PRId32 " val 0x%08" PRIx32 "\n", num, ret); DEBUG_STLINK("AP %d: Read reg %02" PRId32 " val 0x%08" PRIx32 "\n",
ap->apsel, num, ret);
return ret; return ret;
} }
void stlink_reg_write(int num, uint32_t val) void stlink_reg_write(ADIv5_AP_t *ap, int num, uint32_t val)
{ {
uint8_t cmd[16] = { uint8_t cmd[16] = {
STLINK_DEBUG_COMMAND, STLINK_DEBUG_APIV2_WRITEREG, num, STLINK_DEBUG_COMMAND, STLINK_DEBUG_APIV2_WRITEREG, num,
val & 0xff, (val >> 8) & 0xff, (val >> 16) & 0xff, val & 0xff, (val >> 8) & 0xff, (val >> 16) & 0xff,
(val >> 24) & 0xff (val >> 24) & 0xff, ap->apsel};
};
uint8_t res[2]; uint8_t res[2];
send_recv(cmd, 16, res, 2); send_recv(cmd, 16, res, 2);
DEBUG_STLINK("Write reg %02" PRId32 " val 0x%08" PRIx32 "\n", num, val); DEBUG_STLINK("AP %d: Write reg %02" PRId32 " val 0x%08" PRIx32 "\n",
ap->apsel, num, val);
stlink_usb_error_check(res, true); stlink_usb_error_check(res, true);
} }

6
src/platforms/pc-stlinkv2/stlinkv2.h
View File

@ -44,9 +44,9 @@ void stlink_dp_abort(ADIv5_DP_t *dp, uint32_t abort);
int stlink_open_ap(uint8_t ap); int stlink_open_ap(uint8_t ap);
void stlink_close_ap(uint8_t ap); void stlink_close_ap(uint8_t ap);
int stlink_usb_get_rw_status(void); int stlink_usb_get_rw_status(void);
void stlink_regs_read(void *data); void stlink_regs_read(ADIv5_AP_t *ap, void *data);
uint32_t stlink_reg_read(int idx); uint32_t stlink_reg_read(ADIv5_AP_t *ap, int idx);
void stlink_reg_write(int num, uint32_t val); void stlink_reg_write(ADIv5_AP_t *ap, int num, uint32_t val);
extern int debug_level; extern int debug_level;
# define DEBUG_STLINK if (debug_level > 0) printf # define DEBUG_STLINK if (debug_level > 0) printf
# define DEBUG_USB if (debug_level > 1) printf # define DEBUG_USB if (debug_level > 1) printf

18
src/target/cortexm.c
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@ -450,16 +450,16 @@ enum { DB_DHCSR, DB_DCRSR, DB_DCRDR, DB_DEMCR };
static void cortexm_regs_read(target *t, void *data) static void cortexm_regs_read(target *t, void *data)
{ {
uint32_t *regs = data; uint32_t *regs = data;
ADIv5_AP_t *ap = cortexm_ap(t);
#if defined(STLINKV2) #if defined(STLINKV2)
extern void stlink_regs_read(void *data); extern void stlink_regs_read(ADIv5_AP_t *ap, void *data);
extern uint32_t stlink_reg_read(int idx); extern uint32_t stlink_reg_read(ADIv5_AP_t *ap, int idx);
stlink_regs_read(data); stlink_regs_read(ap, data);
regs += sizeof(regnum_cortex_m); regs += sizeof(regnum_cortex_m);
if (t->target_options & TOPT_FLAVOUR_V7MF) if (t->target_options & TOPT_FLAVOUR_V7MF)
for(size_t t = 0; t < sizeof(regnum_cortex_mf) / 4; t++) for(size_t t = 0; t < sizeof(regnum_cortex_mf) / 4; t++)
*regs++ = stlink_reg_read(regnum_cortex_mf[t]); *regs++ = stlink_reg_read(ap, regnum_cortex_mf[t]);
#else #else
ADIv5_AP_t *ap = cortexm_ap(t);
unsigned i; unsigned i;
/* FIXME: Describe what's really going on here */ /* FIXME: Describe what's really going on here */
@ -491,19 +491,19 @@ static void cortexm_regs_read(target *t, void *data)
static void cortexm_regs_write(target *t, const void *data) static void cortexm_regs_write(target *t, const void *data)
{ {
const uint32_t *regs = data; const uint32_t *regs = data;
ADIv5_AP_t *ap = cortexm_ap(t);
#if defined(STLINKV2) #if defined(STLINKV2)
extern void stlink_reg_write(int num, uint32_t val); extern void stlink_reg_write(ADIv5_AP_t *ap, int num, uint32_t val);
for(size_t z = 1; z < sizeof(regnum_cortex_m) / 4; z++) { for(size_t z = 1; z < sizeof(regnum_cortex_m) / 4; z++) {
stlink_reg_write(regnum_cortex_m[z], *regs); stlink_reg_write(ap, regnum_cortex_m[z], *regs);
regs++; regs++;
if (t->target_options & TOPT_FLAVOUR_V7MF) if (t->target_options & TOPT_FLAVOUR_V7MF)
for(size_t z = 0; z < sizeof(regnum_cortex_mf) / 4; z++) { for(size_t z = 0; z < sizeof(regnum_cortex_mf) / 4; z++) {
stlink_reg_write(regnum_cortex_mf[z], *regs); stlink_reg_write(ap, regnum_cortex_mf[z], *regs);
regs++; regs++;
} }
} }
#else #else
ADIv5_AP_t *ap = cortexm_ap(t);
unsigned i; unsigned i;
/* FIXME: Describe what's really going on here */ /* FIXME: Describe what's really going on here */