swdptap: Refactored swdptap_seq_in and cleaned up
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92c7a11cd2
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@ -59,40 +59,47 @@ static void swdptap_turnaround(const swdio_status_t dir)
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SWDIO_MODE_DRIVE();
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}
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static uint32_t swdptap_seq_in_swd_delay(size_t clock_cycles) __attribute__((optimize(3)));
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static uint32_t swdptap_seq_in_swd_delay(size_t clock_cycles)
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{
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size_t index = 0;
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uint32_t value = 0;
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while (clock_cycles--) {
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if (gpio_get(SWDIO_PORT, SWDIO_PIN))
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value |= (1U << index);
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gpio_set(SWCLK_PORT, SWCLK_PIN);
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for (volatile int32_t cnt = swd_delay_cnt - 2; cnt > 0; cnt--)
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continue;
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++index;
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gpio_clear(SWCLK_PORT, SWCLK_PIN);
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for (volatile int32_t cnt = swd_delay_cnt - 2; cnt > 0; cnt--)
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continue;
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}
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return value;
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}
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static uint32_t swdptap_seq_in_no_delay(size_t clock_cycles) __attribute__((optimize(3)));
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static uint32_t swdptap_seq_in_no_delay(size_t clock_cycles)
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{
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size_t index = 0;
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uint32_t value = 0;
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while (clock_cycles--) {
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if (gpio_get(SWDIO_PORT, SWDIO_PIN))
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value |= (1U << index);
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gpio_set(SWCLK_PORT, SWCLK_PIN);
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++index;
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gpio_clear(SWCLK_PORT, SWCLK_PIN);
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}
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return value;
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}
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static uint32_t swdptap_seq_in(size_t clock_cycles)
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{
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uint32_t index = 1;
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uint32_t ret = 0;
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int len = clock_cycles;
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register volatile int32_t cnt;
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swdptap_turnaround(SWDIO_STATUS_FLOAT);
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if (swd_delay_cnt) {
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while (len--) {
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int res;
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res = gpio_get(SWDIO_PORT, SWDIO_PIN);
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gpio_set(SWCLK_PORT, SWCLK_PIN);
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for(cnt = swd_delay_cnt; --cnt > 0;);
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ret |= (res) ? index : 0;
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index <<= 1;
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gpio_clear(SWCLK_PORT, SWCLK_PIN);
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for(cnt = swd_delay_cnt; --cnt > 0;);
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}
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} else {
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volatile int res;
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while (len--) {
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res = gpio_get(SWDIO_PORT, SWDIO_PIN);
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gpio_set(SWCLK_PORT, SWCLK_PIN);
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ret |= (res) ? index : 0;
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index <<= 1;
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gpio_clear(SWCLK_PORT, SWCLK_PIN);
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}
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}
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#ifdef DEBUG_SWD_BITS
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for (int i = 0; i < len; i++)
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DEBUG("%d", (ret & (1 << i)) ? 1 : 0);
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#endif
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return ret;
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if (swd_delay_cnt)
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return swdptap_seq_in_swd_delay(clock_cycles);
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else // NOLINT(readability-else-after-return)
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return swdptap_seq_in_no_delay(clock_cycles);
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}
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static bool swdptap_seq_in_parity(uint32_t *ret, size_t ticks)
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