misc: code format & cleanup
This commit is contained in:
Rafael Silva
Rachel Mant
parent
460bd1e477
commit
73f3910f62
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@ -487,14 +487,15 @@ static void adiv5_component_probe(ADIv5_AP_t *ap, uint32_t addr, const size_t re
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if (pidr & PIDR_JEP106_USED) {
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/* (OFFSET - 8) because we want it on bits 11:8 of new code, see "JEP-106 code list" */
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designer_code = (pidr & PIDR_JEP106_CONT_MASK) >> (PIDR_JEP106_CONT_OFFSET - 8) |
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(pidr & PIDR_JEP106_CODE_MASK) >> PIDR_JEP106_CODE_OFFSET;
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(pidr & PIDR_JEP106_CODE_MASK) >> PIDR_JEP106_CODE_OFFSET;
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if (designer_code == JEP106_MANUFACTURER_ERRATA_STM32WX || designer_code == JEP106_MANUFACTURER_ERRATA_CS) {
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/**
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* see 'JEP-106 code list' for context, here we are aliasing codes that are non compliant with the
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* JEP-106 standard to their expected codes, this is later used to determine the correct probe function.
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*/
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DEBUG_WARN("Patching Designer code 0x%03" PRIx16 " -> 0x%03" PRIx16 "\n", designer_code, JEP106_MANUFACTURER_STM);
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DEBUG_WARN(
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"Patching Designer code 0x%03" PRIx16 " -> 0x%03" PRIx16 "\n", designer_code, JEP106_MANUFACTURER_STM);
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designer_code = JEP106_MANUFACTURER_STM;
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}
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} else {
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@ -32,15 +32,17 @@
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unsigned int make_packet_request(uint8_t RnW, uint16_t addr)
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{
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bool APnDP = addr & ADIV5_APnDP;
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addr &= 0xff;
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unsigned int request = 0x81; /* Park and Startbit */
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if(APnDP) request ^= 0x22;
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if(RnW) request ^= 0x24;
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addr &= 0xffU;
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unsigned int request = 0x81U; /* Park and Startbit */
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if (APnDP)
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request ^= 0x22U;
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if (RnW)
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request ^= 0x24U;
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addr &= 0xC;
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request |= (addr << 1) & 0x18;
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if((addr == 4) || (addr == 8))
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request ^= 0x20;
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addr &= 0xcU;
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request |= (addr << 1U) & 0x18U;
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if (addr == 4U || addr == 8U)
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request ^= 0x20U;
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return request;
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}
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@ -48,13 +50,13 @@ unsigned int make_packet_request(uint8_t RnW, uint16_t addr)
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static void dp_line_reset(ADIv5_DP_t *dp)
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{
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dp->seq_out(0xFFFFFFFF, 32);
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dp->seq_out(0x0FFFFFFF, 32);
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dp->seq_out(0xFFFFFFFFU, 32U);
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dp->seq_out(0x0FFFFFFFU, 32U);
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}
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bool firmware_dp_low_write(ADIv5_DP_t *dp, uint16_t addr, const uint32_t data)
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{
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unsigned int request = make_packet_request(ADIV5_LOW_WRITE, addr & 0xf);
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unsigned int request = make_packet_request(ADIV5_LOW_WRITE, addr & 0xfU);
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dp->seq_out(request, 8);
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int res = dp->seq_in(3);
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dp->seq_out_parity(data, 32);
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@ -143,14 +145,13 @@ int adiv5_swdp_scan(uint32_t targetid)
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} else {
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target_id = targetid;
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}
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volatile int nr_dps = (scan_multidrop) ? 16: 1;
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const volatile size_t nr_dps = (scan_multidrop) ? 16U : 1U;
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volatile uint32_t dp_targetid;
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for (volatile int i = 0; i < nr_dps; i++) {
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for (volatile size_t i = 0; i < nr_dps; i++) {
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if (scan_multidrop) {
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dp_line_reset(initial_dp);
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dp_targetid = (i << 28) | (target_id & 0x0fffffff);
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initial_dp->dp_low_write(initial_dp, ADIV5_DP_TARGETSEL,
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dp_targetid);
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dp_targetid = (i << 28U) | (target_id & 0x0fffffffU);
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initial_dp->dp_low_write(initial_dp, ADIV5_DP_TARGETSEL, dp_targetid);
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TRY_CATCH (e, EXCEPTION_ALL) {
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idcode = initial_dp->dp_read(initial_dp, ADIV5_DP_IDCODE);
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}
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@ -160,8 +161,8 @@ int adiv5_swdp_scan(uint32_t targetid)
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} else {
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dp_targetid = target_id;
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}
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ADIv5_DP_t *dp = (void*)calloc(1, sizeof(*dp));
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if (!dp) { /* calloc failed: heap exhaustion */
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ADIv5_DP_t *dp = calloc(1, sizeof(*dp));
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if (!dp) { /* calloc failed: heap exhaustion */
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DEBUG_WARN("calloc: failed in %s\n", __func__);
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continue;
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}
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@ -169,26 +170,23 @@ int adiv5_swdp_scan(uint32_t targetid)
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dp->idcode = idcode;
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dp->targetid = dp_targetid;
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adiv5_dp_init(dp);
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}
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return target_list?1:0;
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return target_list ? 1U : 0U;
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}
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uint32_t firmware_swdp_read(ADIv5_DP_t *dp, uint16_t addr)
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{
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if (addr & ADIV5_APnDP) {
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adiv5_dp_low_access(dp, ADIV5_LOW_READ, addr, 0);
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return adiv5_dp_low_access(dp, ADIV5_LOW_READ,
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ADIV5_DP_RDBUFF, 0);
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return adiv5_dp_low_access(dp, ADIV5_LOW_READ, ADIV5_DP_RDBUFF, 0);
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} else {
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return firmware_swdp_low_access(dp, ADIV5_LOW_READ, addr, 0);
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}
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}
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uint32_t firmware_swdp_error(ADIv5_DP_t *dp)
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uint32_t firmware_swdp_error(ADIv5_DP_t *dp)
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{
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if ((dp->fault && (dp->idcode & ADIV5_DP_DPIDR_VERSION_MASK) == ADIV5_DP_DPIDR_VERSION_DPv2) &&
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dp->dp_low_write) {
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if ((dp->fault && (dp->idcode & ADIV5_DP_DPIDR_VERSION_MASK) == ADIV5_DP_DPIDR_VERSION_DPv2) && dp->dp_low_write) {
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/* On protocoll error target gets deselected.
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* With DP Change, another target needs selection.
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* => Reselect with right target! */
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@ -198,17 +196,16 @@ uint32_t firmware_swdp_read(ADIv5_DP_t *dp, uint16_t addr)
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/* Exception here is unexpected, so do not catch */
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}
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uint32_t err, clr = 0;
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err = adiv5_dp_read(dp, ADIV5_DP_CTRLSTAT) &
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(ADIV5_DP_CTRLSTAT_STICKYORUN | ADIV5_DP_CTRLSTAT_STICKYCMP |
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ADIV5_DP_CTRLSTAT_STICKYERR | ADIV5_DP_CTRLSTAT_WDATAERR);
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err = adiv5_dp_read(dp, ADIV5_DP_CTRLSTAT) & (ADIV5_DP_CTRLSTAT_STICKYORUN | ADIV5_DP_CTRLSTAT_STICKYCMP |
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ADIV5_DP_CTRLSTAT_STICKYERR | ADIV5_DP_CTRLSTAT_WDATAERR);
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if(err & ADIV5_DP_CTRLSTAT_STICKYORUN)
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if (err & ADIV5_DP_CTRLSTAT_STICKYORUN)
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clr |= ADIV5_DP_ABORT_ORUNERRCLR;
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if(err & ADIV5_DP_CTRLSTAT_STICKYCMP)
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if (err & ADIV5_DP_CTRLSTAT_STICKYCMP)
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clr |= ADIV5_DP_ABORT_STKCMPCLR;
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if(err & ADIV5_DP_CTRLSTAT_STICKYERR)
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if (err & ADIV5_DP_CTRLSTAT_STICKYERR)
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clr |= ADIV5_DP_ABORT_STKERRCLR;
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if(err & ADIV5_DP_CTRLSTAT_WDATAERR)
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if (err & ADIV5_DP_CTRLSTAT_WDATAERR)
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clr |= ADIV5_DP_ABORT_WDERRCLR;
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adiv5_dp_write(dp, ADIV5_DP_ABORT, clr);
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@ -217,8 +214,7 @@ uint32_t firmware_swdp_read(ADIv5_DP_t *dp, uint16_t addr)
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return err;
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}
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uint32_t firmware_swdp_low_access(ADIv5_DP_t *dp, uint8_t RnW,
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uint16_t addr, uint32_t value)
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uint32_t firmware_swdp_low_access(ADIv5_DP_t *dp, uint8_t RnW, uint16_t addr, uint32_t value)
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{
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uint32_t request = make_packet_request(RnW, addr);
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uint32_t response = 0;
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File diff suppressed because it is too large
Load Diff
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@ -24,174 +24,172 @@
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extern unsigned cortexm_wait_timeout;
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/* Private peripheral bus base address */
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#define CORTEXM_PPB_BASE 0xE0000000
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#define CORTEXM_PPB_BASE 0xe0000000U
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#define CORTEXM_SCS_BASE (CORTEXM_PPB_BASE + 0xE000)
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#define CORTEXM_SCS_BASE (CORTEXM_PPB_BASE + 0xe000U)
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#define CORTEXM_CPUID (CORTEXM_SCS_BASE + 0xD00)
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#define CORTEXM_AIRCR (CORTEXM_SCS_BASE + 0xD0C)
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#define CORTEXM_CFSR (CORTEXM_SCS_BASE + 0xD28)
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#define CORTEXM_HFSR (CORTEXM_SCS_BASE + 0xD2C)
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#define CORTEXM_DFSR (CORTEXM_SCS_BASE + 0xD30)
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#define CORTEXM_CPACR (CORTEXM_SCS_BASE + 0xD88)
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#define CORTEXM_DHCSR (CORTEXM_SCS_BASE + 0xDF0)
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#define CORTEXM_DCRSR (CORTEXM_SCS_BASE + 0xDF4)
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#define CORTEXM_DCRDR (CORTEXM_SCS_BASE + 0xDF8)
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#define CORTEXM_DEMCR (CORTEXM_SCS_BASE + 0xDFC)
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#define CORTEXM_CPUID (CORTEXM_SCS_BASE + 0xd00U)
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#define CORTEXM_AIRCR (CORTEXM_SCS_BASE + 0xd0cU)
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#define CORTEXM_CFSR (CORTEXM_SCS_BASE + 0xd28U)
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#define CORTEXM_HFSR (CORTEXM_SCS_BASE + 0xd2cU)
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#define CORTEXM_DFSR (CORTEXM_SCS_BASE + 0xd30U)
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#define CORTEXM_CPACR (CORTEXM_SCS_BASE + 0xd88U)
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#define CORTEXM_DHCSR (CORTEXM_SCS_BASE + 0xdf0U)
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#define CORTEXM_DCRSR (CORTEXM_SCS_BASE + 0xdf4U)
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#define CORTEXM_DCRDR (CORTEXM_SCS_BASE + 0xdf8U)
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#define CORTEXM_DEMCR (CORTEXM_SCS_BASE + 0xdfcU)
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/* Cache identification */
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#define CORTEXM_CLIDR (CORTEXM_SCS_BASE + 0xD78)
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#define CORTEXM_CTR (CORTEXM_SCS_BASE + 0xD7C)
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#define CORTEXM_CCSIDR (CORTEXM_SCS_BASE + 0xD80)
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#define CORTEXM_CSSELR (CORTEXM_SCS_BASE + 0xD84)
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#define CORTEXM_CLIDR (CORTEXM_SCS_BASE + 0xd78U)
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#define CORTEXM_CTR (CORTEXM_SCS_BASE + 0xd7cU)
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#define CORTEXM_CCSIDR (CORTEXM_SCS_BASE + 0xd80U)
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#define CORTEXM_CSSELR (CORTEXM_SCS_BASE + 0xd84U)
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/* Cache maintenance operations */
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#define CORTEXM_ICIALLU (CORTEXM_SCS_BASE + 0xF50)
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#define CORTEXM_DCCMVAC (CORTEXM_SCS_BASE + 0xF68)
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#define CORTEXM_DCCIMVAC (CORTEXM_SCS_BASE + 0xF70)
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#define CORTEXM_ICIALLU (CORTEXM_SCS_BASE + 0xf50U)
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#define CORTEXM_DCCMVAC (CORTEXM_SCS_BASE + 0xf68U)
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#define CORTEXM_DCCIMVAC (CORTEXM_SCS_BASE + 0xf70U)
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#define CORTEXM_FPB_BASE (CORTEXM_PPB_BASE + 0x2000)
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#define CORTEXM_FPB_BASE (CORTEXM_PPB_BASE + 0x2000U)
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/* ARM Literature uses FP_*, we use CORTEXM_FPB_* consistently */
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#define CORTEXM_FPB_CTRL (CORTEXM_FPB_BASE + 0x000)
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#define CORTEXM_FPB_REMAP (CORTEXM_FPB_BASE + 0x004)
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#define CORTEXM_FPB_COMP(i) (CORTEXM_FPB_BASE + 0x008 + (4*(i)))
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#define CORTEXM_FPB_CTRL (CORTEXM_FPB_BASE + 0x000U)
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#define CORTEXM_FPB_REMAP (CORTEXM_FPB_BASE + 0x004U)
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#define CORTEXM_FPB_COMP(i) (CORTEXM_FPB_BASE + 0x008U + (4U * (i)))
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#define CORTEXM_DWT_BASE (CORTEXM_PPB_BASE + 0x1000)
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#define CORTEXM_DWT_BASE (CORTEXM_PPB_BASE + 0x1000U)
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#define CORTEXM_DWT_CTRL (CORTEXM_DWT_BASE + 0x000)
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#define CORTEXM_DWT_COMP(i) (CORTEXM_DWT_BASE + 0x020 + (0x10*(i)))
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#define CORTEXM_DWT_MASK(i) (CORTEXM_DWT_BASE + 0x024 + (0x10*(i)))
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#define CORTEXM_DWT_FUNC(i) (CORTEXM_DWT_BASE + 0x028 + (0x10*(i)))
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#define CORTEXM_DWT_CTRL (CORTEXM_DWT_BASE + 0x000U)
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#define CORTEXM_DWT_COMP(i) (CORTEXM_DWT_BASE + 0x020U + (0x10U * (i)))
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#define CORTEXM_DWT_MASK(i) (CORTEXM_DWT_BASE + 0x024U + (0x10U * (i)))
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#define CORTEXM_DWT_FUNC(i) (CORTEXM_DWT_BASE + 0x028U + (0x10U * (i)))
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/* Application Interrupt and Reset Control Register (AIRCR) */
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#define CORTEXM_AIRCR_VECTKEY (0x05FA << 16)
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#define CORTEXM_AIRCR_VECTKEY (0x05faU << 16U)
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/* Bits 31:16 - Read as VECTKETSTAT, 0xFA05 */
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#define CORTEXM_AIRCR_ENDIANESS (1 << 15)
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#define CORTEXM_AIRCR_ENDIANESS (1U << 15U)
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/* Bits 15:11 - Unused, reserved */
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#define CORTEXM_AIRCR_PRIGROUP (7 << 8)
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#define CORTEXM_AIRCR_PRIGROUP (7U << 8U)
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/* Bits 7:3 - Unused, reserved */
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#define CORTEXM_AIRCR_SYSRESETREQ (1 << 2)
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#define CORTEXM_AIRCR_VECTCLRACTIVE (1 << 1)
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#define CORTEXM_AIRCR_VECTRESET (1 << 0)
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#define CORTEXM_AIRCR_SYSRESETREQ (1U << 2U)
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#define CORTEXM_AIRCR_VECTCLRACTIVE (1U << 1U)
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#define CORTEXM_AIRCR_VECTRESET (1U << 0U)
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/* HardFault Status Register (HFSR) */
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#define CORTEXM_HFSR_DEBUGEVT (1 << 31)
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#define CORTEXM_HFSR_FORCED (1 << 30)
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#define CORTEXM_HFSR_DEBUGEVT (1U << 31U)
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#define CORTEXM_HFSR_FORCED (1U << 30U)
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/* Bits 29:2 - Not specified */
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#define CORTEXM_HFSR_VECTTBL (1 << 1)
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#define CORTEXM_HFSR_VECTTBL (1U << 1U)
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/* Bits 0 - Reserved */
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/* Debug Fault Status Register (DFSR) */
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/* Bits 31:5 - Reserved */
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#define CORTEXM_DFSR_RESETALL 0x1F
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#define CORTEXM_DFSR_EXTERNAL (1 << 4)
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#define CORTEXM_DFSR_VCATCH (1 << 3)
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#define CORTEXM_DFSR_DWTTRAP (1 << 2)
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#define CORTEXM_DFSR_BKPT (1 << 1)
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#define CORTEXM_DFSR_HALTED (1 << 0)
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#define CORTEXM_DFSR_RESETALL 0x1fU
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#define CORTEXM_DFSR_EXTERNAL (1U << 4U)
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#define CORTEXM_DFSR_VCATCH (1U << 3U)
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#define CORTEXM_DFSR_DWTTRAP (1U << 2U)
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#define CORTEXM_DFSR_BKPT (1U << 1U)
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#define CORTEXM_DFSR_HALTED (1U << 0U)
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/* Debug Halting Control and Status Register (DHCSR) */
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/* This key must be written to bits 31:16 for write to take effect */
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#define CORTEXM_DHCSR_DBGKEY 0xA05F0000
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#define CORTEXM_DHCSR_DBGKEY 0xa05f0000U
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/* Bits 31:26 - Reserved */
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#define CORTEXM_DHCSR_S_RESET_ST (1 << 25)
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#define CORTEXM_DHCSR_S_RETIRE_ST (1 << 24)
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#define CORTEXM_DHCSR_S_RESET_ST (1U << 25U)
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#define CORTEXM_DHCSR_S_RETIRE_ST (1U << 24U)
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/* Bits 23:20 - Reserved */
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#define CORTEXM_DHCSR_S_LOCKUP (1 << 19)
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#define CORTEXM_DHCSR_S_SLEEP (1 << 18)
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#define CORTEXM_DHCSR_S_HALT (1 << 17)
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#define CORTEXM_DHCSR_S_REGRDY (1 << 16)
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#define CORTEXM_DHCSR_S_LOCKUP (1U << 19U)
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#define CORTEXM_DHCSR_S_SLEEP (1U << 18U)
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#define CORTEXM_DHCSR_S_HALT (1U << 17U)
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#define CORTEXM_DHCSR_S_REGRDY (1U << 16U)
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/* Bits 15:6 - Reserved */
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#define CORTEXM_DHCSR_C_SNAPSTALL (1 << 5) /* v7m only */
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#define CORTEXM_DHCSR_C_SNAPSTALL (1U << 5U) /* v7m only */
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/* Bit 4 - Reserved */
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#define CORTEXM_DHCSR_C_MASKINTS (1 << 3)
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#define CORTEXM_DHCSR_C_STEP (1 << 2)
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#define CORTEXM_DHCSR_C_HALT (1 << 1)
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#define CORTEXM_DHCSR_C_DEBUGEN (1 << 0)
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#define CORTEXM_DHCSR_C_MASKINTS (1U << 3U)
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#define CORTEXM_DHCSR_C_STEP (1U << 2U)
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#define CORTEXM_DHCSR_C_HALT (1U << 1U)
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#define CORTEXM_DHCSR_C_DEBUGEN (1U << 0U)
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/* Debug Core Register Selector Register (DCRSR) */
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#define CORTEXM_DCRSR_REGWnR 0x00010000
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#define CORTEXM_DCRSR_REGSEL_MASK 0x0000001F
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#define CORTEXM_DCRSR_REGSEL_XPSR 0x00000010
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#define CORTEXM_DCRSR_REGSEL_MSP 0x00000011
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#define CORTEXM_DCRSR_REGSEL_PSP 0x00000012
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#define CORTEXM_DCRSR_REGWnR 0x00010000
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#define CORTEXM_DCRSR_REGSEL_MASK 0x0000001f
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||||
#define CORTEXM_DCRSR_REGSEL_XPSR 0x00000010
|
||||
#define CORTEXM_DCRSR_REGSEL_MSP 0x00000011
|
||||
#define CORTEXM_DCRSR_REGSEL_PSP 0x00000012
|
||||
|
||||
/* Debug Exception and Monitor Control Register (DEMCR) */
|
||||
/* Bits 31:25 - Reserved */
|
||||
#define CORTEXM_DEMCR_TRCENA (1 << 24)
|
||||
#define CORTEXM_DEMCR_TRCENA (1U << 24U)
|
||||
/* Bits 23:20 - Reserved */
|
||||
#define CORTEXM_DEMCR_MON_REQ (1 << 19) /* v7m only */
|
||||
#define CORTEXM_DEMCR_MON_STEP (1 << 18) /* v7m only */
|
||||
#define CORTEXM_DEMCR_VC_MON_PEND (1 << 17) /* v7m only */
|
||||
#define CORTEXM_DEMCR_VC_MON_EN (1 << 16) /* v7m only */
|
||||
#define CORTEXM_DEMCR_MON_REQ (1U << 19U) /* v7m only */
|
||||
#define CORTEXM_DEMCR_MON_STEP (1U << 18U) /* v7m only */
|
||||
#define CORTEXM_DEMCR_VC_MON_PEND (1U << 17U) /* v7m only */
|
||||
#define CORTEXM_DEMCR_VC_MON_EN (1U << 16U) /* v7m only */
|
||||
/* Bits 15:11 - Reserved */
|
||||
#define CORTEXM_DEMCR_VC_HARDERR (1 << 10)
|
||||
#define CORTEXM_DEMCR_VC_INTERR (1 << 9) /* v7m only */
|
||||
#define CORTEXM_DEMCR_VC_BUSERR (1 << 8) /* v7m only */
|
||||
#define CORTEXM_DEMCR_VC_STATERR (1 << 7) /* v7m only */
|
||||
#define CORTEXM_DEMCR_VC_CHKERR (1 << 6) /* v7m only */
|
||||
#define CORTEXM_DEMCR_VC_NOCPERR (1 << 5) /* v7m only */
|
||||
#define CORTEXM_DEMCR_VC_MMERR (1 << 4) /* v7m only */
|
||||
#define CORTEXM_DEMCR_VC_HARDERR (1U << 10U)
|
||||
#define CORTEXM_DEMCR_VC_INTERR (1U << 9U) /* v7m only */
|
||||
#define CORTEXM_DEMCR_VC_BUSERR (1U << 8U) /* v7m only */
|
||||
#define CORTEXM_DEMCR_VC_STATERR (1U << 7U) /* v7m only */
|
||||
#define CORTEXM_DEMCR_VC_CHKERR (1U << 6U) /* v7m only */
|
||||
#define CORTEXM_DEMCR_VC_NOCPERR (1U << 5U) /* v7m only */
|
||||
#define CORTEXM_DEMCR_VC_MMERR (1U << 4U) /* v7m only */
|
||||
/* Bits 3:1 - Reserved */
|
||||
#define CORTEXM_DEMCR_VC_CORERESET (1 << 0)
|
||||
#define CORTEXM_DEMCR_VC_CORERESET (1U << 0U)
|
||||
|
||||
/* Flash Patch and Breakpoint Control Register (FP_CTRL) */
|
||||
/* Bits 32:15 - Reserved */
|
||||
/* Bits 14:12 - NUM_CODE2 */ /* v7m only */
|
||||
/* Bits 11:8 - NUM_LIT */ /* v7m only */
|
||||
/* Bits 14:12 - NUM_CODE2 */ /* v7m only */
|
||||
/* Bits 11:8 - NUM_LIT */ /* v7m only */
|
||||
/* Bits 7:4 - NUM_CODE1 */
|
||||
/* Bits 3:2 - Unspecified */
|
||||
#define CORTEXM_FPB_CTRL_KEY (1 << 1)
|
||||
#define CORTEXM_FPB_CTRL_ENABLE (1 << 0)
|
||||
#define CORTEXM_FPB_CTRL_KEY (1U << 1U)
|
||||
#define CORTEXM_FPB_CTRL_ENABLE (1U << 0U)
|
||||
|
||||
/* Data Watchpoint and Trace Mask Register (DWT_MASKx)
|
||||
* The value here is the number of address bits we mask out */
|
||||
#define CORTEXM_DWT_MASK_BYTE (0)
|
||||
#define CORTEXM_DWT_MASK_HALFWORD (1)
|
||||
#define CORTEXM_DWT_MASK_WORD (2)
|
||||
#define CORTEXM_DWT_MASK_DWORD (3)
|
||||
#define CORTEXM_DWT_MASK_BYTE (0U)
|
||||
#define CORTEXM_DWT_MASK_HALFWORD (1U)
|
||||
#define CORTEXM_DWT_MASK_WORD (2U)
|
||||
#define CORTEXM_DWT_MASK_DWORD (3U)
|
||||
|
||||
/* Data Watchpoint and Trace Function Register (DWT_FUNCTIONx) */
|
||||
#define CORTEXM_DWT_FUNC_MATCHED (1 << 24)
|
||||
#define CORTEXM_DWT_FUNC_DATAVSIZE_WORD (2 << 10) /* v7m only */
|
||||
#define CORTEXM_DWT_FUNC_FUNC_READ (5 << 0)
|
||||
#define CORTEXM_DWT_FUNC_FUNC_WRITE (6 << 0)
|
||||
#define CORTEXM_DWT_FUNC_FUNC_ACCESS (7 << 0)
|
||||
#define CORTEXM_DWT_FUNC_MATCHED (1U << 24U)
|
||||
#define CORTEXM_DWT_FUNC_DATAVSIZE_WORD (2U << 10U) /* v7m only */
|
||||
#define CORTEXM_DWT_FUNC_FUNC_READ (5U << 0U)
|
||||
#define CORTEXM_DWT_FUNC_FUNC_WRITE (6U << 0U)
|
||||
#define CORTEXM_DWT_FUNC_FUNC_ACCESS (7U << 0U)
|
||||
|
||||
#define REG_SP 13
|
||||
#define REG_LR 14
|
||||
#define REG_PC 15
|
||||
#define REG_XPSR 16
|
||||
#define REG_MSP 17
|
||||
#define REG_PSP 18
|
||||
#define REG_SPECIAL 19
|
||||
#define REG_SP 13U
|
||||
#define REG_LR 14U
|
||||
#define REG_PC 15U
|
||||
#define REG_XPSR 16U
|
||||
#define REG_MSP 17U
|
||||
#define REG_PSP 18U
|
||||
#define REG_SPECIAL 19U
|
||||
|
||||
#define ARM_THUMB_BREAKPOINT 0xBE00
|
||||
#define CORTEXM_XPSR_THUMB (1 << 24)
|
||||
#define ARM_THUMB_BREAKPOINT 0xbe00U
|
||||
#define CORTEXM_XPSR_THUMB (1U << 24U)
|
||||
|
||||
#define CORTEXM_TOPT_INHIBIT_NRST (1 << 2)
|
||||
#define CORTEXM_TOPT_INHIBIT_NRST (1U << 2U)
|
||||
|
||||
enum cortexm_types {
|
||||
CORTEX_M0 = 0xc200,
|
||||
CORTEX_M0 = 0xc200,
|
||||
CORTEX_M0P = 0xc600,
|
||||
CORTEX_M3 = 0xc230,
|
||||
CORTEX_M4 = 0xc240,
|
||||
CORTEX_M7 = 0xc270,
|
||||
CORTEX_M3 = 0xc230,
|
||||
CORTEX_M4 = 0xc240,
|
||||
CORTEX_M7 = 0xc270,
|
||||
CORTEX_M23 = 0xd200,
|
||||
CORTEX_M33 = 0xd210,
|
||||
};
|
||||
#define CPUID_PARTNO_MASK 0xfff0
|
||||
#define CPUID_REVISION_MASK 0x00f00000
|
||||
#define CPUID_PATCH_MASK 0xf
|
||||
#define CPUID_PARTNO_MASK 0xfff0U
|
||||
#define CPUID_REVISION_MASK 0x00f00000U
|
||||
#define CPUID_PATCH_MASK 0xfU
|
||||
|
||||
ADIv5_AP_t *cortexm_ap(target *t);
|
||||
|
||||
bool cortexm_attach(target *t);
|
||||
void cortexm_detach(target *t);
|
||||
int cortexm_run_stub(target *t, uint32_t loadaddr,
|
||||
uint32_t r0, uint32_t r1, uint32_t r2, uint32_t r3);
|
||||
int cortexm_mem_write_sized(
|
||||
target *t, target_addr dest, const void *src, size_t len, enum align align);
|
||||
int cortexm_run_stub(target *t, uint32_t loadaddr, uint32_t r0, uint32_t r1, uint32_t r2, uint32_t r3);
|
||||
int cortexm_mem_write_sized(target *t, target_addr dest, const void *src, size_t len, enum align align);
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue