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misc: code format & cleanup

This commit is contained in:
Rafael Silva 2022-07-29 15:48:02 +01:00 committed by Rachel Mant
parent 460bd1e477
commit 73f3910f62
4 changed files with 534 additions and 500 deletions
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3
src/target/adiv5.c
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@ -494,7 +494,8 @@ static void adiv5_component_probe(ADIv5_AP_t *ap, uint32_t addr, const size_t re
* see 'JEP-106 code list' for context, here we are aliasing codes that are non compliant with the * see 'JEP-106 code list' for context, here we are aliasing codes that are non compliant with the
* JEP-106 standard to their expected codes, this is later used to determine the correct probe function. * JEP-106 standard to their expected codes, this is later used to determine the correct probe function.
*/ */
DEBUG_WARN("Patching Designer code 0x%03" PRIx16 " -> 0x%03" PRIx16 "\n", designer_code, JEP106_MANUFACTURER_STM); DEBUG_WARN(
"Patching Designer code 0x%03" PRIx16 " -> 0x%03" PRIx16 "\n", designer_code, JEP106_MANUFACTURER_STM);
designer_code = JEP106_MANUFACTURER_STM; designer_code = JEP106_MANUFACTURER_STM;
} }
} else { } else {

60
src/target/adiv5_swdp.c
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@ -32,15 +32,17 @@
unsigned int make_packet_request(uint8_t RnW, uint16_t addr) unsigned int make_packet_request(uint8_t RnW, uint16_t addr)
{ {
bool APnDP = addr & ADIV5_APnDP; bool APnDP = addr & ADIV5_APnDP;
addr &= 0xff; addr &= 0xffU;
unsigned int request = 0x81; /* Park and Startbit */ unsigned int request = 0x81U; /* Park and Startbit */
if(APnDP) request ^= 0x22; if (APnDP)
if(RnW) request ^= 0x24; request ^= 0x22U;
if (RnW)
request ^= 0x24U;
addr &= 0xC; addr &= 0xcU;
request |= (addr << 1) & 0x18; request |= (addr << 1U) & 0x18U;
if((addr == 4) || (addr == 8)) if (addr == 4U || addr == 8U)
request ^= 0x20; request ^= 0x20U;
return request; return request;
} }
@ -48,13 +50,13 @@ unsigned int make_packet_request(uint8_t RnW, uint16_t addr)
static void dp_line_reset(ADIv5_DP_t *dp) static void dp_line_reset(ADIv5_DP_t *dp)
{ {
dp->seq_out(0xFFFFFFFF, 32); dp->seq_out(0xFFFFFFFFU, 32U);
dp->seq_out(0x0FFFFFFF, 32); dp->seq_out(0x0FFFFFFFU, 32U);
} }
bool firmware_dp_low_write(ADIv5_DP_t *dp, uint16_t addr, const uint32_t data) bool firmware_dp_low_write(ADIv5_DP_t *dp, uint16_t addr, const uint32_t data)
{ {
unsigned int request = make_packet_request(ADIV5_LOW_WRITE, addr & 0xf); unsigned int request = make_packet_request(ADIV5_LOW_WRITE, addr & 0xfU);
dp->seq_out(request, 8); dp->seq_out(request, 8);
int res = dp->seq_in(3); int res = dp->seq_in(3);
dp->seq_out_parity(data, 32); dp->seq_out_parity(data, 32);
@ -143,14 +145,13 @@ int adiv5_swdp_scan(uint32_t targetid)
} else { } else {
target_id = targetid; target_id = targetid;
} }
volatile int nr_dps = (scan_multidrop) ? 16: 1; const volatile size_t nr_dps = (scan_multidrop) ? 16U : 1U;
volatile uint32_t dp_targetid; volatile uint32_t dp_targetid;
for (volatile int i = 0; i < nr_dps; i++) { for (volatile size_t i = 0; i < nr_dps; i++) {
if (scan_multidrop) { if (scan_multidrop) {
dp_line_reset(initial_dp); dp_line_reset(initial_dp);
dp_targetid = (i << 28) | (target_id & 0x0fffffff); dp_targetid = (i << 28U) | (target_id & 0x0fffffffU);
initial_dp->dp_low_write(initial_dp, ADIV5_DP_TARGETSEL, initial_dp->dp_low_write(initial_dp, ADIV5_DP_TARGETSEL, dp_targetid);
dp_targetid);
TRY_CATCH (e, EXCEPTION_ALL) { TRY_CATCH (e, EXCEPTION_ALL) {
idcode = initial_dp->dp_read(initial_dp, ADIV5_DP_IDCODE); idcode = initial_dp->dp_read(initial_dp, ADIV5_DP_IDCODE);
} }
@ -160,7 +161,7 @@ int adiv5_swdp_scan(uint32_t targetid)
} else { } else {
dp_targetid = target_id; dp_targetid = target_id;
} }
ADIv5_DP_t *dp = (void*)calloc(1, sizeof(*dp)); ADIv5_DP_t *dp = calloc(1, sizeof(*dp));
if (!dp) { /* calloc failed: heap exhaustion */ if (!dp) { /* calloc failed: heap exhaustion */
DEBUG_WARN("calloc: failed in %s\n", __func__); DEBUG_WARN("calloc: failed in %s\n", __func__);
continue; continue;
@ -169,26 +170,23 @@ int adiv5_swdp_scan(uint32_t targetid)
dp->idcode = idcode; dp->idcode = idcode;
dp->targetid = dp_targetid; dp->targetid = dp_targetid;
adiv5_dp_init(dp); adiv5_dp_init(dp);
} }
return target_list?1:0; return target_list ? 1U : 0U;
} }
uint32_t firmware_swdp_read(ADIv5_DP_t *dp, uint16_t addr) uint32_t firmware_swdp_read(ADIv5_DP_t *dp, uint16_t addr)
{ {
if (addr & ADIV5_APnDP) { if (addr & ADIV5_APnDP) {
adiv5_dp_low_access(dp, ADIV5_LOW_READ, addr, 0); adiv5_dp_low_access(dp, ADIV5_LOW_READ, addr, 0);
return adiv5_dp_low_access(dp, ADIV5_LOW_READ, return adiv5_dp_low_access(dp, ADIV5_LOW_READ, ADIV5_DP_RDBUFF, 0);
ADIV5_DP_RDBUFF, 0);
} else { } else {
return firmware_swdp_low_access(dp, ADIV5_LOW_READ, addr, 0); return firmware_swdp_low_access(dp, ADIV5_LOW_READ, addr, 0);
} }
} }
uint32_t firmware_swdp_error(ADIv5_DP_t *dp) uint32_t firmware_swdp_error(ADIv5_DP_t *dp)
{ {
if ((dp->fault && (dp->idcode & ADIV5_DP_DPIDR_VERSION_MASK) == ADIV5_DP_DPIDR_VERSION_DPv2) && if ((dp->fault && (dp->idcode & ADIV5_DP_DPIDR_VERSION_MASK) == ADIV5_DP_DPIDR_VERSION_DPv2) && dp->dp_low_write) {
dp->dp_low_write) {
/* On protocoll error target gets deselected. /* On protocoll error target gets deselected.
* With DP Change, another target needs selection. * With DP Change, another target needs selection.
* => Reselect with right target! */ * => Reselect with right target! */
@ -198,17 +196,16 @@ uint32_t firmware_swdp_read(ADIv5_DP_t *dp, uint16_t addr)
/* Exception here is unexpected, so do not catch */ /* Exception here is unexpected, so do not catch */
} }
uint32_t err, clr = 0; uint32_t err, clr = 0;
err = adiv5_dp_read(dp, ADIV5_DP_CTRLSTAT) & err = adiv5_dp_read(dp, ADIV5_DP_CTRLSTAT) & (ADIV5_DP_CTRLSTAT_STICKYORUN | ADIV5_DP_CTRLSTAT_STICKYCMP |
(ADIV5_DP_CTRLSTAT_STICKYORUN | ADIV5_DP_CTRLSTAT_STICKYCMP |
ADIV5_DP_CTRLSTAT_STICKYERR | ADIV5_DP_CTRLSTAT_WDATAERR); ADIV5_DP_CTRLSTAT_STICKYERR | ADIV5_DP_CTRLSTAT_WDATAERR);
if(err & ADIV5_DP_CTRLSTAT_STICKYORUN) if (err & ADIV5_DP_CTRLSTAT_STICKYORUN)
clr |= ADIV5_DP_ABORT_ORUNERRCLR; clr |= ADIV5_DP_ABORT_ORUNERRCLR;
if(err & ADIV5_DP_CTRLSTAT_STICKYCMP) if (err & ADIV5_DP_CTRLSTAT_STICKYCMP)
clr |= ADIV5_DP_ABORT_STKCMPCLR; clr |= ADIV5_DP_ABORT_STKCMPCLR;
if(err & ADIV5_DP_CTRLSTAT_STICKYERR) if (err & ADIV5_DP_CTRLSTAT_STICKYERR)
clr |= ADIV5_DP_ABORT_STKERRCLR; clr |= ADIV5_DP_ABORT_STKERRCLR;
if(err & ADIV5_DP_CTRLSTAT_WDATAERR) if (err & ADIV5_DP_CTRLSTAT_WDATAERR)
clr |= ADIV5_DP_ABORT_WDERRCLR; clr |= ADIV5_DP_ABORT_WDERRCLR;
adiv5_dp_write(dp, ADIV5_DP_ABORT, clr); adiv5_dp_write(dp, ADIV5_DP_ABORT, clr);
@ -217,8 +214,7 @@ uint32_t firmware_swdp_read(ADIv5_DP_t *dp, uint16_t addr)
return err; return err;
} }
uint32_t firmware_swdp_low_access(ADIv5_DP_t *dp, uint8_t RnW, uint32_t firmware_swdp_low_access(ADIv5_DP_t *dp, uint8_t RnW, uint16_t addr, uint32_t value)
uint16_t addr, uint32_t value)
{ {
uint32_t request = make_packet_request(RnW, addr); uint32_t request = make_packet_request(RnW, addr);
uint32_t response = 0; uint32_t response = 0;

519
src/target/cortexm.c
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File diff suppressed because it is too large Load Diff

192
src/target/cortexm.h
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@ -24,117 +24,117 @@
extern unsigned cortexm_wait_timeout; extern unsigned cortexm_wait_timeout;
/* Private peripheral bus base address */ /* Private peripheral bus base address */
#define CORTEXM_PPB_BASE 0xE0000000 #define CORTEXM_PPB_BASE 0xe0000000U
#define CORTEXM_SCS_BASE (CORTEXM_PPB_BASE + 0xE000) #define CORTEXM_SCS_BASE (CORTEXM_PPB_BASE + 0xe000U)
#define CORTEXM_CPUID (CORTEXM_SCS_BASE + 0xD00) #define CORTEXM_CPUID (CORTEXM_SCS_BASE + 0xd00U)
#define CORTEXM_AIRCR (CORTEXM_SCS_BASE + 0xD0C) #define CORTEXM_AIRCR (CORTEXM_SCS_BASE + 0xd0cU)
#define CORTEXM_CFSR (CORTEXM_SCS_BASE + 0xD28) #define CORTEXM_CFSR (CORTEXM_SCS_BASE + 0xd28U)
#define CORTEXM_HFSR (CORTEXM_SCS_BASE + 0xD2C) #define CORTEXM_HFSR (CORTEXM_SCS_BASE + 0xd2cU)
#define CORTEXM_DFSR (CORTEXM_SCS_BASE + 0xD30) #define CORTEXM_DFSR (CORTEXM_SCS_BASE + 0xd30U)
#define CORTEXM_CPACR (CORTEXM_SCS_BASE + 0xD88) #define CORTEXM_CPACR (CORTEXM_SCS_BASE + 0xd88U)
#define CORTEXM_DHCSR (CORTEXM_SCS_BASE + 0xDF0) #define CORTEXM_DHCSR (CORTEXM_SCS_BASE + 0xdf0U)
#define CORTEXM_DCRSR (CORTEXM_SCS_BASE + 0xDF4) #define CORTEXM_DCRSR (CORTEXM_SCS_BASE + 0xdf4U)
#define CORTEXM_DCRDR (CORTEXM_SCS_BASE + 0xDF8) #define CORTEXM_DCRDR (CORTEXM_SCS_BASE + 0xdf8U)
#define CORTEXM_DEMCR (CORTEXM_SCS_BASE + 0xDFC) #define CORTEXM_DEMCR (CORTEXM_SCS_BASE + 0xdfcU)
/* Cache identification */ /* Cache identification */
#define CORTEXM_CLIDR (CORTEXM_SCS_BASE + 0xD78) #define CORTEXM_CLIDR (CORTEXM_SCS_BASE + 0xd78U)
#define CORTEXM_CTR (CORTEXM_SCS_BASE + 0xD7C) #define CORTEXM_CTR (CORTEXM_SCS_BASE + 0xd7cU)
#define CORTEXM_CCSIDR (CORTEXM_SCS_BASE + 0xD80) #define CORTEXM_CCSIDR (CORTEXM_SCS_BASE + 0xd80U)
#define CORTEXM_CSSELR (CORTEXM_SCS_BASE + 0xD84) #define CORTEXM_CSSELR (CORTEXM_SCS_BASE + 0xd84U)
/* Cache maintenance operations */ /* Cache maintenance operations */
#define CORTEXM_ICIALLU (CORTEXM_SCS_BASE + 0xF50) #define CORTEXM_ICIALLU (CORTEXM_SCS_BASE + 0xf50U)
#define CORTEXM_DCCMVAC (CORTEXM_SCS_BASE + 0xF68) #define CORTEXM_DCCMVAC (CORTEXM_SCS_BASE + 0xf68U)
#define CORTEXM_DCCIMVAC (CORTEXM_SCS_BASE + 0xF70) #define CORTEXM_DCCIMVAC (CORTEXM_SCS_BASE + 0xf70U)
#define CORTEXM_FPB_BASE (CORTEXM_PPB_BASE + 0x2000) #define CORTEXM_FPB_BASE (CORTEXM_PPB_BASE + 0x2000U)
/* ARM Literature uses FP_*, we use CORTEXM_FPB_* consistently */ /* ARM Literature uses FP_*, we use CORTEXM_FPB_* consistently */
#define CORTEXM_FPB_CTRL (CORTEXM_FPB_BASE + 0x000) #define CORTEXM_FPB_CTRL (CORTEXM_FPB_BASE + 0x000U)
#define CORTEXM_FPB_REMAP (CORTEXM_FPB_BASE + 0x004) #define CORTEXM_FPB_REMAP (CORTEXM_FPB_BASE + 0x004U)
#define CORTEXM_FPB_COMP(i) (CORTEXM_FPB_BASE + 0x008 + (4*(i))) #define CORTEXM_FPB_COMP(i) (CORTEXM_FPB_BASE + 0x008U + (4U * (i)))
#define CORTEXM_DWT_BASE (CORTEXM_PPB_BASE + 0x1000) #define CORTEXM_DWT_BASE (CORTEXM_PPB_BASE + 0x1000U)
#define CORTEXM_DWT_CTRL (CORTEXM_DWT_BASE + 0x000) #define CORTEXM_DWT_CTRL (CORTEXM_DWT_BASE + 0x000U)
#define CORTEXM_DWT_COMP(i) (CORTEXM_DWT_BASE + 0x020 + (0x10*(i))) #define CORTEXM_DWT_COMP(i) (CORTEXM_DWT_BASE + 0x020U + (0x10U * (i)))
#define CORTEXM_DWT_MASK(i) (CORTEXM_DWT_BASE + 0x024 + (0x10*(i))) #define CORTEXM_DWT_MASK(i) (CORTEXM_DWT_BASE + 0x024U + (0x10U * (i)))
#define CORTEXM_DWT_FUNC(i) (CORTEXM_DWT_BASE + 0x028 + (0x10*(i))) #define CORTEXM_DWT_FUNC(i) (CORTEXM_DWT_BASE + 0x028U + (0x10U * (i)))
/* Application Interrupt and Reset Control Register (AIRCR) */ /* Application Interrupt and Reset Control Register (AIRCR) */
#define CORTEXM_AIRCR_VECTKEY (0x05FA << 16) #define CORTEXM_AIRCR_VECTKEY (0x05faU << 16U)
/* Bits 31:16 - Read as VECTKETSTAT, 0xFA05 */ /* Bits 31:16 - Read as VECTKETSTAT, 0xFA05 */
#define CORTEXM_AIRCR_ENDIANESS (1 << 15) #define CORTEXM_AIRCR_ENDIANESS (1U << 15U)
/* Bits 15:11 - Unused, reserved */ /* Bits 15:11 - Unused, reserved */
#define CORTEXM_AIRCR_PRIGROUP (7 << 8) #define CORTEXM_AIRCR_PRIGROUP (7U << 8U)
/* Bits 7:3 - Unused, reserved */ /* Bits 7:3 - Unused, reserved */
#define CORTEXM_AIRCR_SYSRESETREQ (1 << 2) #define CORTEXM_AIRCR_SYSRESETREQ (1U << 2U)
#define CORTEXM_AIRCR_VECTCLRACTIVE (1 << 1) #define CORTEXM_AIRCR_VECTCLRACTIVE (1U << 1U)
#define CORTEXM_AIRCR_VECTRESET (1 << 0) #define CORTEXM_AIRCR_VECTRESET (1U << 0U)
/* HardFault Status Register (HFSR) */ /* HardFault Status Register (HFSR) */
#define CORTEXM_HFSR_DEBUGEVT (1 << 31) #define CORTEXM_HFSR_DEBUGEVT (1U << 31U)
#define CORTEXM_HFSR_FORCED (1 << 30) #define CORTEXM_HFSR_FORCED (1U << 30U)
/* Bits 29:2 - Not specified */ /* Bits 29:2 - Not specified */
#define CORTEXM_HFSR_VECTTBL (1 << 1) #define CORTEXM_HFSR_VECTTBL (1U << 1U)
/* Bits 0 - Reserved */ /* Bits 0 - Reserved */
/* Debug Fault Status Register (DFSR) */ /* Debug Fault Status Register (DFSR) */
/* Bits 31:5 - Reserved */ /* Bits 31:5 - Reserved */
#define CORTEXM_DFSR_RESETALL 0x1F #define CORTEXM_DFSR_RESETALL 0x1fU
#define CORTEXM_DFSR_EXTERNAL (1 << 4) #define CORTEXM_DFSR_EXTERNAL (1U << 4U)
#define CORTEXM_DFSR_VCATCH (1 << 3) #define CORTEXM_DFSR_VCATCH (1U << 3U)
#define CORTEXM_DFSR_DWTTRAP (1 << 2) #define CORTEXM_DFSR_DWTTRAP (1U << 2U)
#define CORTEXM_DFSR_BKPT (1 << 1) #define CORTEXM_DFSR_BKPT (1U << 1U)
#define CORTEXM_DFSR_HALTED (1 << 0) #define CORTEXM_DFSR_HALTED (1U << 0U)
/* Debug Halting Control and Status Register (DHCSR) */ /* Debug Halting Control and Status Register (DHCSR) */
/* This key must be written to bits 31:16 for write to take effect */ /* This key must be written to bits 31:16 for write to take effect */
#define CORTEXM_DHCSR_DBGKEY 0xA05F0000 #define CORTEXM_DHCSR_DBGKEY 0xa05f0000U
/* Bits 31:26 - Reserved */ /* Bits 31:26 - Reserved */
#define CORTEXM_DHCSR_S_RESET_ST (1 << 25) #define CORTEXM_DHCSR_S_RESET_ST (1U << 25U)
#define CORTEXM_DHCSR_S_RETIRE_ST (1 << 24) #define CORTEXM_DHCSR_S_RETIRE_ST (1U << 24U)
/* Bits 23:20 - Reserved */ /* Bits 23:20 - Reserved */
#define CORTEXM_DHCSR_S_LOCKUP (1 << 19) #define CORTEXM_DHCSR_S_LOCKUP (1U << 19U)
#define CORTEXM_DHCSR_S_SLEEP (1 << 18) #define CORTEXM_DHCSR_S_SLEEP (1U << 18U)
#define CORTEXM_DHCSR_S_HALT (1 << 17) #define CORTEXM_DHCSR_S_HALT (1U << 17U)
#define CORTEXM_DHCSR_S_REGRDY (1 << 16) #define CORTEXM_DHCSR_S_REGRDY (1U << 16U)
/* Bits 15:6 - Reserved */ /* Bits 15:6 - Reserved */
#define CORTEXM_DHCSR_C_SNAPSTALL (1 << 5) /* v7m only */ #define CORTEXM_DHCSR_C_SNAPSTALL (1U << 5U) /* v7m only */
/* Bit 4 - Reserved */ /* Bit 4 - Reserved */
#define CORTEXM_DHCSR_C_MASKINTS (1 << 3) #define CORTEXM_DHCSR_C_MASKINTS (1U << 3U)
#define CORTEXM_DHCSR_C_STEP (1 << 2) #define CORTEXM_DHCSR_C_STEP (1U << 2U)
#define CORTEXM_DHCSR_C_HALT (1 << 1) #define CORTEXM_DHCSR_C_HALT (1U << 1U)
#define CORTEXM_DHCSR_C_DEBUGEN (1 << 0) #define CORTEXM_DHCSR_C_DEBUGEN (1U << 0U)
/* Debug Core Register Selector Register (DCRSR) */ /* Debug Core Register Selector Register (DCRSR) */
#define CORTEXM_DCRSR_REGWnR 0x00010000 #define CORTEXM_DCRSR_REGWnR 0x00010000
#define CORTEXM_DCRSR_REGSEL_MASK 0x0000001F #define CORTEXM_DCRSR_REGSEL_MASK 0x0000001f
#define CORTEXM_DCRSR_REGSEL_XPSR 0x00000010 #define CORTEXM_DCRSR_REGSEL_XPSR 0x00000010
#define CORTEXM_DCRSR_REGSEL_MSP 0x00000011 #define CORTEXM_DCRSR_REGSEL_MSP 0x00000011
#define CORTEXM_DCRSR_REGSEL_PSP 0x00000012 #define CORTEXM_DCRSR_REGSEL_PSP 0x00000012
/* Debug Exception and Monitor Control Register (DEMCR) */ /* Debug Exception and Monitor Control Register (DEMCR) */
/* Bits 31:25 - Reserved */ /* Bits 31:25 - Reserved */
#define CORTEXM_DEMCR_TRCENA (1 << 24) #define CORTEXM_DEMCR_TRCENA (1U << 24U)
/* Bits 23:20 - Reserved */ /* Bits 23:20 - Reserved */
#define CORTEXM_DEMCR_MON_REQ (1 << 19) /* v7m only */ #define CORTEXM_DEMCR_MON_REQ (1U << 19U) /* v7m only */
#define CORTEXM_DEMCR_MON_STEP (1 << 18) /* v7m only */ #define CORTEXM_DEMCR_MON_STEP (1U << 18U) /* v7m only */
#define CORTEXM_DEMCR_VC_MON_PEND (1 << 17) /* v7m only */ #define CORTEXM_DEMCR_VC_MON_PEND (1U << 17U) /* v7m only */
#define CORTEXM_DEMCR_VC_MON_EN (1 << 16) /* v7m only */ #define CORTEXM_DEMCR_VC_MON_EN (1U << 16U) /* v7m only */
/* Bits 15:11 - Reserved */ /* Bits 15:11 - Reserved */
#define CORTEXM_DEMCR_VC_HARDERR (1 << 10) #define CORTEXM_DEMCR_VC_HARDERR (1U << 10U)
#define CORTEXM_DEMCR_VC_INTERR (1 << 9) /* v7m only */ #define CORTEXM_DEMCR_VC_INTERR (1U << 9U) /* v7m only */
#define CORTEXM_DEMCR_VC_BUSERR (1 << 8) /* v7m only */ #define CORTEXM_DEMCR_VC_BUSERR (1U << 8U) /* v7m only */
#define CORTEXM_DEMCR_VC_STATERR (1 << 7) /* v7m only */ #define CORTEXM_DEMCR_VC_STATERR (1U << 7U) /* v7m only */
#define CORTEXM_DEMCR_VC_CHKERR (1 << 6) /* v7m only */ #define CORTEXM_DEMCR_VC_CHKERR (1U << 6U) /* v7m only */
#define CORTEXM_DEMCR_VC_NOCPERR (1 << 5) /* v7m only */ #define CORTEXM_DEMCR_VC_NOCPERR (1U << 5U) /* v7m only */
#define CORTEXM_DEMCR_VC_MMERR (1 << 4) /* v7m only */ #define CORTEXM_DEMCR_VC_MMERR (1U << 4U) /* v7m only */
/* Bits 3:1 - Reserved */ /* Bits 3:1 - Reserved */
#define CORTEXM_DEMCR_VC_CORERESET (1 << 0) #define CORTEXM_DEMCR_VC_CORERESET (1U << 0U)
/* Flash Patch and Breakpoint Control Register (FP_CTRL) */ /* Flash Patch and Breakpoint Control Register (FP_CTRL) */
/* Bits 32:15 - Reserved */ /* Bits 32:15 - Reserved */
@ -142,35 +142,35 @@ extern unsigned cortexm_wait_timeout;
/* Bits 11:8 - NUM_LIT */ /* v7m only */ /* Bits 11:8 - NUM_LIT */ /* v7m only */
/* Bits 7:4 - NUM_CODE1 */ /* Bits 7:4 - NUM_CODE1 */
/* Bits 3:2 - Unspecified */ /* Bits 3:2 - Unspecified */
#define CORTEXM_FPB_CTRL_KEY (1 << 1) #define CORTEXM_FPB_CTRL_KEY (1U << 1U)
#define CORTEXM_FPB_CTRL_ENABLE (1 << 0) #define CORTEXM_FPB_CTRL_ENABLE (1U << 0U)
/* Data Watchpoint and Trace Mask Register (DWT_MASKx) /* Data Watchpoint and Trace Mask Register (DWT_MASKx)
* The value here is the number of address bits we mask out */ * The value here is the number of address bits we mask out */
#define CORTEXM_DWT_MASK_BYTE (0) #define CORTEXM_DWT_MASK_BYTE (0U)
#define CORTEXM_DWT_MASK_HALFWORD (1) #define CORTEXM_DWT_MASK_HALFWORD (1U)
#define CORTEXM_DWT_MASK_WORD (2) #define CORTEXM_DWT_MASK_WORD (2U)
#define CORTEXM_DWT_MASK_DWORD (3) #define CORTEXM_DWT_MASK_DWORD (3U)
/* Data Watchpoint and Trace Function Register (DWT_FUNCTIONx) */ /* Data Watchpoint and Trace Function Register (DWT_FUNCTIONx) */
#define CORTEXM_DWT_FUNC_MATCHED (1 << 24) #define CORTEXM_DWT_FUNC_MATCHED (1U << 24U)
#define CORTEXM_DWT_FUNC_DATAVSIZE_WORD (2 << 10) /* v7m only */ #define CORTEXM_DWT_FUNC_DATAVSIZE_WORD (2U << 10U) /* v7m only */
#define CORTEXM_DWT_FUNC_FUNC_READ (5 << 0) #define CORTEXM_DWT_FUNC_FUNC_READ (5U << 0U)
#define CORTEXM_DWT_FUNC_FUNC_WRITE (6 << 0) #define CORTEXM_DWT_FUNC_FUNC_WRITE (6U << 0U)
#define CORTEXM_DWT_FUNC_FUNC_ACCESS (7 << 0) #define CORTEXM_DWT_FUNC_FUNC_ACCESS (7U << 0U)
#define REG_SP 13 #define REG_SP 13U
#define REG_LR 14 #define REG_LR 14U
#define REG_PC 15 #define REG_PC 15U
#define REG_XPSR 16 #define REG_XPSR 16U
#define REG_MSP 17 #define REG_MSP 17U
#define REG_PSP 18 #define REG_PSP 18U
#define REG_SPECIAL 19 #define REG_SPECIAL 19U
#define ARM_THUMB_BREAKPOINT 0xBE00 #define ARM_THUMB_BREAKPOINT 0xbe00U
#define CORTEXM_XPSR_THUMB (1 << 24) #define CORTEXM_XPSR_THUMB (1U << 24U)
#define CORTEXM_TOPT_INHIBIT_NRST (1 << 2) #define CORTEXM_TOPT_INHIBIT_NRST (1U << 2U)
enum cortexm_types { enum cortexm_types {
CORTEX_M0 = 0xc200, CORTEX_M0 = 0xc200,
@ -181,17 +181,15 @@ enum cortexm_types {
CORTEX_M23 = 0xd200, CORTEX_M23 = 0xd200,
CORTEX_M33 = 0xd210, CORTEX_M33 = 0xd210,
}; };
#define CPUID_PARTNO_MASK 0xfff0 #define CPUID_PARTNO_MASK 0xfff0U
#define CPUID_REVISION_MASK 0x00f00000 #define CPUID_REVISION_MASK 0x00f00000U
#define CPUID_PATCH_MASK 0xf #define CPUID_PATCH_MASK 0xfU
ADIv5_AP_t *cortexm_ap(target *t); ADIv5_AP_t *cortexm_ap(target *t);
bool cortexm_attach(target *t); bool cortexm_attach(target *t);
void cortexm_detach(target *t); void cortexm_detach(target *t);
int cortexm_run_stub(target *t, uint32_t loadaddr, int cortexm_run_stub(target *t, uint32_t loadaddr, uint32_t r0, uint32_t r1, uint32_t r2, uint32_t r3);
uint32_t r0, uint32_t r1, uint32_t r2, uint32_t r3); int cortexm_mem_write_sized(target *t, target_addr dest, const void *src, size_t len, enum align align);
int cortexm_mem_write_sized(
target *t, target_addr dest, const void *src, size_t len, enum align align);
#endif #endif