misc: code format & cleanup
This commit is contained in:
Rafael Silva
Rachel Mant
parent
460bd1e477
commit
73f3910f62
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@ -494,7 +494,8 @@ static void adiv5_component_probe(ADIv5_AP_t *ap, uint32_t addr, const size_t re
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* see 'JEP-106 code list' for context, here we are aliasing codes that are non compliant with the
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* JEP-106 standard to their expected codes, this is later used to determine the correct probe function.
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*/
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DEBUG_WARN("Patching Designer code 0x%03" PRIx16 " -> 0x%03" PRIx16 "\n", designer_code, JEP106_MANUFACTURER_STM);
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DEBUG_WARN(
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"Patching Designer code 0x%03" PRIx16 " -> 0x%03" PRIx16 "\n", designer_code, JEP106_MANUFACTURER_STM);
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designer_code = JEP106_MANUFACTURER_STM;
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}
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} else {
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@ -32,15 +32,17 @@
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unsigned int make_packet_request(uint8_t RnW, uint16_t addr)
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{
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bool APnDP = addr & ADIV5_APnDP;
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addr &= 0xff;
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unsigned int request = 0x81; /* Park and Startbit */
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if(APnDP) request ^= 0x22;
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if(RnW) request ^= 0x24;
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addr &= 0xffU;
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unsigned int request = 0x81U; /* Park and Startbit */
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if (APnDP)
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request ^= 0x22U;
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if (RnW)
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request ^= 0x24U;
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addr &= 0xC;
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request |= (addr << 1) & 0x18;
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if((addr == 4) || (addr == 8))
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request ^= 0x20;
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addr &= 0xcU;
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request |= (addr << 1U) & 0x18U;
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if (addr == 4U || addr == 8U)
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request ^= 0x20U;
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return request;
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}
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@ -48,13 +50,13 @@ unsigned int make_packet_request(uint8_t RnW, uint16_t addr)
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static void dp_line_reset(ADIv5_DP_t *dp)
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{
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dp->seq_out(0xFFFFFFFF, 32);
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dp->seq_out(0x0FFFFFFF, 32);
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dp->seq_out(0xFFFFFFFFU, 32U);
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dp->seq_out(0x0FFFFFFFU, 32U);
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}
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bool firmware_dp_low_write(ADIv5_DP_t *dp, uint16_t addr, const uint32_t data)
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{
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unsigned int request = make_packet_request(ADIV5_LOW_WRITE, addr & 0xf);
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unsigned int request = make_packet_request(ADIV5_LOW_WRITE, addr & 0xfU);
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dp->seq_out(request, 8);
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int res = dp->seq_in(3);
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dp->seq_out_parity(data, 32);
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@ -143,14 +145,13 @@ int adiv5_swdp_scan(uint32_t targetid)
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} else {
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target_id = targetid;
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}
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volatile int nr_dps = (scan_multidrop) ? 16: 1;
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const volatile size_t nr_dps = (scan_multidrop) ? 16U : 1U;
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volatile uint32_t dp_targetid;
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for (volatile int i = 0; i < nr_dps; i++) {
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for (volatile size_t i = 0; i < nr_dps; i++) {
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if (scan_multidrop) {
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dp_line_reset(initial_dp);
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dp_targetid = (i << 28) | (target_id & 0x0fffffff);
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initial_dp->dp_low_write(initial_dp, ADIV5_DP_TARGETSEL,
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dp_targetid);
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dp_targetid = (i << 28U) | (target_id & 0x0fffffffU);
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initial_dp->dp_low_write(initial_dp, ADIV5_DP_TARGETSEL, dp_targetid);
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TRY_CATCH (e, EXCEPTION_ALL) {
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idcode = initial_dp->dp_read(initial_dp, ADIV5_DP_IDCODE);
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}
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@ -160,7 +161,7 @@ int adiv5_swdp_scan(uint32_t targetid)
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} else {
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dp_targetid = target_id;
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}
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ADIv5_DP_t *dp = (void*)calloc(1, sizeof(*dp));
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ADIv5_DP_t *dp = calloc(1, sizeof(*dp));
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if (!dp) { /* calloc failed: heap exhaustion */
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DEBUG_WARN("calloc: failed in %s\n", __func__);
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continue;
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@ -169,17 +170,15 @@ int adiv5_swdp_scan(uint32_t targetid)
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dp->idcode = idcode;
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dp->targetid = dp_targetid;
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adiv5_dp_init(dp);
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}
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return target_list?1:0;
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return target_list ? 1U : 0U;
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}
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uint32_t firmware_swdp_read(ADIv5_DP_t *dp, uint16_t addr)
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{
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if (addr & ADIV5_APnDP) {
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adiv5_dp_low_access(dp, ADIV5_LOW_READ, addr, 0);
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return adiv5_dp_low_access(dp, ADIV5_LOW_READ,
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ADIV5_DP_RDBUFF, 0);
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return adiv5_dp_low_access(dp, ADIV5_LOW_READ, ADIV5_DP_RDBUFF, 0);
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} else {
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return firmware_swdp_low_access(dp, ADIV5_LOW_READ, addr, 0);
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}
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@ -187,8 +186,7 @@ uint32_t firmware_swdp_read(ADIv5_DP_t *dp, uint16_t addr)
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uint32_t firmware_swdp_error(ADIv5_DP_t *dp)
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{
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if ((dp->fault && (dp->idcode & ADIV5_DP_DPIDR_VERSION_MASK) == ADIV5_DP_DPIDR_VERSION_DPv2) &&
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dp->dp_low_write) {
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if ((dp->fault && (dp->idcode & ADIV5_DP_DPIDR_VERSION_MASK) == ADIV5_DP_DPIDR_VERSION_DPv2) && dp->dp_low_write) {
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/* On protocoll error target gets deselected.
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* With DP Change, another target needs selection.
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* => Reselect with right target! */
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@ -198,8 +196,7 @@ uint32_t firmware_swdp_read(ADIv5_DP_t *dp, uint16_t addr)
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/* Exception here is unexpected, so do not catch */
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}
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uint32_t err, clr = 0;
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err = adiv5_dp_read(dp, ADIV5_DP_CTRLSTAT) &
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(ADIV5_DP_CTRLSTAT_STICKYORUN | ADIV5_DP_CTRLSTAT_STICKYCMP |
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err = adiv5_dp_read(dp, ADIV5_DP_CTRLSTAT) & (ADIV5_DP_CTRLSTAT_STICKYORUN | ADIV5_DP_CTRLSTAT_STICKYCMP |
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ADIV5_DP_CTRLSTAT_STICKYERR | ADIV5_DP_CTRLSTAT_WDATAERR);
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if (err & ADIV5_DP_CTRLSTAT_STICKYORUN)
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@ -217,8 +214,7 @@ uint32_t firmware_swdp_read(ADIv5_DP_t *dp, uint16_t addr)
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return err;
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}
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uint32_t firmware_swdp_low_access(ADIv5_DP_t *dp, uint8_t RnW,
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uint16_t addr, uint32_t value)
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uint32_t firmware_swdp_low_access(ADIv5_DP_t *dp, uint8_t RnW, uint16_t addr, uint32_t value)
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{
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uint32_t request = make_packet_request(RnW, addr);
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uint32_t response = 0;
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@ -68,12 +68,12 @@ const struct command_s cortexm_cmd_list[] = {
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#ifdef PLATFORM_HAS_USBUART
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{"redirect_stdout", (cmd_handler)cortexm_redirect_stdout, "Redirect semihosting stdout to USB UART"},
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#endif
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{NULL, NULL, NULL}
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{NULL, NULL, NULL},
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};
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/* target options recognised by the Cortex-M target */
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#define TOPT_FLAVOUR_V6M (1<<0) /* if not set, target is assumed to be v7m */
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#define TOPT_FLAVOUR_V7MF (1<<1) /* if set, floating-point enabled. */
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#define TOPT_FLAVOUR_V6M (1U << 0U) /* if not set, target is assumed to be v7m */
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#define TOPT_FLAVOUR_V7MF (1U << 1U) /* if set, floating-point enabled. */
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static void cortexm_regs_read(target *t, void *data);
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static void cortexm_regs_write(target *t, const void *data);
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@ -91,8 +91,8 @@ static int cortexm_breakwatch_set(target *t, struct breakwatch *);
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static int cortexm_breakwatch_clear(target *t, struct breakwatch *);
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static target_addr cortexm_check_watch(target *t);
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#define CORTEXM_MAX_WATCHPOINTS 4 /* architecture says up to 15, no implementation has > 4 */
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#define CORTEXM_MAX_BREAKPOINTS 8 /* architecture says up to 127, no implementation has > 8 */
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#define CORTEXM_MAX_WATCHPOINTS 4U /* architecture says up to 15, no implementation has > 4 */
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#define CORTEXM_MAX_BREAKPOINTS 8U /* architecture says up to 127, no implementation has > 8 */
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static int cortexm_hostio_request(target *t);
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@ -133,6 +133,7 @@ static const uint32_t regnum_cortex_mf[] = {
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0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f, /* s24-s31 */
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};
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/* clang-format off */
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static const char tdesc_cortex_m[] =
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"<?xml version=\"1.0\"?>"
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"<!DOCTYPE target SYSTEM \"gdb-target.dtd\">"
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@ -215,6 +216,7 @@ static const char tdesc_cortex_mf[] =
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" <reg name=\"d15\" bitsize=\"64\" type=\"float\"/>"
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" </feature>"
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"</target>";
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/* clang-format on */
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ADIv5_AP_t *cortexm_ap(target *t)
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{
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@ -320,8 +322,7 @@ bool cortexm_probe(ADIv5_AP_t *ap)
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break;
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case CORTEX_M7:
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t->core = "M7";
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if (((t->cpuid & CPUID_REVISION_MASK) == 0) &&
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(t->cpuid & CPUID_PATCH_MASK) < 2) {
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if (((t->cpuid & CPUID_REVISION_MASK) == 0) && (t->cpuid & CPUID_PATCH_MASK) < 2) {
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DEBUG_WARN("Silicon bug: Single stepping will enter pending "
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"exception handler with this M7 core revision!\n");
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}
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@ -333,14 +334,11 @@ bool cortexm_probe(ADIv5_AP_t *ap)
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t->core = "M0";
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break;
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default:
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if (ap->designer_code != JEP106_MANUFACTURER_ATMEL) /* Protected Atmel device?*/{
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if (ap->designer_code != JEP106_MANUFACTURER_ATMEL) /* Protected Atmel device?*/
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DEBUG_WARN("Unexpected CortexM CPUID partno %04" PRIx32 "\n", cpuid_partno);
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}
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}
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DEBUG_INFO("CPUID 0x%08" PRIx32 " (%s var %" PRIx32 " rev %" PRIx32 ")\n",
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t->cpuid,
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t->core, (t->cpuid & CPUID_REVISION_MASK) >> 20,
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t->cpuid & CPUID_PATCH_MASK);
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DEBUG_INFO("CPUID 0x%08" PRIx32 " (%s var %" PRIx32 " rev %" PRIx32 ")\n", t->cpuid, t->core,
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(t->cpuid & CPUID_REVISION_MASK) >> 20, t->cpuid & CPUID_PATCH_MASK);
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t->attach = cortexm_attach;
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t->detach = cortexm_detach;
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@ -374,8 +372,7 @@ bool cortexm_probe(ADIv5_AP_t *ap)
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}
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/* Default vectors to catch */
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priv->demcr = CORTEXM_DEMCR_TRCENA | CORTEXM_DEMCR_VC_HARDERR |
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CORTEXM_DEMCR_VC_CORERESET;
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priv->demcr = CORTEXM_DEMCR_TRCENA | CORTEXM_DEMCR_VC_HARDERR | CORTEXM_DEMCR_VC_CORERESET;
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/* Check cache type */
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uint32_t ctr = target_mem_read32(t, CORTEXM_CTR);
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@ -450,9 +447,11 @@ bool cortexm_probe(ADIv5_AP_t *ap)
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if (ap->designer_code != JEP106_MANUFACTURER_ARM) {
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/* Report unexpected designers */
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#if PC_HOSTED == 0
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gdb_outf("Please report probed device with Designer code 0x%3x and Partno 0x%3x\n", ap->designer_code, ap->ap_partno);
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gdb_outf("Please report probed device with Designer code 0x%3x and Partno 0x%3x\n", ap->designer_code,
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ap->ap_partno);
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#else
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DEBUG_WARN("Please report probed device with Designer code 0x%3x and Partno 0x%3x\n", ap->designer_code, ap->ap_partno);
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DEBUG_WARN("Please report probed device with Designer code 0x%3x and Partno 0x%3x\n", ap->designer_code,
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ap->ap_partno);
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#endif
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}
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if (ap->ap_partno == 0x4c0) { /* Cortex-M0+ ROM */
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@ -577,13 +576,18 @@ void cortexm_detach(target *t)
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target_mem_write32(t, CORTEXM_DHCSR, CORTEXM_DHCSR_DBGKEY);
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}
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enum { DB_DHCSR, DB_DCRSR, DB_DCRDR, DB_DEMCR };
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enum {
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DB_DHCSR,
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DB_DCRSR,
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DB_DCRDR,
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DB_DEMCR
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};
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static void cortexm_regs_read(target *t, void *data)
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{
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uint32_t *regs = data;
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ADIv5_AP_t *ap = cortexm_ap(t);
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unsigned i;
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size_t i;
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#if PC_HOSTED == 1
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if ((ap->dp->ap_reg_read) && (ap->dp->ap_regs_read)) {
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uint32_t base_regs[21];
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@ -593,18 +597,15 @@ static void cortexm_regs_read(target *t, void *data)
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if (t->target_options & TOPT_FLAVOUR_V7MF)
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for (i = 0; i < sizeof(regnum_cortex_mf) / 4; i++)
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*regs++ = ap->dp->ap_reg_read(ap, regnum_cortex_mf[i]);
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}
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#else
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if (0) {}
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} else
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#endif
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else {
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{
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/* FIXME: Describe what's really going on here */
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adiv5_ap_write(ap, ADIV5_AP_CSW, ap->csw | ADIV5_AP_CSW_SIZE_WORD);
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/* Map the banked data registers (0x10-0x1c) to the
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* debug registers DHCSR, DCRSR, DCRDR and DEMCR respectively */
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adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, ADIV5_AP_TAR,
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CORTEXM_DHCSR);
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adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, ADIV5_AP_TAR, CORTEXM_DHCSR);
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/* Walk the regnum_cortex_m array, reading the registers it
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* calls out. */
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@ -612,15 +613,12 @@ static void cortexm_regs_read(target *t, void *data)
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/* Required to switch banks */
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*regs++ = adiv5_dp_read(ap->dp, ADIV5_AP_DB(DB_DCRDR));
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for (i = 1; i < sizeof(regnum_cortex_m) / 4; i++) {
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adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, ADIV5_AP_DB(DB_DCRSR),
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regnum_cortex_m[i]);
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adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, ADIV5_AP_DB(DB_DCRSR), regnum_cortex_m[i]);
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*regs++ = adiv5_dp_read(ap->dp, ADIV5_AP_DB(DB_DCRDR));
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}
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if (t->target_options & TOPT_FLAVOUR_V7MF)
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for (i = 0; i < sizeof(regnum_cortex_mf) / 4; i++) {
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adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE,
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ADIV5_AP_DB(DB_DCRSR),
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regnum_cortex_mf[i]);
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adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, ADIV5_AP_DB(DB_DCRSR), regnum_cortex_mf[i]);
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*regs++ = adiv5_dp_read(ap->dp, ADIV5_AP_DB(DB_DCRDR));
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}
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}
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@ -641,45 +639,35 @@ static void cortexm_regs_write(target *t, const void *data)
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ap->dp->ap_reg_write(ap, regnum_cortex_mf[z], *regs);
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regs++;
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}
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}
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#else
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if (0) {}
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} else
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#endif
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else {
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unsigned i;
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{
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size_t i;
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/* FIXME: Describe what's really going on here */
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adiv5_ap_write(ap, ADIV5_AP_CSW, ap->csw | ADIV5_AP_CSW_SIZE_WORD);
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/* Map the banked data registers (0x10-0x1c) to the
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* debug registers DHCSR, DCRSR, DCRDR and DEMCR respectively */
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adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, ADIV5_AP_TAR,
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CORTEXM_DHCSR);
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adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, ADIV5_AP_TAR, CORTEXM_DHCSR);
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/* Walk the regnum_cortex_m array, writing the registers it
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* calls out. */
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adiv5_ap_write(ap, ADIV5_AP_DB(DB_DCRDR), *regs++);
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/* Required to switch banks */
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adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, ADIV5_AP_DB(DB_DCRSR),
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0x10000 | regnum_cortex_m[0]);
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adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, ADIV5_AP_DB(DB_DCRSR), 0x10000 | regnum_cortex_m[0]);
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for (i = 1; i < sizeof(regnum_cortex_m) / 4; i++) {
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adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE,
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ADIV5_AP_DB(DB_DCRDR), *regs++);
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adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, ADIV5_AP_DB(DB_DCRSR),
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0x10000 | regnum_cortex_m[i]);
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adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, ADIV5_AP_DB(DB_DCRDR), *regs++);
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adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, ADIV5_AP_DB(DB_DCRSR), 0x10000 | regnum_cortex_m[i]);
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}
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if (t->target_options & TOPT_FLAVOUR_V7MF)
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for (i = 0; i < sizeof(regnum_cortex_mf) / 4; i++) {
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adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE,
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ADIV5_AP_DB(DB_DCRDR), *regs++);
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adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE,
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ADIV5_AP_DB(DB_DCRSR),
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0x10000 | regnum_cortex_mf[i]);
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adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, ADIV5_AP_DB(DB_DCRDR), *regs++);
|
||||
adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, ADIV5_AP_DB(DB_DCRSR), 0x10000 | regnum_cortex_mf[i]);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
int cortexm_mem_write_sized(
|
||||
target *t, target_addr dest, const void *src, size_t len, enum align align)
|
||||
int cortexm_mem_write_sized(target *t, target_addr dest, const void *src, size_t len, enum align align)
|
||||
{
|
||||
cortexm_cache_clean(t, dest, len, true);
|
||||
adiv5_mem_write_sized(cortexm_ap(t), dest, src, len, align);
|
||||
|
|
@ -688,12 +676,11 @@ int cortexm_mem_write_sized(
|
|||
|
||||
static int dcrsr_regnum(target *t, unsigned reg)
|
||||
{
|
||||
if (reg < sizeof(regnum_cortex_m) / 4) {
|
||||
if (reg < sizeof(regnum_cortex_m) / 4U) {
|
||||
return regnum_cortex_m[reg];
|
||||
} else if ((t->target_options & TOPT_FLAVOUR_V7MF) &&
|
||||
(reg < (sizeof(regnum_cortex_m) +
|
||||
sizeof(regnum_cortex_mf)) / 4)) {
|
||||
return regnum_cortex_mf[reg - sizeof(regnum_cortex_m)/4];
|
||||
(reg < (sizeof(regnum_cortex_m) + sizeof(regnum_cortex_mf)) / 4)) {
|
||||
return regnum_cortex_mf[reg - sizeof(regnum_cortex_m) / 4U];
|
||||
} else {
|
||||
return -1;
|
||||
}
|
||||
|
|
@ -714,8 +701,7 @@ static ssize_t cortexm_reg_write(target *t, int reg, const void *data, size_t ma
|
|||
return -1;
|
||||
const uint32_t *r = data;
|
||||
target_mem_write32(t, CORTEXM_DCRDR, *r);
|
||||
target_mem_write32(t, CORTEXM_DCRSR, CORTEXM_DCRSR_REGWnR |
|
||||
dcrsr_regnum(t, reg));
|
||||
target_mem_write32(t, CORTEXM_DCRSR, CORTEXM_DCRSR_REGWnR | dcrsr_regnum(t, reg));
|
||||
return 4;
|
||||
}
|
||||
|
||||
|
|
@ -737,7 +723,7 @@ static void cortexm_reset(target *t)
|
|||
{
|
||||
/* Read DHCSR here to clear S_RESET_ST bit before reset */
|
||||
target_mem_read32(t, CORTEXM_DHCSR);
|
||||
platform_timeout to;
|
||||
platform_timeout reset_timeout;
|
||||
if ((t->target_options & CORTEXM_TOPT_INHIBIT_NRST) == 0) {
|
||||
platform_nrst_set_val(true);
|
||||
platform_nrst_set_val(false);
|
||||
|
|
@ -750,19 +736,19 @@ static void cortexm_reset(target *t)
|
|||
/* No reset seen yet, maybe as nRST is not connected, or device has
|
||||
* CORTEXM_TOPT_INHIBIT_NRST set.
|
||||
* Trigger reset by AIRCR.*/
|
||||
target_mem_write32(t, CORTEXM_AIRCR,
|
||||
CORTEXM_AIRCR_VECTKEY | CORTEXM_AIRCR_SYSRESETREQ);
|
||||
target_mem_write32(t, CORTEXM_AIRCR, CORTEXM_AIRCR_VECTKEY | CORTEXM_AIRCR_SYSRESETREQ);
|
||||
}
|
||||
/* If target needs to do something extra (see Atmel SAM4L for example) */
|
||||
if (t->extended_reset != NULL) {
|
||||
t->extended_reset(t);
|
||||
}
|
||||
/* Wait for CORTEXM_DHCSR_S_RESET_ST to read 0, meaning reset released.*/
|
||||
platform_timeout_set(&to, 1000);
|
||||
platform_timeout_set(&reset_timeout, 1000);
|
||||
while ((target_mem_read32(t, CORTEXM_DHCSR) & CORTEXM_DHCSR_S_RESET_ST) &&
|
||||
!platform_timeout_is_expired(&to));
|
||||
!platform_timeout_is_expired(&reset_timeout))
|
||||
continue;
|
||||
#if defined(PLATFORM_HAS_DEBUG)
|
||||
if (platform_timeout_is_expired(&to))
|
||||
if (platform_timeout_is_expired(&reset_timeout))
|
||||
DEBUG_WARN("Reset seem to be stuck low!\n");
|
||||
#endif
|
||||
/* 10 ms delay to ensure that things such as the STM32 HSI clock
|
||||
|
|
@ -778,9 +764,7 @@ static void cortexm_halt_request(target *t)
|
|||
{
|
||||
volatile struct exception e;
|
||||
TRY_CATCH (e, EXCEPTION_TIMEOUT) {
|
||||
target_mem_write32(t, CORTEXM_DHCSR, CORTEXM_DHCSR_DBGKEY |
|
||||
CORTEXM_DHCSR_C_HALT |
|
||||
CORTEXM_DHCSR_C_DEBUGEN);
|
||||
target_mem_write32(t, CORTEXM_DHCSR, CORTEXM_DHCSR_DBGKEY | CORTEXM_DHCSR_C_HALT | CORTEXM_DHCSR_C_DEBUGEN);
|
||||
}
|
||||
if (e.type) {
|
||||
tc_printf(t, "Timeout sending interrupt, is target in WFI?\n");
|
||||
|
|
@ -826,7 +810,7 @@ static enum target_halt_reason cortexm_halt_poll(target *t, target_addr *watch)
|
|||
uint32_t pc = cortexm_pc_read(t);
|
||||
uint16_t bkpt_instr;
|
||||
bkpt_instr = target_mem_read16(t, pc);
|
||||
if (bkpt_instr == 0xBEAB) {
|
||||
if (bkpt_instr == 0xbeabU) {
|
||||
if (cortexm_hostio_request(t)) {
|
||||
return TARGET_HALT_REQUEST;
|
||||
} else {
|
||||
|
|
@ -866,7 +850,7 @@ static void cortexm_halt_resume(target *t, bool step)
|
|||
|
||||
if (priv->on_bkpt) {
|
||||
uint32_t pc = cortexm_pc_read(t);
|
||||
if ((target_mem_read16(t, pc) & 0xFF00) == 0xBE00)
|
||||
if ((target_mem_read16(t, pc) & 0xff00U) == 0xbe00U)
|
||||
cortexm_pc_write(t, pc + 2);
|
||||
}
|
||||
|
||||
|
|
@ -893,8 +877,8 @@ static int cortexm_fault_unwind(target *t)
|
|||
target_regs_read(t, regs);
|
||||
/* save retcode currently in lr */
|
||||
retcode = regs[REG_LR];
|
||||
bool spsel = retcode & (1<<2);
|
||||
bool fpca = !(retcode & (1<<4));
|
||||
bool spsel = retcode & (1U << 2U);
|
||||
bool fpca = !(retcode & (1U << 4U));
|
||||
/* Read stack for pre-exception registers */
|
||||
uint32_t sp = spsel ? regs[REG_PSP] : regs[REG_MSP];
|
||||
target_mem_read(t, stack, sp, sizeof(stack));
|
||||
|
|
@ -904,19 +888,19 @@ static int cortexm_fault_unwind(target *t)
|
|||
regs[REG_PC] = stack[6]; /* restore PC to pre-exception state */
|
||||
|
||||
/* adjust stack to pop exception state */
|
||||
framesize = fpca ? 0x68 : 0x20; /* check for basic vs. extended frame */
|
||||
if (stack[7] & (1<<9)) /* check for stack alignment fixup */
|
||||
framesize += 4;
|
||||
framesize = fpca ? 0x68U : 0x20U; /* check for basic vs. extended frame */
|
||||
if (stack[7] & (1U << 9U)) /* check for stack alignment fixup */
|
||||
framesize += 4U;
|
||||
|
||||
if (spsel) {
|
||||
regs[REG_SPECIAL] |= 0x4000000;
|
||||
regs[REG_SPECIAL] |= 0x4000000U;
|
||||
regs[REG_SP] = regs[REG_PSP] += framesize;
|
||||
} else {
|
||||
regs[REG_SP] = regs[REG_MSP] += framesize;
|
||||
}
|
||||
|
||||
if (fpca)
|
||||
regs[REG_SPECIAL] |= 0x2000000;
|
||||
regs[REG_SPECIAL] |= 0x2000000U;
|
||||
|
||||
/* FIXME: stack[7] contains xPSR when this is supported */
|
||||
/* although, if we caught the exception it will be unchanged */
|
||||
|
|
@ -924,8 +908,7 @@ static int cortexm_fault_unwind(target *t)
|
|||
/* Reset exception state to allow resuming from restored
|
||||
* state.
|
||||
*/
|
||||
target_mem_write32(t, CORTEXM_AIRCR,
|
||||
CORTEXM_AIRCR_VECTKEY | CORTEXM_AIRCR_VECTCLRACTIVE);
|
||||
target_mem_write32(t, CORTEXM_AIRCR, CORTEXM_AIRCR_VECTKEY | CORTEXM_AIRCR_VECTCLRACTIVE);
|
||||
|
||||
/* Write pre-exception registers back to core */
|
||||
target_regs_write(t, regs);
|
||||
|
|
@ -935,10 +918,9 @@ static int cortexm_fault_unwind(target *t)
|
|||
return 0;
|
||||
}
|
||||
|
||||
int cortexm_run_stub(target *t, uint32_t loadaddr,
|
||||
uint32_t r0, uint32_t r1, uint32_t r2, uint32_t r3)
|
||||
int cortexm_run_stub(target *t, uint32_t loadaddr, uint32_t r0, uint32_t r1, uint32_t r2, uint32_t r3)
|
||||
{
|
||||
uint32_t regs[t->regs_size / 4];
|
||||
uint32_t regs[t->regs_size / 4U];
|
||||
|
||||
memset(regs, 0, sizeof(regs));
|
||||
regs[0] = r0;
|
||||
|
|
@ -970,9 +952,8 @@ int cortexm_run_stub(target *t, uint32_t loadaddr,
|
|||
DEBUG_WARN("Stub hangs\n");
|
||||
uint32_t arm_regs[t->regs_size];
|
||||
target_regs_read(t, arm_regs);
|
||||
for (unsigned int i = 0; i < 20; i++) {
|
||||
DEBUG_WARN("%2d: %08" PRIx32 ", %08" PRIx32 "\n",
|
||||
i, arm_regs_start[i], arm_regs[i]);
|
||||
for (size_t i = 0; i < 20; i++) {
|
||||
DEBUG_WARN("%2d: %08" PRIx32 ", %08" PRIx32 "\n", i, arm_regs_start[i], arm_regs[i]);
|
||||
}
|
||||
#endif
|
||||
return -3;
|
||||
|
|
@ -988,10 +969,10 @@ int cortexm_run_stub(target *t, uint32_t loadaddr,
|
|||
}
|
||||
uint32_t pc = cortexm_pc_read(t);
|
||||
uint16_t bkpt_instr = target_mem_read16(t, pc);
|
||||
if (bkpt_instr >> 8 != 0xbe)
|
||||
if (bkpt_instr >> 8U != 0xbeU)
|
||||
return -2;
|
||||
|
||||
return bkpt_instr & 0xff;
|
||||
return bkpt_instr & 0xffU;
|
||||
}
|
||||
|
||||
/* The following routines implement hardware breakpoints and watchpoints.
|
||||
|
|
@ -1034,16 +1015,16 @@ static uint32_t dwt_func(target *t, enum target_breakwatch type)
|
|||
static int cortexm_breakwatch_set(target *t, struct breakwatch *bw)
|
||||
{
|
||||
struct cortexm_priv *priv = t->priv;
|
||||
unsigned i;
|
||||
size_t i;
|
||||
uint32_t val = bw->addr;
|
||||
|
||||
switch (bw->type) {
|
||||
case TARGET_BREAK_HARD:
|
||||
if (priv->flash_patch_revision == 0) {
|
||||
val &= 0x1FFFFFFC;
|
||||
val |= (bw->addr & 2)?0x80000000:0x40000000;
|
||||
val &= 0x1ffffffcU;
|
||||
val |= (bw->addr & 2U) ? 0x80000000U : 0x40000000U;
|
||||
}
|
||||
val |= 1;
|
||||
val |= 1U;
|
||||
|
||||
for (i = 0; i < priv->hw_breakpoint_max; i++)
|
||||
if (!priv->hw_breakpoint[i])
|
||||
|
|
@ -1107,9 +1088,7 @@ static target_addr cortexm_check_watch(target *t)
|
|||
|
||||
for (i = 0; i < priv->hw_watchpoint_max; i++)
|
||||
/* if SET and MATCHED then break */
|
||||
if(priv->hw_watchpoint[i] &&
|
||||
(target_mem_read32(t, CORTEXM_DWT_FUNC(i)) &
|
||||
CORTEXM_DWT_FUNC_MATCHED))
|
||||
if (priv->hw_watchpoint[i] && (target_mem_read32(t, CORTEXM_DWT_FUNC(i)) & CORTEXM_DWT_FUNC_MATCHED))
|
||||
break;
|
||||
|
||||
if (i == priv->hw_watchpoint_max)
|
||||
|
|
@ -1121,8 +1100,7 @@ static target_addr cortexm_check_watch(target *t)
|
|||
static bool cortexm_vector_catch(target *t, int argc, char *argv[])
|
||||
{
|
||||
struct cortexm_priv *priv = t->priv;
|
||||
const char *vectors[] = {"reset", NULL, NULL, NULL, "mm", "nocp",
|
||||
"chk", "stat", "bus", "int", "hard"};
|
||||
static const char *vectors[] = {"reset", NULL, NULL, NULL, "mm", "nocp", "chk", "stat", "bus", "int", "hard"};
|
||||
uint32_t tmp = 0;
|
||||
unsigned i;
|
||||
|
||||
|
|
@ -1222,16 +1200,18 @@ static void probe_mem_read(target *t __attribute__((unused)), void *probe_dest,
|
|||
uint8_t *src = (uint8_t *)target_src;
|
||||
|
||||
DEBUG_INFO("probe_mem_read\n");
|
||||
while (len--) *dst++=*src++;
|
||||
|
||||
memcpy(dst, src, len);
|
||||
}
|
||||
|
||||
static void probe_mem_write(target *t __attribute__((unused)), target_addr target_dest, const void *probe_src, size_t len)
|
||||
static void probe_mem_write(
|
||||
target *t __attribute__((unused)), target_addr target_dest, const void *probe_src, size_t len)
|
||||
{
|
||||
uint8_t *dst = (uint8_t *)target_dest;
|
||||
uint8_t *src = (uint8_t *)probe_src;
|
||||
|
||||
DEBUG_INFO("probe_mem_write\n");
|
||||
while (len--) *dst++=*src++;
|
||||
memcpy(dst, src, len);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
|
@ -1243,11 +1223,12 @@ static int cortexm_hostio_request(target *t)
|
|||
t->tc->interrupted = false;
|
||||
target_regs_read(t, arm_regs);
|
||||
uint32_t syscall = arm_regs[0];
|
||||
if (syscall != SYS_EXIT) target_mem_read(t, params, arm_regs[1], sizeof(params));
|
||||
if (syscall != SYS_EXIT)
|
||||
target_mem_read(t, params, arm_regs[1], sizeof(params));
|
||||
int32_t ret = 0;
|
||||
|
||||
DEBUG_INFO("syscall 0"PRIx32"%"PRIx32" (%"PRIx32" %"PRIx32" %"PRIx32" %"PRIx32")\n",
|
||||
syscall, params[0], params[1], params[2], params[3]);
|
||||
DEBUG_INFO("syscall 0" PRIx32 "%" PRIx32 " (%" PRIx32 " %" PRIx32 " %" PRIx32 " %" PRIx32 ")\n", syscall, params[0],
|
||||
params[1], params[2], params[3]);
|
||||
switch (syscall) {
|
||||
#if PC_HOSTED == 1
|
||||
|
||||
|
|
@ -1257,11 +1238,12 @@ static int cortexm_hostio_request(target *t)
|
|||
target_addr fnam_taddr = params[0];
|
||||
uint32_t fnam_len = params[2];
|
||||
ret = -1;
|
||||
if ((fnam_taddr == TARGET_NULL) || (fnam_len == 0)) break;
|
||||
if (fnam_taddr == TARGET_NULL || fnam_len == 0)
|
||||
break;
|
||||
|
||||
/* Translate stupid fopen modes to open flags.
|
||||
* See DUI0471C, Table 8-3 */
|
||||
const uint32_t flags[] = {
|
||||
static const uint32_t flags[] = {
|
||||
O_RDONLY, /* r, rb */
|
||||
O_RDWR, /* r+, r+b */
|
||||
O_WRONLY | O_CREAT | O_TRUNC, /*w*/
|
||||
|
|
@ -1286,9 +1268,13 @@ static int cortexm_hostio_request(target *t)
|
|||
}
|
||||
|
||||
char *fnam = malloc(fnam_len + 1);
|
||||
if (fnam == NULL) break;
|
||||
if (fnam == NULL)
|
||||
break;
|
||||
target_mem_read(t, fnam, fnam_taddr, fnam_len + 1);
|
||||
if (target_check_error(t)) {free(fnam); break;}
|
||||
if (target_check_error(t)) {
|
||||
free(fnam);
|
||||
break;
|
||||
}
|
||||
fnam[fnam_len] = '\0';
|
||||
ret = open(fnam, pflag, 0644);
|
||||
free(fnam);
|
||||
|
|
@ -1305,16 +1291,22 @@ static int cortexm_hostio_request(target *t)
|
|||
ret = -1;
|
||||
target_addr buf_taddr = params[1];
|
||||
uint32_t buf_len = params[2];
|
||||
if (buf_taddr == TARGET_NULL) break;
|
||||
if (buf_len == 0) {ret = 0; break;}
|
||||
if (buf_taddr == TARGET_NULL)
|
||||
break;
|
||||
if (buf_len == 0) {
|
||||
ret = 0;
|
||||
break;
|
||||
}
|
||||
uint8_t *buf = malloc(buf_len);
|
||||
if (buf == NULL) break;
|
||||
if (buf == NULL)
|
||||
break;
|
||||
ssize_t rc = read(params[0] - 1, buf, buf_len);
|
||||
if (rc >= 0)
|
||||
rc = buf_len - rc;
|
||||
target_mem_write(t, buf_taddr, buf, buf_len);
|
||||
free(buf);
|
||||
if (target_check_error(t)) break;
|
||||
if (target_check_error(t))
|
||||
break;
|
||||
ret = rc;
|
||||
break;
|
||||
}
|
||||
|
|
@ -1323,12 +1315,20 @@ static int cortexm_hostio_request(target *t)
|
|||
ret = -1;
|
||||
target_addr buf_taddr = params[1];
|
||||
uint32_t buf_len = params[2];
|
||||
if (buf_taddr == TARGET_NULL) break;
|
||||
if (buf_len == 0) {ret = 0; break;}
|
||||
if (buf_taddr == TARGET_NULL)
|
||||
break;
|
||||
if (buf_len == 0) {
|
||||
ret = 0;
|
||||
break;
|
||||
}
|
||||
uint8_t *buf = malloc(buf_len);
|
||||
if (buf == NULL) break;
|
||||
if (buf == NULL)
|
||||
break;
|
||||
target_mem_read(t, buf, buf_taddr, buf_len);
|
||||
if (target_check_error(t)) {free(buf); break;}
|
||||
if (target_check_error(t)) {
|
||||
free(buf);
|
||||
break;
|
||||
}
|
||||
ret = write(params[0] - 1, buf, buf_len);
|
||||
free(buf);
|
||||
if (ret >= 0)
|
||||
|
|
@ -1340,9 +1340,11 @@ static int cortexm_hostio_request(target *t)
|
|||
ret = -1;
|
||||
uint8_t ch;
|
||||
target_addr ch_taddr = arm_regs[1];
|
||||
if (ch_taddr == TARGET_NULL) break;
|
||||
if (ch_taddr == TARGET_NULL)
|
||||
break;
|
||||
ch = target_mem_read8(t, ch_taddr);
|
||||
if (target_check_error(t)) break;
|
||||
if (target_check_error(t))
|
||||
break;
|
||||
fputc(ch, stderr);
|
||||
ret = 0;
|
||||
break;
|
||||
|
|
@ -1352,9 +1354,11 @@ static int cortexm_hostio_request(target *t)
|
|||
ret = -1;
|
||||
uint8_t ch;
|
||||
target_addr str = arm_regs[1];
|
||||
if (str == TARGET_NULL) break;
|
||||
if (str == TARGET_NULL)
|
||||
break;
|
||||
while ((ch = target_mem_read8(t, str++)) != '\0') {
|
||||
if (target_check_error(t)) break;
|
||||
if (target_check_error(t))
|
||||
break;
|
||||
fputc(ch, stderr);
|
||||
}
|
||||
ret = 0;
|
||||
|
|
@ -1367,8 +1371,10 @@ static int cortexm_hostio_request(target *t)
|
|||
|
||||
case SYS_SEEK: { /* lseek */
|
||||
off_t pos = params[1];
|
||||
if (lseek(params[0] - 1, pos, SEEK_SET) == (off_t)pos) ret = 0;
|
||||
else ret = -1;
|
||||
if (lseek(params[0] - 1, pos, SEEK_SET) == (off_t)pos)
|
||||
ret = 0;
|
||||
else
|
||||
ret = -1;
|
||||
break;
|
||||
}
|
||||
|
||||
|
|
@ -1376,21 +1382,36 @@ static int cortexm_hostio_request(target *t)
|
|||
ret = -1;
|
||||
target_addr fnam1_taddr = params[0];
|
||||
uint32_t fnam1_len = params[1];
|
||||
if (fnam1_taddr == TARGET_NULL) break;
|
||||
if (fnam1_len == 0) break;
|
||||
if (fnam1_taddr == TARGET_NULL)
|
||||
break;
|
||||
if (fnam1_len == 0)
|
||||
break;
|
||||
target_addr fnam2_taddr = params[2];
|
||||
uint32_t fnam2_len = params[3];
|
||||
if (fnam2_taddr == TARGET_NULL) break;
|
||||
if (fnam2_len == 0) break;
|
||||
if (fnam2_taddr == TARGET_NULL)
|
||||
break;
|
||||
if (fnam2_len == 0)
|
||||
break;
|
||||
char *fnam1 = malloc(fnam1_len + 1);
|
||||
if (fnam1 == NULL) break;
|
||||
if (fnam1 == NULL)
|
||||
break;
|
||||
target_mem_read(t, fnam1, fnam1_taddr, fnam1_len + 1);
|
||||
if (target_check_error(t)) {free(fnam1); break;}
|
||||
if (target_check_error(t)) {
|
||||
free(fnam1);
|
||||
break;
|
||||
}
|
||||
fnam1[fnam1_len] = '\0';
|
||||
char *fnam2 = malloc(fnam2_len + 1);
|
||||
if (fnam2 == NULL) {free(fnam1); break;}
|
||||
if (fnam2 == NULL) {
|
||||
free(fnam1);
|
||||
break;
|
||||
}
|
||||
target_mem_read(t, fnam2, fnam2_taddr, fnam2_len + 1);
|
||||
if (target_check_error(t)) {free(fnam1); free(fnam2); break;}
|
||||
if (target_check_error(t)) {
|
||||
free(fnam1);
|
||||
free(fnam2);
|
||||
break;
|
||||
}
|
||||
fnam2[fnam2_len] = '\0';
|
||||
ret = rename(fnam1, fnam2);
|
||||
free(fnam1);
|
||||
|
|
@ -1401,13 +1422,19 @@ static int cortexm_hostio_request(target *t)
|
|||
case SYS_REMOVE: { /* unlink */
|
||||
ret = -1;
|
||||
target_addr fnam_taddr = params[0];
|
||||
if (fnam_taddr == TARGET_NULL) break;
|
||||
if (fnam_taddr == TARGET_NULL)
|
||||
break;
|
||||
uint32_t fnam_len = params[1];
|
||||
if (fnam_len == 0) break;
|
||||
if (fnam_len == 0)
|
||||
break;
|
||||
char *fnam = malloc(fnam_len + 1);
|
||||
if (fnam == NULL) break;
|
||||
if (fnam == NULL)
|
||||
break;
|
||||
target_mem_read(t, fnam, fnam_taddr, fnam_len + 1);
|
||||
if (target_check_error(t)) {free(fnam); break;}
|
||||
if (target_check_error(t)) {
|
||||
free(fnam);
|
||||
break;
|
||||
}
|
||||
fnam[fnam_len] = '\0';
|
||||
ret = remove(fnam);
|
||||
free(fnam);
|
||||
|
|
@ -1417,13 +1444,19 @@ static int cortexm_hostio_request(target *t)
|
|||
case SYS_SYSTEM: { /* system */
|
||||
ret = -1;
|
||||
target_addr cmd_taddr = params[0];
|
||||
if (cmd_taddr == TARGET_NULL) break;
|
||||
if (cmd_taddr == TARGET_NULL)
|
||||
break;
|
||||
uint32_t cmd_len = params[1];
|
||||
if (cmd_len == 0) break;
|
||||
if (cmd_len == 0)
|
||||
break;
|
||||
char *cmd = malloc(cmd_len + 1);
|
||||
if (cmd == NULL) break;
|
||||
if (cmd == NULL)
|
||||
break;
|
||||
target_mem_read(t, cmd, cmd_taddr, cmd_len + 1);
|
||||
if (target_check_error(t)) {free(cmd); break;}
|
||||
if (target_check_error(t)) {
|
||||
free(cmd);
|
||||
break;
|
||||
}
|
||||
cmd[cmd_len] = '\0';
|
||||
ret = system(cmd);
|
||||
free(cmd);
|
||||
|
|
@ -1433,8 +1466,10 @@ static int cortexm_hostio_request(target *t)
|
|||
case SYS_FLEN: { /* file length */
|
||||
ret = -1;
|
||||
struct stat stat_buf;
|
||||
if (fstat(params[0]-1, &stat_buf) != 0) break;
|
||||
if (stat_buf.st_size > INT32_MAX) break;
|
||||
if (fstat(params[0] - 1, &stat_buf) != 0)
|
||||
break;
|
||||
if (stat_buf.st_size > INT32_MAX)
|
||||
break;
|
||||
ret = stat_buf.st_size;
|
||||
break;
|
||||
}
|
||||
|
|
@ -1443,12 +1478,14 @@ static int cortexm_hostio_request(target *t)
|
|||
/* can't use clock() because that would give cpu time of pc-hosted process */
|
||||
ret = -1;
|
||||
struct timeval timeval_buf;
|
||||
if(gettimeofday(&timeval_buf, NULL) != 0) break;
|
||||
if (gettimeofday(&timeval_buf, NULL) != 0)
|
||||
break;
|
||||
uint32_t sec = timeval_buf.tv_sec;
|
||||
uint64_t usec = timeval_buf.tv_usec;
|
||||
if (time0_sec > sec) time0_sec = sec;
|
||||
if (time0_sec > sec)
|
||||
time0_sec = sec;
|
||||
sec -= time0_sec;
|
||||
uint64_t csec64 = (sec * 1000000ull + usec)/10000ull;
|
||||
uint64_t csec64 = (sec * UINT64_C(1000000) + usec) / UINT64_C(10000);
|
||||
uint32_t csec = csec64 & 0x7fffffff;
|
||||
ret = csec;
|
||||
break;
|
||||
|
|
@ -1473,7 +1510,7 @@ static int cortexm_hostio_request(target *t)
|
|||
case SYS_OPEN: { /* open */
|
||||
/* Translate stupid fopen modes to open flags.
|
||||
* See DUI0471C, Table 8-3 */
|
||||
const uint32_t flags[] = {
|
||||
static const uint32_t flags[] = {
|
||||
TARGET_O_RDONLY, /* r, rb */
|
||||
TARGET_O_RDWR, /* r+, r+b */
|
||||
TARGET_O_WRONLY | TARGET_O_CREAT | TARGET_O_TRUNC, /*w*/
|
||||
|
|
@ -1524,13 +1561,15 @@ static int cortexm_hostio_request(target *t)
|
|||
target_addr str_begin = arm_regs[1];
|
||||
target_addr str_end = str_begin;
|
||||
while (target_mem_read8(t, str_end) != 0) {
|
||||
if (target_check_error(t)) break;
|
||||
if (target_check_error(t))
|
||||
break;
|
||||
str_end++;
|
||||
}
|
||||
int len = str_end - str_begin;
|
||||
if (len != 0) {
|
||||
int rc = tc_write(t, STDERR_FILENO, str_begin, len);
|
||||
if (rc != len) break;
|
||||
if (rc != len)
|
||||
break;
|
||||
}
|
||||
ret = 0;
|
||||
break;
|
||||
|
|
@ -1539,12 +1578,13 @@ static int cortexm_hostio_request(target *t)
|
|||
ret = tc_isatty(t, params[0] - 1);
|
||||
break;
|
||||
case SYS_SEEK: /* lseek */
|
||||
if (tc_lseek(t, params[0] - 1, params[1], TARGET_SEEK_SET) == (long)params[1]) ret = 0;
|
||||
else ret = -1;
|
||||
if (tc_lseek(t, params[0] - 1, params[1], TARGET_SEEK_SET) == (long)params[1])
|
||||
ret = 0;
|
||||
else
|
||||
ret = -1;
|
||||
break;
|
||||
case SYS_RENAME: /* rename */
|
||||
ret = tc_rename(t, params[0], params[1] + 1,
|
||||
params[2], params[3] + 1);
|
||||
ret = tc_rename(t, params[0], params[1] + 1, params[2], params[3] + 1);
|
||||
break;
|
||||
case SYS_REMOVE: /* unlink */
|
||||
ret = tc_unlink(t, params[0], params[1] + 1);
|
||||
|
|
@ -1554,8 +1594,7 @@ static int cortexm_hostio_request(target *t)
|
|||
ret = tc_system(t, params[0], params[1] + 1);
|
||||
break;
|
||||
|
||||
case SYS_FLEN:
|
||||
{ /* file length */
|
||||
case SYS_FLEN: { /* file length */
|
||||
ret = -1;
|
||||
uint32_t fio_stat[16]; /* same size as fio_stat in gdb/include/gdb/fileio.h */
|
||||
//DEBUG("SYS_FLEN fio_stat addr %p\n", fio_stat);
|
||||
|
|
@ -1568,12 +1607,15 @@ static int cortexm_hostio_request(target *t)
|
|||
int rc = tc_fstat(t, params[0] - 1, (target_addr)fio_stat); /* write fstat() result in fio_stat[] */
|
||||
t->mem_read = saved_mem_read;
|
||||
t->mem_write = saved_mem_write;
|
||||
if (rc) break; /* tc_fstat() failed */
|
||||
if (rc)
|
||||
break; /* tc_fstat() failed */
|
||||
uint32_t fst_size_msw = fio_stat[7]; /* most significant 32 bits of fst_size in fio_stat */
|
||||
uint32_t fst_size_lsw = fio_stat[8]; /* least significant 32 bits of fst_size in fio_stat */
|
||||
if (fst_size_msw != 0) break; /* file size too large for int32_t return type */
|
||||
if (fst_size_msw != 0)
|
||||
break; /* file size too large for int32_t return type */
|
||||
ret = __builtin_bswap32(fst_size_lsw); /* convert from bigendian to target order */
|
||||
if (ret < 0) ret = -1; /* file size too large for int32_t return type */
|
||||
if (ret < 0)
|
||||
ret = -1; /* file size too large for int32_t return type */
|
||||
break;
|
||||
}
|
||||
|
||||
|
|
@ -1592,18 +1634,21 @@ static int cortexm_hostio_request(target *t)
|
|||
saved_mem_write = t->mem_write;
|
||||
t->mem_read = probe_mem_read;
|
||||
t->mem_write = probe_mem_write;
|
||||
int rc = tc_gettimeofday(t, (target_addr) &fio_timeval, (target_addr) NULL); /* write gettimeofday() result in fio_timeval[] */
|
||||
int rc = tc_gettimeofday(
|
||||
t, (target_addr)&fio_timeval, (target_addr)NULL); /* write gettimeofday() result in fio_timeval[] */
|
||||
t->mem_read = saved_mem_read;
|
||||
t->mem_write = saved_mem_write;
|
||||
if (rc) break; /* tc_gettimeofday() failed */
|
||||
if (rc)
|
||||
break; /* tc_gettimeofday() failed */
|
||||
uint32_t sec = __builtin_bswap32(fio_timeval.ftv_sec); /* convert from bigendian to target order */
|
||||
uint64_t usec = __builtin_bswap64(fio_timeval.ftv_usec);
|
||||
if (syscall == SYS_TIME) { /* SYS_TIME: time in seconds */
|
||||
ret = sec;
|
||||
} else { /* SYS_CLOCK: time in hundredths of seconds */
|
||||
if (time0_sec > sec) time0_sec = sec; /* set sys_clock time origin */
|
||||
if (time0_sec > sec)
|
||||
time0_sec = sec; /* set sys_clock time origin */
|
||||
sec -= time0_sec;
|
||||
uint64_t csec64 = (sec * 1000000ull + usec)/10000ull;
|
||||
uint64_t csec64 = (sec * UINT64_C(1000000) + usec) / UINT64_C(10000);
|
||||
uint32_t csec = csec64 & 0x7fffffff;
|
||||
ret = csec;
|
||||
}
|
||||
|
|
@ -1622,8 +1667,10 @@ static int cortexm_hostio_request(target *t)
|
|||
int rc = tc_read(t, STDIN_FILENO, (target_addr)&ch, 1); /* read a character in ch */
|
||||
t->mem_read = saved_mem_read;
|
||||
t->mem_write = saved_mem_write;
|
||||
if (rc == 1) ret = ch;
|
||||
else ret = -1;
|
||||
if (rc == 1)
|
||||
ret = ch;
|
||||
else
|
||||
ret = -1;
|
||||
break;
|
||||
}
|
||||
|
||||
|
|
@ -1647,39 +1694,27 @@ static int cortexm_hostio_request(target *t)
|
|||
ret = -1;
|
||||
target_addr buf_ptr = params[0];
|
||||
target_addr buf_len = params[1];
|
||||
if (strlen(t->cmdline)+1 > buf_len) break;
|
||||
if(target_mem_write(t, buf_ptr, t->cmdline, strlen(t->cmdline)+1)) break;
|
||||
if (strlen(t->cmdline) + 1 > buf_len)
|
||||
break;
|
||||
if (target_mem_write(t, buf_ptr, t->cmdline, strlen(t->cmdline) + 1))
|
||||
break;
|
||||
retval[0] = buf_ptr;
|
||||
retval[1] = strlen(t->cmdline) + 1;
|
||||
if(target_mem_write(t, arm_regs[1], retval, sizeof(retval))) break;
|
||||
if (target_mem_write(t, arm_regs[1], retval, sizeof(retval)))
|
||||
break;
|
||||
ret = 0;
|
||||
break;
|
||||
}
|
||||
|
||||
case SYS_ISERROR: { /* iserror */
|
||||
int errorNo = params[0];
|
||||
ret = (errorNo == TARGET_EPERM) ||
|
||||
(errorNo == TARGET_ENOENT) ||
|
||||
(errorNo == TARGET_EINTR) ||
|
||||
(errorNo == TARGET_EIO) ||
|
||||
(errorNo == TARGET_EBADF) ||
|
||||
(errorNo == TARGET_EACCES) ||
|
||||
(errorNo == TARGET_EFAULT) ||
|
||||
(errorNo == TARGET_EBUSY) ||
|
||||
(errorNo == TARGET_EEXIST) ||
|
||||
(errorNo == TARGET_ENODEV) ||
|
||||
(errorNo == TARGET_ENOTDIR) ||
|
||||
(errorNo == TARGET_EISDIR) ||
|
||||
(errorNo == TARGET_EINVAL) ||
|
||||
(errorNo == TARGET_ENFILE) ||
|
||||
(errorNo == TARGET_EMFILE) ||
|
||||
(errorNo == TARGET_EFBIG) ||
|
||||
(errorNo == TARGET_ENOSPC) ||
|
||||
(errorNo == TARGET_ESPIPE) ||
|
||||
(errorNo == TARGET_EROFS) ||
|
||||
(errorNo == TARGET_ENOSYS) ||
|
||||
(errorNo == TARGET_ENAMETOOLONG) ||
|
||||
(errorNo == TARGET_EUNKNOWN);
|
||||
ret = errorNo == TARGET_EPERM || errorNo == TARGET_ENOENT || errorNo == TARGET_EINTR || errorNo == TARGET_EIO ||
|
||||
errorNo == TARGET_EBADF || errorNo == TARGET_EACCES || errorNo == TARGET_EFAULT ||
|
||||
errorNo == TARGET_EBUSY || errorNo == TARGET_EEXIST || errorNo == TARGET_ENODEV ||
|
||||
errorNo == TARGET_ENOTDIR || errorNo == TARGET_EISDIR || errorNo == TARGET_EINVAL ||
|
||||
errorNo == TARGET_ENFILE || errorNo == TARGET_EMFILE || errorNo == TARGET_EFBIG ||
|
||||
errorNo == TARGET_ENOSPC || errorNo == TARGET_ESPIPE || errorNo == TARGET_EROFS ||
|
||||
errorNo == TARGET_ENOSYS || errorNo == TARGET_ENAMETOOLONG || errorNo == TARGET_EUNKNOWN;
|
||||
break;
|
||||
}
|
||||
|
||||
|
|
@ -1694,13 +1729,18 @@ static int cortexm_hostio_request(target *t)
|
|||
int buf_size = params[2];
|
||||
char fnam[] = "tempXX.tmp";
|
||||
ret = -1;
|
||||
if (buf_ptr == 0) break;
|
||||
if (buf_size <= 0) break;
|
||||
if ((target_id < 0) || (target_id > 255)) break; /* target id out of range */
|
||||
if (buf_ptr == 0)
|
||||
break;
|
||||
if (buf_size <= 0)
|
||||
break;
|
||||
if ((target_id < 0) || (target_id > 255))
|
||||
break; /* target id out of range */
|
||||
fnam[5] = 'A' + (target_id & 0xF); /* create filename */
|
||||
fnam[4] = 'A' + (target_id >> 4 & 0xF);
|
||||
if (strlen(fnam)+1>(uint32_t)buf_size) break; /* target buffer too small */
|
||||
if(target_mem_write(t, buf_ptr, fnam, strlen(fnam)+1)) break; /* copy filename to target */
|
||||
if (strlen(fnam) + 1 > (uint32_t)buf_size)
|
||||
break; /* target buffer too small */
|
||||
if (target_mem_write(t, buf_ptr, fnam, strlen(fnam) + 1))
|
||||
break; /* copy filename to target */
|
||||
ret = 0;
|
||||
break;
|
||||
}
|
||||
|
|
@ -1710,7 +1750,6 @@ static int cortexm_hostio_request(target *t)
|
|||
case SYS_TICKFREQ: /* tickfreq */
|
||||
ret = -1;
|
||||
break;
|
||||
|
||||
}
|
||||
|
||||
arm_regs[0] = ret;
|
||||
|
|
|
|||
|
|
@ -24,117 +24,117 @@
|
|||
|
||||
extern unsigned cortexm_wait_timeout;
|
||||
/* Private peripheral bus base address */
|
||||
#define CORTEXM_PPB_BASE 0xE0000000
|
||||
#define CORTEXM_PPB_BASE 0xe0000000U
|
||||
|
||||
#define CORTEXM_SCS_BASE (CORTEXM_PPB_BASE + 0xE000)
|
||||
#define CORTEXM_SCS_BASE (CORTEXM_PPB_BASE + 0xe000U)
|
||||
|
||||
#define CORTEXM_CPUID (CORTEXM_SCS_BASE + 0xD00)
|
||||
#define CORTEXM_AIRCR (CORTEXM_SCS_BASE + 0xD0C)
|
||||
#define CORTEXM_CFSR (CORTEXM_SCS_BASE + 0xD28)
|
||||
#define CORTEXM_HFSR (CORTEXM_SCS_BASE + 0xD2C)
|
||||
#define CORTEXM_DFSR (CORTEXM_SCS_BASE + 0xD30)
|
||||
#define CORTEXM_CPACR (CORTEXM_SCS_BASE + 0xD88)
|
||||
#define CORTEXM_DHCSR (CORTEXM_SCS_BASE + 0xDF0)
|
||||
#define CORTEXM_DCRSR (CORTEXM_SCS_BASE + 0xDF4)
|
||||
#define CORTEXM_DCRDR (CORTEXM_SCS_BASE + 0xDF8)
|
||||
#define CORTEXM_DEMCR (CORTEXM_SCS_BASE + 0xDFC)
|
||||
#define CORTEXM_CPUID (CORTEXM_SCS_BASE + 0xd00U)
|
||||
#define CORTEXM_AIRCR (CORTEXM_SCS_BASE + 0xd0cU)
|
||||
#define CORTEXM_CFSR (CORTEXM_SCS_BASE + 0xd28U)
|
||||
#define CORTEXM_HFSR (CORTEXM_SCS_BASE + 0xd2cU)
|
||||
#define CORTEXM_DFSR (CORTEXM_SCS_BASE + 0xd30U)
|
||||
#define CORTEXM_CPACR (CORTEXM_SCS_BASE + 0xd88U)
|
||||
#define CORTEXM_DHCSR (CORTEXM_SCS_BASE + 0xdf0U)
|
||||
#define CORTEXM_DCRSR (CORTEXM_SCS_BASE + 0xdf4U)
|
||||
#define CORTEXM_DCRDR (CORTEXM_SCS_BASE + 0xdf8U)
|
||||
#define CORTEXM_DEMCR (CORTEXM_SCS_BASE + 0xdfcU)
|
||||
|
||||
/* Cache identification */
|
||||
#define CORTEXM_CLIDR (CORTEXM_SCS_BASE + 0xD78)
|
||||
#define CORTEXM_CTR (CORTEXM_SCS_BASE + 0xD7C)
|
||||
#define CORTEXM_CCSIDR (CORTEXM_SCS_BASE + 0xD80)
|
||||
#define CORTEXM_CSSELR (CORTEXM_SCS_BASE + 0xD84)
|
||||
#define CORTEXM_CLIDR (CORTEXM_SCS_BASE + 0xd78U)
|
||||
#define CORTEXM_CTR (CORTEXM_SCS_BASE + 0xd7cU)
|
||||
#define CORTEXM_CCSIDR (CORTEXM_SCS_BASE + 0xd80U)
|
||||
#define CORTEXM_CSSELR (CORTEXM_SCS_BASE + 0xd84U)
|
||||
|
||||
/* Cache maintenance operations */
|
||||
#define CORTEXM_ICIALLU (CORTEXM_SCS_BASE + 0xF50)
|
||||
#define CORTEXM_DCCMVAC (CORTEXM_SCS_BASE + 0xF68)
|
||||
#define CORTEXM_DCCIMVAC (CORTEXM_SCS_BASE + 0xF70)
|
||||
#define CORTEXM_ICIALLU (CORTEXM_SCS_BASE + 0xf50U)
|
||||
#define CORTEXM_DCCMVAC (CORTEXM_SCS_BASE + 0xf68U)
|
||||
#define CORTEXM_DCCIMVAC (CORTEXM_SCS_BASE + 0xf70U)
|
||||
|
||||
#define CORTEXM_FPB_BASE (CORTEXM_PPB_BASE + 0x2000)
|
||||
#define CORTEXM_FPB_BASE (CORTEXM_PPB_BASE + 0x2000U)
|
||||
|
||||
/* ARM Literature uses FP_*, we use CORTEXM_FPB_* consistently */
|
||||
#define CORTEXM_FPB_CTRL (CORTEXM_FPB_BASE + 0x000)
|
||||
#define CORTEXM_FPB_REMAP (CORTEXM_FPB_BASE + 0x004)
|
||||
#define CORTEXM_FPB_COMP(i) (CORTEXM_FPB_BASE + 0x008 + (4*(i)))
|
||||
#define CORTEXM_FPB_CTRL (CORTEXM_FPB_BASE + 0x000U)
|
||||
#define CORTEXM_FPB_REMAP (CORTEXM_FPB_BASE + 0x004U)
|
||||
#define CORTEXM_FPB_COMP(i) (CORTEXM_FPB_BASE + 0x008U + (4U * (i)))
|
||||
|
||||
#define CORTEXM_DWT_BASE (CORTEXM_PPB_BASE + 0x1000)
|
||||
#define CORTEXM_DWT_BASE (CORTEXM_PPB_BASE + 0x1000U)
|
||||
|
||||
#define CORTEXM_DWT_CTRL (CORTEXM_DWT_BASE + 0x000)
|
||||
#define CORTEXM_DWT_COMP(i) (CORTEXM_DWT_BASE + 0x020 + (0x10*(i)))
|
||||
#define CORTEXM_DWT_MASK(i) (CORTEXM_DWT_BASE + 0x024 + (0x10*(i)))
|
||||
#define CORTEXM_DWT_FUNC(i) (CORTEXM_DWT_BASE + 0x028 + (0x10*(i)))
|
||||
#define CORTEXM_DWT_CTRL (CORTEXM_DWT_BASE + 0x000U)
|
||||
#define CORTEXM_DWT_COMP(i) (CORTEXM_DWT_BASE + 0x020U + (0x10U * (i)))
|
||||
#define CORTEXM_DWT_MASK(i) (CORTEXM_DWT_BASE + 0x024U + (0x10U * (i)))
|
||||
#define CORTEXM_DWT_FUNC(i) (CORTEXM_DWT_BASE + 0x028U + (0x10U * (i)))
|
||||
|
||||
/* Application Interrupt and Reset Control Register (AIRCR) */
|
||||
#define CORTEXM_AIRCR_VECTKEY (0x05FA << 16)
|
||||
#define CORTEXM_AIRCR_VECTKEY (0x05faU << 16U)
|
||||
/* Bits 31:16 - Read as VECTKETSTAT, 0xFA05 */
|
||||
#define CORTEXM_AIRCR_ENDIANESS (1 << 15)
|
||||
#define CORTEXM_AIRCR_ENDIANESS (1U << 15U)
|
||||
/* Bits 15:11 - Unused, reserved */
|
||||
#define CORTEXM_AIRCR_PRIGROUP (7 << 8)
|
||||
#define CORTEXM_AIRCR_PRIGROUP (7U << 8U)
|
||||
/* Bits 7:3 - Unused, reserved */
|
||||
#define CORTEXM_AIRCR_SYSRESETREQ (1 << 2)
|
||||
#define CORTEXM_AIRCR_VECTCLRACTIVE (1 << 1)
|
||||
#define CORTEXM_AIRCR_VECTRESET (1 << 0)
|
||||
#define CORTEXM_AIRCR_SYSRESETREQ (1U << 2U)
|
||||
#define CORTEXM_AIRCR_VECTCLRACTIVE (1U << 1U)
|
||||
#define CORTEXM_AIRCR_VECTRESET (1U << 0U)
|
||||
|
||||
/* HardFault Status Register (HFSR) */
|
||||
#define CORTEXM_HFSR_DEBUGEVT (1 << 31)
|
||||
#define CORTEXM_HFSR_FORCED (1 << 30)
|
||||
#define CORTEXM_HFSR_DEBUGEVT (1U << 31U)
|
||||
#define CORTEXM_HFSR_FORCED (1U << 30U)
|
||||
/* Bits 29:2 - Not specified */
|
||||
#define CORTEXM_HFSR_VECTTBL (1 << 1)
|
||||
#define CORTEXM_HFSR_VECTTBL (1U << 1U)
|
||||
/* Bits 0 - Reserved */
|
||||
|
||||
/* Debug Fault Status Register (DFSR) */
|
||||
/* Bits 31:5 - Reserved */
|
||||
#define CORTEXM_DFSR_RESETALL 0x1F
|
||||
#define CORTEXM_DFSR_EXTERNAL (1 << 4)
|
||||
#define CORTEXM_DFSR_VCATCH (1 << 3)
|
||||
#define CORTEXM_DFSR_DWTTRAP (1 << 2)
|
||||
#define CORTEXM_DFSR_BKPT (1 << 1)
|
||||
#define CORTEXM_DFSR_HALTED (1 << 0)
|
||||
#define CORTEXM_DFSR_RESETALL 0x1fU
|
||||
#define CORTEXM_DFSR_EXTERNAL (1U << 4U)
|
||||
#define CORTEXM_DFSR_VCATCH (1U << 3U)
|
||||
#define CORTEXM_DFSR_DWTTRAP (1U << 2U)
|
||||
#define CORTEXM_DFSR_BKPT (1U << 1U)
|
||||
#define CORTEXM_DFSR_HALTED (1U << 0U)
|
||||
|
||||
/* Debug Halting Control and Status Register (DHCSR) */
|
||||
/* This key must be written to bits 31:16 for write to take effect */
|
||||
#define CORTEXM_DHCSR_DBGKEY 0xA05F0000
|
||||
#define CORTEXM_DHCSR_DBGKEY 0xa05f0000U
|
||||
/* Bits 31:26 - Reserved */
|
||||
#define CORTEXM_DHCSR_S_RESET_ST (1 << 25)
|
||||
#define CORTEXM_DHCSR_S_RETIRE_ST (1 << 24)
|
||||
#define CORTEXM_DHCSR_S_RESET_ST (1U << 25U)
|
||||
#define CORTEXM_DHCSR_S_RETIRE_ST (1U << 24U)
|
||||
/* Bits 23:20 - Reserved */
|
||||
#define CORTEXM_DHCSR_S_LOCKUP (1 << 19)
|
||||
#define CORTEXM_DHCSR_S_SLEEP (1 << 18)
|
||||
#define CORTEXM_DHCSR_S_HALT (1 << 17)
|
||||
#define CORTEXM_DHCSR_S_REGRDY (1 << 16)
|
||||
#define CORTEXM_DHCSR_S_LOCKUP (1U << 19U)
|
||||
#define CORTEXM_DHCSR_S_SLEEP (1U << 18U)
|
||||
#define CORTEXM_DHCSR_S_HALT (1U << 17U)
|
||||
#define CORTEXM_DHCSR_S_REGRDY (1U << 16U)
|
||||
/* Bits 15:6 - Reserved */
|
||||
#define CORTEXM_DHCSR_C_SNAPSTALL (1 << 5) /* v7m only */
|
||||
#define CORTEXM_DHCSR_C_SNAPSTALL (1U << 5U) /* v7m only */
|
||||
/* Bit 4 - Reserved */
|
||||
#define CORTEXM_DHCSR_C_MASKINTS (1 << 3)
|
||||
#define CORTEXM_DHCSR_C_STEP (1 << 2)
|
||||
#define CORTEXM_DHCSR_C_HALT (1 << 1)
|
||||
#define CORTEXM_DHCSR_C_DEBUGEN (1 << 0)
|
||||
#define CORTEXM_DHCSR_C_MASKINTS (1U << 3U)
|
||||
#define CORTEXM_DHCSR_C_STEP (1U << 2U)
|
||||
#define CORTEXM_DHCSR_C_HALT (1U << 1U)
|
||||
#define CORTEXM_DHCSR_C_DEBUGEN (1U << 0U)
|
||||
|
||||
/* Debug Core Register Selector Register (DCRSR) */
|
||||
#define CORTEXM_DCRSR_REGWnR 0x00010000
|
||||
#define CORTEXM_DCRSR_REGSEL_MASK 0x0000001F
|
||||
#define CORTEXM_DCRSR_REGSEL_MASK 0x0000001f
|
||||
#define CORTEXM_DCRSR_REGSEL_XPSR 0x00000010
|
||||
#define CORTEXM_DCRSR_REGSEL_MSP 0x00000011
|
||||
#define CORTEXM_DCRSR_REGSEL_PSP 0x00000012
|
||||
|
||||
/* Debug Exception and Monitor Control Register (DEMCR) */
|
||||
/* Bits 31:25 - Reserved */
|
||||
#define CORTEXM_DEMCR_TRCENA (1 << 24)
|
||||
#define CORTEXM_DEMCR_TRCENA (1U << 24U)
|
||||
/* Bits 23:20 - Reserved */
|
||||
#define CORTEXM_DEMCR_MON_REQ (1 << 19) /* v7m only */
|
||||
#define CORTEXM_DEMCR_MON_STEP (1 << 18) /* v7m only */
|
||||
#define CORTEXM_DEMCR_VC_MON_PEND (1 << 17) /* v7m only */
|
||||
#define CORTEXM_DEMCR_VC_MON_EN (1 << 16) /* v7m only */
|
||||
#define CORTEXM_DEMCR_MON_REQ (1U << 19U) /* v7m only */
|
||||
#define CORTEXM_DEMCR_MON_STEP (1U << 18U) /* v7m only */
|
||||
#define CORTEXM_DEMCR_VC_MON_PEND (1U << 17U) /* v7m only */
|
||||
#define CORTEXM_DEMCR_VC_MON_EN (1U << 16U) /* v7m only */
|
||||
/* Bits 15:11 - Reserved */
|
||||
#define CORTEXM_DEMCR_VC_HARDERR (1 << 10)
|
||||
#define CORTEXM_DEMCR_VC_INTERR (1 << 9) /* v7m only */
|
||||
#define CORTEXM_DEMCR_VC_BUSERR (1 << 8) /* v7m only */
|
||||
#define CORTEXM_DEMCR_VC_STATERR (1 << 7) /* v7m only */
|
||||
#define CORTEXM_DEMCR_VC_CHKERR (1 << 6) /* v7m only */
|
||||
#define CORTEXM_DEMCR_VC_NOCPERR (1 << 5) /* v7m only */
|
||||
#define CORTEXM_DEMCR_VC_MMERR (1 << 4) /* v7m only */
|
||||
#define CORTEXM_DEMCR_VC_HARDERR (1U << 10U)
|
||||
#define CORTEXM_DEMCR_VC_INTERR (1U << 9U) /* v7m only */
|
||||
#define CORTEXM_DEMCR_VC_BUSERR (1U << 8U) /* v7m only */
|
||||
#define CORTEXM_DEMCR_VC_STATERR (1U << 7U) /* v7m only */
|
||||
#define CORTEXM_DEMCR_VC_CHKERR (1U << 6U) /* v7m only */
|
||||
#define CORTEXM_DEMCR_VC_NOCPERR (1U << 5U) /* v7m only */
|
||||
#define CORTEXM_DEMCR_VC_MMERR (1U << 4U) /* v7m only */
|
||||
/* Bits 3:1 - Reserved */
|
||||
#define CORTEXM_DEMCR_VC_CORERESET (1 << 0)
|
||||
#define CORTEXM_DEMCR_VC_CORERESET (1U << 0U)
|
||||
|
||||
/* Flash Patch and Breakpoint Control Register (FP_CTRL) */
|
||||
/* Bits 32:15 - Reserved */
|
||||
|
|
@ -142,35 +142,35 @@ extern unsigned cortexm_wait_timeout;
|
|||
/* Bits 11:8 - NUM_LIT */ /* v7m only */
|
||||
/* Bits 7:4 - NUM_CODE1 */
|
||||
/* Bits 3:2 - Unspecified */
|
||||
#define CORTEXM_FPB_CTRL_KEY (1 << 1)
|
||||
#define CORTEXM_FPB_CTRL_ENABLE (1 << 0)
|
||||
#define CORTEXM_FPB_CTRL_KEY (1U << 1U)
|
||||
#define CORTEXM_FPB_CTRL_ENABLE (1U << 0U)
|
||||
|
||||
/* Data Watchpoint and Trace Mask Register (DWT_MASKx)
|
||||
* The value here is the number of address bits we mask out */
|
||||
#define CORTEXM_DWT_MASK_BYTE (0)
|
||||
#define CORTEXM_DWT_MASK_HALFWORD (1)
|
||||
#define CORTEXM_DWT_MASK_WORD (2)
|
||||
#define CORTEXM_DWT_MASK_DWORD (3)
|
||||
#define CORTEXM_DWT_MASK_BYTE (0U)
|
||||
#define CORTEXM_DWT_MASK_HALFWORD (1U)
|
||||
#define CORTEXM_DWT_MASK_WORD (2U)
|
||||
#define CORTEXM_DWT_MASK_DWORD (3U)
|
||||
|
||||
/* Data Watchpoint and Trace Function Register (DWT_FUNCTIONx) */
|
||||
#define CORTEXM_DWT_FUNC_MATCHED (1 << 24)
|
||||
#define CORTEXM_DWT_FUNC_DATAVSIZE_WORD (2 << 10) /* v7m only */
|
||||
#define CORTEXM_DWT_FUNC_FUNC_READ (5 << 0)
|
||||
#define CORTEXM_DWT_FUNC_FUNC_WRITE (6 << 0)
|
||||
#define CORTEXM_DWT_FUNC_FUNC_ACCESS (7 << 0)
|
||||
#define CORTEXM_DWT_FUNC_MATCHED (1U << 24U)
|
||||
#define CORTEXM_DWT_FUNC_DATAVSIZE_WORD (2U << 10U) /* v7m only */
|
||||
#define CORTEXM_DWT_FUNC_FUNC_READ (5U << 0U)
|
||||
#define CORTEXM_DWT_FUNC_FUNC_WRITE (6U << 0U)
|
||||
#define CORTEXM_DWT_FUNC_FUNC_ACCESS (7U << 0U)
|
||||
|
||||
#define REG_SP 13
|
||||
#define REG_LR 14
|
||||
#define REG_PC 15
|
||||
#define REG_XPSR 16
|
||||
#define REG_MSP 17
|
||||
#define REG_PSP 18
|
||||
#define REG_SPECIAL 19
|
||||
#define REG_SP 13U
|
||||
#define REG_LR 14U
|
||||
#define REG_PC 15U
|
||||
#define REG_XPSR 16U
|
||||
#define REG_MSP 17U
|
||||
#define REG_PSP 18U
|
||||
#define REG_SPECIAL 19U
|
||||
|
||||
#define ARM_THUMB_BREAKPOINT 0xBE00
|
||||
#define CORTEXM_XPSR_THUMB (1 << 24)
|
||||
#define ARM_THUMB_BREAKPOINT 0xbe00U
|
||||
#define CORTEXM_XPSR_THUMB (1U << 24U)
|
||||
|
||||
#define CORTEXM_TOPT_INHIBIT_NRST (1 << 2)
|
||||
#define CORTEXM_TOPT_INHIBIT_NRST (1U << 2U)
|
||||
|
||||
enum cortexm_types {
|
||||
CORTEX_M0 = 0xc200,
|
||||
|
|
@ -181,17 +181,15 @@ enum cortexm_types {
|
|||
CORTEX_M23 = 0xd200,
|
||||
CORTEX_M33 = 0xd210,
|
||||
};
|
||||
#define CPUID_PARTNO_MASK 0xfff0
|
||||
#define CPUID_REVISION_MASK 0x00f00000
|
||||
#define CPUID_PATCH_MASK 0xf
|
||||
#define CPUID_PARTNO_MASK 0xfff0U
|
||||
#define CPUID_REVISION_MASK 0x00f00000U
|
||||
#define CPUID_PATCH_MASK 0xfU
|
||||
|
||||
ADIv5_AP_t *cortexm_ap(target *t);
|
||||
|
||||
bool cortexm_attach(target *t);
|
||||
void cortexm_detach(target *t);
|
||||
int cortexm_run_stub(target *t, uint32_t loadaddr,
|
||||
uint32_t r0, uint32_t r1, uint32_t r2, uint32_t r3);
|
||||
int cortexm_mem_write_sized(
|
||||
target *t, target_addr dest, const void *src, size_t len, enum align align);
|
||||
int cortexm_run_stub(target *t, uint32_t loadaddr, uint32_t r0, uint32_t r1, uint32_t r2, uint32_t r3);
|
||||
int cortexm_mem_write_sized(target *t, target_addr dest, const void *src, size_t len, enum align align);
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue