stm32h7: Switched to the unified mass erase command, breaking up the implementation cleanly and added progress dots to stop GDB timing out
This commit is contained in:
dragonmux
Piotr Esden-Tempski
parent
980a1f140c
commit
787d66fe95
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@ -37,7 +37,6 @@
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#include "target_internal.h"
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#include "cortexm.h"
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static bool stm32h7_cmd_erase_mass(target *t, int argc, const char **argv);
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/* static bool stm32h7_cmd_option(target *t, int argc, char *argv[]); */
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static bool stm32h7_uid(target *t, int argc, const char **argv);
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static bool stm32h7_crc(target *t, int argc, const char **argv);
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@ -45,29 +44,22 @@ static bool stm32h7_cmd_psize(target *t, int argc, char *argv[]);
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static bool stm32h7_cmd_rev(target *t, int argc, const char **argv);
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const struct command_s stm32h7_cmd_list[] = {
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{"erase_mass", (cmd_handler)stm32h7_cmd_erase_mass,
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"Erase entire flash memory"},
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/* {"option", (cmd_handler)stm32h7_cmd_option,
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"Manipulate option bytes"},*/
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{"psize", (cmd_handler)stm32h7_cmd_psize,
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"Configure flash write parallelism: (x8|x16|x32|x64(default))"},
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/*{"option", (cmd_handler)stm32h7_cmd_option, "Manipulate option bytes"},*/
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{"psize", (cmd_handler)stm32h7_cmd_psize, "Configure flash write parallelism: (x8|x16|x32|x64(default))"},
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{"uid", (cmd_handler)stm32h7_uid, "Print unique device ID"},
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{"crc", (cmd_handler)stm32h7_crc, "Print CRC of both banks"},
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{"revision", (cmd_handler)stm32h7_cmd_rev,
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"Returns the Device ID and Revision"},
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{"revision", (cmd_handler)stm32h7_cmd_rev, "Returns the Device ID and Revision"},
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{NULL, NULL, NULL}
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};
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static int stm32h7_flash_erase(struct target_flash *f, target_addr addr,
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size_t len);
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static int stm32h7_flash_write(struct target_flash *f,
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target_addr dest, const void *src, size_t len);
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static int stm32h7_flash_erase(struct target_flash *f, target_addr addr, size_t len);
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static int stm32h7_flash_write(struct target_flash *f, target_addr dest, const void *src, size_t len);
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static bool stm32h7_mass_erase(target *t);
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static const char stm32h7_driver_str[] = "STM32H7";
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enum stm32h7_regs
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{
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enum stm32h7_regs {
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FLASH_ACR = 0x00,
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FLASH_KEYR = 0x04,
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FLASH_OPTKEYR = 0x08,
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@ -169,18 +161,15 @@ struct stm32h7_priv_s {
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uint32_t dbg_cr;
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};
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static void stm32h7_add_flash(target *t,
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uint32_t addr, size_t length, size_t blocksize)
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static void stm32h7_add_flash(target *t, uint32_t addr, size_t length, size_t blocksize)
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{
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struct stm32h7_flash *sf = calloc(1, sizeof(*sf));
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struct target_flash *f;
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if (!sf) { /* calloc failed: heap exhaustion */
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DEBUG_WARN("calloc: failed in %s\n", __func__);
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return;
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}
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f = &sf->f;
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struct target_flash *f = &sf->f;
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f->start = addr;
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f->length = length;
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f->blocksize = blocksize;
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@ -237,6 +226,7 @@ bool stm32h7_probe(target *t)
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{
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uint32_t idcode = t->idcode;
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if (idcode == ID_STM32H74x || idcode == ID_STM32H7Bx || idcode == ID_STM32H72x) {
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t->mass_erase = stm32h7_mass_erase;
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t->driver = stm32h7_driver_str;
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t->attach = stm32h7_attach;
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t->detach = stm32h7_detach;
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@ -255,21 +245,20 @@ bool stm32h7_probe(target *t)
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return false;
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}
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static bool stm32h7_flash_unlock(target *t, uint32_t addr)
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static bool stm32h7_flash_unlock(target *t, const uint32_t addr)
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{
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uint32_t regbase = FPEC1_BASE;
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if (addr >= BANK2_START) {
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if (addr >= BANK2_START)
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regbase = FPEC2_BASE;
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}
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while(target_mem_read32(t, regbase + FLASH_SR) & FLASH_SR_BSY) {
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if(target_check_error(t))
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while (target_mem_read32(t, regbase + FLASH_SR) & FLASH_SR_BSY) {
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if (target_check_error(t))
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return false;
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}
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uint32_t sr = target_mem_read32(t, regbase + FLASH_SR) & FLASH_SR_ERROR_MASK;
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if (sr) {
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DEBUG_WARN("%s error 0x%08" PRIx32, __func__, sr);
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target_mem_write32(t, regbase + FLASH_CCR, sr);
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const uint32_t status = target_mem_read32(t, regbase + FLASH_SR) & FLASH_SR_ERROR_MASK;
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if (status) {
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DEBUG_WARN("%s error 0x%08" PRIx32, __func__, status);
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target_mem_write32(t, regbase + FLASH_CCR, status);
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return false;
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}
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if (target_mem_read32(t, regbase + FLASH_CR) & FLASH_CR_LOCK) {
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@ -277,77 +266,72 @@ static bool stm32h7_flash_unlock(target *t, uint32_t addr)
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target_mem_write32(t, regbase + FLASH_KEYR, KEY1);
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target_mem_write32(t, regbase + FLASH_KEYR, KEY2);
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}
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if (target_mem_read32(t, regbase + FLASH_CR) & FLASH_CR_LOCK)
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return false;
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else
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return true;
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return !(target_mem_read32(t, regbase + FLASH_CR) & FLASH_CR_LOCK);
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}
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static int stm32h7_flash_erase(struct target_flash *f, target_addr addr,
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size_t len)
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static int stm32h7_flash_erase(struct target_flash *f, target_addr addr, size_t len)
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{
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target *t = f->t;
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struct stm32h7_flash *sf = (struct stm32h7_flash *)f;
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if (stm32h7_flash_unlock(t, addr) == false)
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if (!stm32h7_flash_unlock(t, addr))
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return -1;
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/* We come out of reset with HSI 64 MHz. Adapt FLASH_ACR.*/
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target_mem_write32(t, sf->regbase + FLASH_ACR, 0);
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addr &= (NUM_SECTOR_PER_BANK * FLASH_SECTOR_SIZE) - 1;
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int start_sector = addr / FLASH_SECTOR_SIZE;
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int end_sector = (addr + len - 1) / FLASH_SECTOR_SIZE;
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size_t start_sector = addr / FLASH_SECTOR_SIZE;
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const size_t end_sector = (addr + len - 1) / FLASH_SECTOR_SIZE;
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enum align psize = ((struct stm32h7_flash *)f)->psize;
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uint32_t sr;
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while (start_sector <= end_sector) {
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uint32_t cr = (psize * FLASH_CR_PSIZE16) | FLASH_CR_SER |
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(start_sector * FLASH_CR_SNB_1);
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target_mem_write32(t, sf->regbase + FLASH_CR, cr);
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cr |= FLASH_CR_START;
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target_mem_write32(t, sf->regbase + FLASH_CR, cr);
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uint32_t ctrl_reg = (psize * FLASH_CR_PSIZE16) | FLASH_CR_SER | (start_sector * FLASH_CR_SNB_1);
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target_mem_write32(t, sf->regbase + FLASH_CR, ctrl_reg);
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ctrl_reg |= FLASH_CR_START;
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target_mem_write32(t, sf->regbase + FLASH_CR, ctrl_reg);
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DEBUG_INFO(" started cr %08" PRIx32 " sr %08" PRIx32 "\n",
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target_mem_read32(t, sf->regbase + FLASH_CR),
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target_mem_read32(t, sf->regbase + FLASH_SR));
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uint32_t status = 0;
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do {
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sr = target_mem_read32(t, sf->regbase + FLASH_SR);
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status = target_mem_read32(t, sf->regbase + FLASH_SR);
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if (target_check_error(t)) {
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DEBUG_WARN("stm32h7_flash_erase: comm failed\n");
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return -1;
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}
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// target_mem_write32(t, H7_IWDG_BASE, 0x0000aaaa);
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}while (sr & (FLASH_SR_QW | FLASH_SR_BSY));
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if (sr & FLASH_SR_ERROR_MASK) {
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DEBUG_WARN("stm32h7_flash_erase: error, sr: %08" PRIx32 "\n", sr);
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} while (status & (FLASH_SR_QW | FLASH_SR_BSY));
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if (status & FLASH_SR_ERROR_MASK) {
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DEBUG_WARN("stm32h7_flash_erase: error, sr: %08" PRIx32 "\n", status);
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return -1;
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}
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start_sector++;
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++start_sector;
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}
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return 0;
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}
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static int stm32h7_flash_write(struct target_flash *f, target_addr dest,
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const void *src, size_t len)
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static int stm32h7_flash_write(struct target_flash *f, target_addr dest, const void *src, size_t len)
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{
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target *t = f->t;
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struct stm32h7_flash *sf = (struct stm32h7_flash *)f;
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enum align psize = sf->psize;
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if (stm32h7_flash_unlock(t, dest) == false)
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if (!stm32h7_flash_unlock(t, dest))
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return -1;
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uint32_t cr = psize * FLASH_CR_PSIZE16;
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target_mem_write32(t, sf->regbase + FLASH_CR, cr);
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cr |= FLASH_CR_PG;
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target_mem_write32(t, sf->regbase + FLASH_CR, cr);
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/* does H7 stall?*/
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uint32_t sr_reg = sf->regbase + FLASH_SR;
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uint32_t sr;
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uint32_t status_reg = sf->regbase + FLASH_SR;
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uint32_t status = 0;
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target_mem_write(t, dest, src, len);
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while ((sr = target_mem_read32(t, sr_reg)) & FLASH_SR_BSY) {
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while ((status = target_mem_read32(t, status_reg)) & FLASH_SR_BSY) {
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if(target_check_error(t)) {
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DEBUG_WARN("stm32h7_flash_write: BSY comm failed\n");
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return -1;
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}
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}
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if (sr & FLASH_SR_ERROR_MASK) {
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DEBUG_WARN("stm32h7_flash_write: error sr %08" PRIx32 "\n", sr);
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if (status & FLASH_SR_ERROR_MASK) {
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DEBUG_WARN("stm32h7_flash_write: error sr %08" PRIx32 "\n", status);
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return -1;
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}
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/* Close write windows.*/
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@ -355,97 +339,62 @@ static int stm32h7_flash_write(struct target_flash *f, target_addr dest,
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return 0;
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}
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/* Both banks are erased in parallel.*/
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static bool stm32h7_cmd_erase(target *t, int bank_mask)
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static bool stm32h7_erase_bank(target *const t, const enum align psize,
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const uint32_t start_addr, const uint32_t reg_base)
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{
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const char spinner[] = "|/-\\";
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int spinindex = 0;
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bool do_bank1 = bank_mask & 1, do_bank2 = bank_mask & 2;
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uint32_t cr;
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bool result = false;
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enum align psize = ALIGN_DWORD;
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for (struct target_flash *f = t->flash; f; f = f->next) {
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if (f->write == stm32h7_flash_write) {
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psize = ((struct stm32h7_flash *)f)->psize;
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if (!stm32h7_flash_unlock(t, start_addr)) {
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DEBUG_WARN("mass erase: Unlock bank failed\n");
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return false;
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}
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}
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cr = (psize * FLASH_CR_PSIZE16) | FLASH_CR_BER | FLASH_CR_START;
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/* Flash mass erase start instruction */
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if (do_bank1) {
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if (stm32h7_flash_unlock(t, BANK1_START) == false) {
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DEBUG_WARN("ME: Unlock bank1 failed\n");
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goto done;
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}
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uint32_t regbase = FPEC1_BASE;
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/* BER and start can be merged (3.3.10).*/
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target_mem_write32(t, regbase + FLASH_CR, cr);
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DEBUG_INFO("ME bank1 started\n");
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}
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if (do_bank2) {
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if (stm32h7_flash_unlock(t, BANK2_START) == false) {
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DEBUG_WARN("ME: Unlock bank2 failed\n");
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goto done;
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}
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uint32_t regbase = FPEC2_BASE;
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/* BER and start can be merged (3.3.10).*/
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target_mem_write32(t, regbase + FLASH_CR, cr);
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DEBUG_INFO("ME bank2 started\n");
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}
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/* Read FLASH_SR to poll for QW bit */
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if (do_bank1) {
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uint32_t regbase = FPEC1_BASE;
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while (target_mem_read32(t, regbase + FLASH_SR) & FLASH_SR_QW) {
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// target_mem_write32(t, H7_IWDG_BASE, 0x0000aaaa);
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tc_printf(t, "\b%c", spinner[spinindex++ % 4]);
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if(target_check_error(t)) {
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DEBUG_WARN("ME bank1: comm failed\n");
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goto done;
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}
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}
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}
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if (do_bank2) {
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uint32_t regbase = FPEC2_BASE;
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while (target_mem_read32(t, regbase + FLASH_SR) & FLASH_SR_QW) {
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// target_mem_write32(t, H7_IWDG_BASE 0x0000aaaa);
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tc_printf(t, "\b%c", spinner[spinindex++ % 4]);
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if(target_check_error(t)) {
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DEBUG_WARN("ME bank2: comm failed\n");
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goto done;
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}
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}
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}
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if (do_bank1) {
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/* Check for error */
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uint32_t regbase = FPEC1_BASE;
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uint32_t sr = target_mem_read32(t, regbase + FLASH_SR);
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if (sr & FLASH_SR_ERROR_MASK) {
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DEBUG_WARN("ME bank1, error sr %" PRIx32 "\n", sr);
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goto done;
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}
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}
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if (do_bank2) {
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/* Check for error */
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uint32_t regbase = FPEC2_BASE;
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uint32_t sr = target_mem_read32(t, regbase + FLASH_SR);
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if (sr & FLASH_SR_ERROR_MASK) {
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DEBUG_WARN("ME bank2, error: sr %" PRIx32 "\n", sr);
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goto done;
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}
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}
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result = true;
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done:
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tc_printf(t, "\n");
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return result;
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const uint32_t ctrl_reg = (psize * FLASH_CR_PSIZE16) | FLASH_CR_BER | FLASH_CR_START;
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target_mem_write32(t, reg_base + FLASH_CR, ctrl_reg);
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DEBUG_INFO("mass erase of bank started\n");
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return true;
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}
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static bool stm32h7_cmd_erase_mass(target *t, int argc, const char **argv)
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static bool stm32h7_wait_erase_bank(target *const t, platform_timeout *timeout, const uint32_t reg_base)
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{
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(void)argc;
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(void)argv;
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tc_printf(t, "Erasing flash... This may take a few seconds. ");
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return stm32h7_cmd_erase(t, 3);
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while (target_mem_read32(t, reg_base + FLASH_SR) & FLASH_SR_QW) {
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if (target_check_error(t)) {
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DEBUG_WARN("mass erase bank: comm failed\n");
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return false;
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}
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target_print_progress(timeout);
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}
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return true;
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}
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static bool stm32h7_check_bank(target *const t, const uint32_t reg_base)
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{
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uint32_t status = target_mem_read32(t, reg_base + FLASH_SR);
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if (status & FLASH_SR_ERROR_MASK)
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DEBUG_WARN("mass erase bank: error sr %" PRIx32 "\n", status);
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return !(status & FLASH_SR_ERROR_MASK);
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}
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/* Both banks are erased in parallel.*/
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static bool stm32h7_mass_erase(target *t)
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{
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enum align psize = ALIGN_DWORD;
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for (struct target_flash *flash = t->flash; flash; flash = flash->next) {
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if (flash->write == stm32h7_flash_write)
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psize = ((struct stm32h7_flash *)flash)->psize;
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}
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/* Send mass erase Flash start instruction */
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if (!stm32h7_erase_bank(t, psize, BANK1_START, FPEC1_BASE) ||
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stm32h7_erase_bank(t, psize, BANK2_START, FPEC2_BASE))
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return false;
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platform_timeout timeout;
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platform_timeout_set(&timeout, 500);
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/* Wait for the banks to finish erasing */
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if (!stm32h7_wait_erase_bank(t, &timeout, FPEC1_BASE) ||
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!stm32h7_wait_erase_bank(t, &timeout, FPEC2_BASE))
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return false;
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/* Check the banks for final errors */
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return stm32h7_check_bank(t, FPEC1_BASE) && stm32h7_check_bank(t, FPEC2_BASE);
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}
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/* Print the Unique device ID.
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