cortexa: Implement single register read/write

This commit is contained in:
Gareth McMullin 2017-10-02 13:06:33 +13:00 committed by UweBonnes
parent 20cad17ce3
commit 7bcf7f4924
1 changed files with 46 additions and 0 deletions

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@ -43,6 +43,9 @@ static void cortexa_regs_read(target *t, void *data);
static void cortexa_regs_write(target *t, const void *data);
static void cortexa_regs_read_internal(target *t);
static void cortexa_regs_write_internal(target *t);
static ssize_t cortexa_reg_read(target *t, int reg, void *data, size_t max);
static ssize_t cortexa_reg_write(target *t, int reg, const void *data, size_t max);
static void cortexa_reset(target *t);
static enum target_halt_reason cortexa_halt_poll(target *t, target_addr *watch);
@ -357,6 +360,8 @@ bool cortexa_probe(ADIv5_AP_t *apb, uint32_t debug_base)
t->tdesc = tdesc_cortex_a;
t->regs_read = cortexa_regs_read;
t->regs_write = cortexa_regs_write;
t->reg_read = cortexa_reg_read;
t->reg_write = cortexa_reg_write;
t->reset = cortexa_reset;
t->halt_request = cortexa_halt_request;
@ -468,6 +473,47 @@ static void cortexa_regs_write(target *t, const void *data)
memcpy(&priv->reg_cache, data, t->regs_size);
}
static ssize_t ptr_for_reg(target *t, int reg, void **r)
{
struct cortexa_priv *priv = (struct cortexa_priv *)t->priv;
switch (reg) {
case 0 ... 15:
*r = &priv->reg_cache.r[reg];
return 4;
case 16:
*r = &priv->reg_cache.cpsr;
return 4;
case 17:
*r = &priv->reg_cache.fpscr;
return 4;
case 18 ... 33:
*r = &priv->reg_cache.d[reg - 18];
return 8;
default:
return -1;
}
}
static ssize_t cortexa_reg_read(target *t, int reg, void *data, size_t max)
{
void *r = NULL;
size_t s = ptr_for_reg(t, reg, &r);
if (s > max)
return -1;
memcpy(data, r, s);
return s;
}
static ssize_t cortexa_reg_write(target *t, int reg, const void *data, size_t max)
{
void *r = NULL;
size_t s = ptr_for_reg(t, reg, &r);
if (s > max)
return -1;
memcpy(r, data, s);
return s;
}
static void cortexa_regs_read_internal(target *t)
{
struct cortexa_priv *priv = (struct cortexa_priv *)t->priv;