Merge pull request #98 from UweBonnes/stm32l4
Add STM32L4 handling. No option write handling yet.
This commit is contained in:
Gareth McMullin
commit
7e5a664df9
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@ -11,7 +11,7 @@ endif
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CFLAGS=-Os -std=gnu99 -mcpu=cortex-m0 -mthumb -I../libopencm3/include
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ASFLAGS=-mcpu=cortex-m3 -mthumb
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all: lmi.stub stm32f4.stub nrf51.stub stm32f1.stub
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all: lmi.stub stm32f4.stub stm32l4.stub nrf51.stub stm32f1.stub
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stm32f1.o: stm32f1.c
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$(Q)echo " CC $<"
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@ -21,6 +21,10 @@ stm32f4.o: stm32f4.c
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$(Q)echo " CC $<"
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$(Q)$(CC) $(CFLAGS) -DSTM32F4 -o $@ -c $<
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stm32l4.o: stm32l4.c
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$(Q)echo " CC $<"
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$(Q)$(CC) $(CFLAGS) -o $@ -c $<
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%.o: %.s
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$(Q)echo " AS $<"
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$(Q)$(AS) $(ASFLAGS) -o $@ $<
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@ -0,0 +1,53 @@
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/*
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* This file is part of the Black Magic Debug project.
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*
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* Copyright (C) 2015 Black Sphere Technologies Ltd.
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* Written by Gareth McMullin <gareth@blacksphere.co.nz>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "stub.h"
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#include <stdint.h>
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/* No STM32L4 definitions in libopencm3 yet */
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#define FLASH_SR ((volatile uint32_t *) 0x40022010)
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#define FLASH_SR_EOP (1 << 0)
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#define SR_ERROR_MASK 0xC3FA
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#define FLASH_SR_BSY (1 << 16)
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#define FLASH_CR ((volatile uint32_t *) 0x40022014)
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#define FLASH_CR_PG (1 << 0)
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#define FLASH_CR_EOPIE (1 << 24)
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#define FLASH_CR_ERRIE (1 << 25)
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#define FLASH_SR_EOP (1 << 0)
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void __attribute__((naked))
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stm32l4_flash_write_stub(uint32_t *dest, uint32_t *src, uint32_t size)
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{
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if ((size & 7) || ((uint32_t)dest & 7))
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stub_exit(1);
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for (int i = 0; i < size; i += 8) {
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*FLASH_CR = FLASH_CR_EOPIE | FLASH_CR_ERRIE | FLASH_CR_PG;
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*dest++ = *src++;
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*dest++ = *src++;
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__asm("dsb");
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while (*FLASH_SR & FLASH_SR_BSY)
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;
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if ((*FLASH_SR & SR_ERROR_MASK) || !(*FLASH_SR & FLASH_SR_EOP))
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stub_exit(1);
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*FLASH_SR |= FLASH_SR_EOP;
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}
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*FLASH_CR = 0;
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stub_exit(0);
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}
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@ -0,0 +1 @@
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0x1C04, 0x4314, 0x2300, 0x0764, 0xD011, 0xBE01, 0xE00F, 0x4C11, 0x6825, 0x03ED, 0xD4FB, 0x6826, 0x4D0F, 0x422E, 0xD115, 0x6825, 0x07ED, 0xD512, 0x2601, 0x6825, 0x3308, 0x4335, 0x6025, 0x4C0B, 0x4293, 0xD20C, 0x4D0A, 0x6025, 0x58CC, 0x50C4, 0x18CC, 0x6865, 0x18C4, 0x6065, 0xF3BF, 0x8F4F, 0xE7E1, 0xBE01, 0xE7EA, 0x2300, 0x6023, 0xBE00, 0x2010, 0x4002, 0xC3FA, 0x0000, 0x2014, 0x4002, 0x0001, 0x0300,
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@ -41,6 +41,7 @@ SRC = \
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stm32f1.c \
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stm32f4.c \
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stm32l0.c \
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stm32l4.c \
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swdptap.c \
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target.c \
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@ -243,6 +243,7 @@ bool cortexm_probe(target *t)
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PROBE(stm32f1_probe);
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PROBE(stm32f4_probe);
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PROBE(stm32l0_probe); /* STM32L0xx & STM32L1xx */
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PROBE(stm32l4_probe);
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PROBE(lpc11xx_probe);
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PROBE(lpc43xx_probe);
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PROBE(sam3x_probe);
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@ -263,6 +263,7 @@ bool stm32f1_probe(target *t);
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bool stm32f4_probe(target *t);
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bool stm32l0_probe(target *t);
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bool stm32l1_probe(target *t);
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bool stm32l4_probe(target *t);
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bool lmi_probe(target *t);
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bool lpc11xx_probe(target *t);
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bool lpc43xx_probe(target *t);
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@ -0,0 +1,288 @@
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/*
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* This file is part of the Black Magic Debug project.
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*
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* Copyright (C) 2015 Uwe Bonnes
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* Written by Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/* This file implements STM32L4 target specific functions for detecting
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* the device, providing the XML memory map and Flash memory programming.
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*
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* On L4, flash and options are written in DWORDs (8-Byte) only.
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*
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* Refereces:
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* ST doc - RM0351
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* Reference manual
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* STM32L4x6 advanced ARM®-based 32-bit MCUs
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*
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*/
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#include "general.h"
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#include "adiv5.h"
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#include "target.h"
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#include "cortexm.h"
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#include "command.h"
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#include "gdb_packet.h"
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static bool stm32l4_cmd_erase_mass(target *t);
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static bool stm32l4_cmd_erase_bank1(target *t);
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static bool stm32l4_cmd_erase_bank2(target *t);
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static bool stm32l4_cmd_option(target *t, int argc, char *argv[]);
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const struct command_s stm32l4_cmd_list[] = {
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{"erase_mass", (cmd_handler)stm32l4_cmd_erase_mass, "Erase entire flash memory"},
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{"erase_bank1", (cmd_handler)stm32l4_cmd_erase_bank1, "Erase entire bank1 flash memory"},
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{"erase_bank2", (cmd_handler)stm32l4_cmd_erase_bank2, "Erase entire bank2 flash memory"},
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{"option", (cmd_handler)stm32l4_cmd_option, "Manipulate option bytes"},
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{NULL, NULL, NULL}
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};
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static int stm32l4_flash_erase(struct target_flash *f, uint32_t addr, size_t len);
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static int stm32l4_flash_write(struct target_flash *f,
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uint32_t dest, const void *src, size_t len);
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static const char stm32l4_driver_str[] = "STM32L4xx";
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#define PAGE_SIZE 0x800
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/* Flash Program ad Erase Controller Register Map */
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#define FPEC_BASE 0x40022000
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#define FLASH_ACR (FPEC_BASE+0x00)
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#define FLASH_KEYR (FPEC_BASE+0x08)
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#define FLASH_OPTKEYR (FPEC_BASE+0x0c)
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#define FLASH_SR (FPEC_BASE+0x10)
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#define FLASH_CR (FPEC_BASE+0x14)
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#define FLASH_OPTR (FPEC_BASE+0x20)
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//#define FLASH_OPTCR (FPEC_BASE+0x14)
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#define FLASH_CR_PG (1 << 0)
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#define FLASH_CR_PER (1 << 1)
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#define FLASH_CR_MER1 (1 << 2)
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#define FLASH_CR_PAGE_SHIFT 3
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#define FLASH_CR_BKER (1 << 11)
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#define FLASH_CR_MER2 (1 << 15)
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#define FLASH_CR_STRT (1 << 16)
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#define FLASH_CR_OPTSTRT (1 << 17)
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#define FLASH_CR_FSTPG (1 << 18)
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#define FLASH_CR_EOPIE (1 << 24)
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#define FLASH_CR_ERRIE (1 << 25)
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#define FLASH_CR_OPTLOCK (1 << 30)
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#define FLASH_CR_LOCK (1 << 31)
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#define FLASH_SR_EOP (1 << 0)
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#define FLASH_SR_OPERR (1 << 1)
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#define FLASH_SR_PROGERR (1 << 3)
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#define FLASH_SR_WRPERR (1 << 4)
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#define FLASH_SR_PGAERR (1 << 5)
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#define FLASH_SR_SIZERR (1 << 6)
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#define FLASH_SR_PGSERR (1 << 7)
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#define FLASH_SR_MSERR (1 << 8)
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#define FLASH_SR_FASTERR (1 << 9)
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#define FLASH_SR_RDERR (1 << 14)
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#define FLASH_SR_OPTVERR (1 << 15)
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#define FLASH_SR_ERROR_MASK 0xC3FA
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#define FLASH_SR_BSY (1 << 16)
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#define KEY1 0x45670123
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#define KEY2 0xCDEF89AB
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#define OPTKEY1 0x08192A3B
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#define OPTKEY2 0x4C5D6E7F
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#define SR_ERROR_MASK 0xF2
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#define OR_DUALBANK (1 << 21)
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#define DBGMCU_IDCODE 0xE0042000
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#define FLASH_SIZE_REG 0x1FFF75E0
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#define FLASH_SIZE_REG 0x1FFF75E0
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/* This routine is uses double word access.*/
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static const uint16_t stm32l4_flash_write_stub[] = {
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#include "../flashstub/stm32l4.stub"
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};
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#define SRAM_BASE 0x20000000
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#define STUB_BUFFER_BASE ALIGN(SRAM_BASE + sizeof(stm32l4_flash_write_stub), 8)
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struct stm32l4_flash {
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struct target_flash f;
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uint32_t bank1_start;
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};
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static void stm32l4_add_flash(target *t,
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uint32_t addr, size_t length, size_t blocksize,
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uint32_t bank1_start)
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{
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struct stm32l4_flash *sf = calloc(1, sizeof(*sf));
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struct target_flash *f = &sf->f;
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f->start = addr;
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f->length = length;
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f->blocksize = blocksize;
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f->erase = stm32l4_flash_erase;
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f->write = stm32l4_flash_write;
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f->align = 8;
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f->erased = 0xff;
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sf->bank1_start = bank1_start;
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target_add_flash(t, f);
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}
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bool stm32l4_probe(target *t)
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{
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uint32_t idcode;
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uint32_t size;
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uint32_t options;
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uint32_t bank1_start = 0x08040000;
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idcode = target_mem_read32(t, DBGMCU_IDCODE);
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switch(idcode & 0xFFF) {
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case 0x415: /* */
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t->driver = stm32l4_driver_str;
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target_add_ram(t, 0x10000000, 1 << 15);
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target_add_ram(t, 0x20000000, 3 << 15);
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size = (target_mem_read32(t, FLASH_SIZE_REG) & 0xffff);
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options = target_mem_read32(t, FLASH_OPTR);
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if ((size < 0x400) && (options & OR_DUALBANK))
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bank1_start = 0x08000000 + (size << 9);
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stm32l4_add_flash(t, 0x08000000, size << 10, PAGE_SIZE, bank1_start);
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target_add_commands(t, stm32l4_cmd_list, "STM32L4");
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return true;
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}
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return false;
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}
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static void stm32l4_flash_unlock(target *t)
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{
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if (target_mem_read32(t, FLASH_CR) & FLASH_CR_LOCK) {
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/* Enable FPEC controller access */
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target_mem_write32(t, FLASH_KEYR, KEY1);
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target_mem_write32(t, FLASH_KEYR, KEY2);
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}
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}
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static int stm32l4_flash_erase(struct target_flash *f, uint32_t addr, size_t len)
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{
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target *t = f->t;
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uint16_t sr;
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uint32_t bank1_start = ((struct stm32l4_flash *)f)->bank1_start;
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uint32_t page;
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stm32l4_flash_unlock(t);
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page = (addr - 0x08000000) / PAGE_SIZE;
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while(len) {
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uint32_t cr;
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cr = FLASH_CR_PER | (page << FLASH_CR_PAGE_SHIFT );
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if (addr >= bank1_start)
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cr |= FLASH_CR_BKER;
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/* Flash page erase instruction */
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target_mem_write32(t, FLASH_CR, cr);
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/* write address to FMA */
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cr |= FLASH_CR_STRT;
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target_mem_write32(t, FLASH_CR, cr);
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/* Read FLASH_SR to poll for BSY bit */
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while(target_mem_read32(t, FLASH_SR) & FLASH_SR_BSY)
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if(target_check_error(t))
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return -1;
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len -= PAGE_SIZE;
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addr += PAGE_SIZE;
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page++;
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}
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/* Check for error */
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sr = target_mem_read32(t, FLASH_SR);
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if(sr & FLASH_SR_ERROR_MASK)
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return -1;
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return 0;
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}
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static int stm32l4_flash_write(struct target_flash *f,
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uint32_t dest, const void *src, size_t len)
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{
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/* Write buffer to target ram call stub */
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target_mem_write(f->t, SRAM_BASE, stm32l4_flash_write_stub,
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sizeof(stm32l4_flash_write_stub));
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target_mem_write(f->t, STUB_BUFFER_BASE, src, len);
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return cortexm_run_stub(f->t, SRAM_BASE, dest,
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STUB_BUFFER_BASE, len, 0);
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}
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static bool stm32l4_cmd_erase(target *t, uint32_t action)
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{
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const char spinner[] = "|/-\\";
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int spinindex = 0;
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gdb_out("Erasing flash... This may take a few seconds. ");
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stm32l4_flash_unlock(t);
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/* Flash erase action start instruction */
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target_mem_write32(t, FLASH_CR, action);
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target_mem_write32(t, FLASH_CR, action | FLASH_CR_STRT);
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/* Read FLASH_SR to poll for BSY bit */
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while (target_mem_read32(t, FLASH_SR) & FLASH_SR_BSY) {
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gdb_outf("\b%c", spinner[spinindex++ % 4]);
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if(target_check_error(t)) {
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gdb_out("\n");
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return false;
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}
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}
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gdb_out("\n");
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/* Check for error */
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uint16_t sr = target_mem_read32(t, FLASH_SR);
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if (sr & FLASH_SR_ERROR_MASK)
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return false;
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return true;
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}
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static bool stm32l4_cmd_erase_mass(target *t)
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{
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return stm32l4_cmd_erase(t, FLASH_CR_MER1 | FLASH_CR_MER2);
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}
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static bool stm32l4_cmd_erase_bank1(target *t)
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{
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return stm32l4_cmd_erase(t, FLASH_CR_MER1);
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}
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static bool stm32l4_cmd_erase_bank2(target *t)
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{
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return stm32l4_cmd_erase(t, FLASH_CR_MER2);
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}
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static bool stm32l4_cmd_option(target *t, int argc, char *argv[])
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{
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uint32_t addr, val;
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(void) argc;
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(void) argv;
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for (int i = 0; i < 0x23; i += 8) {
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addr = 0x1fff7800 + i;
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val = target_mem_read32(t, addr);
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gdb_outf("0x%08X: 0x%08x\n", addr, val);
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}
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for (int i = 8; i < 0x23; i += 8) {
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addr = 0x1ffff800 + i;
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val = target_mem_read32(t, addr);
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gdb_outf("0x%08X: 0x%08X\n", addr, val);
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}
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return true;
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}
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