[efm32] Print MSC Interrupt Flags to DEBUG after each flash write
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@ -75,6 +75,7 @@ const struct command_s efm32_cmd_list[] = {
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#define EFM32_MSC_ADDRB(msc) (msc+0x010)
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#define EFM32_MSC_ADDRB(msc) (msc+0x010)
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#define EFM32_MSC_WDATA(msc) (msc+0x018)
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#define EFM32_MSC_WDATA(msc) (msc+0x018)
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#define EFM32_MSC_STATUS(msc) (msc+0x01c)
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#define EFM32_MSC_STATUS(msc) (msc+0x01c)
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#define EFM32_MSC_IF(msc) (msc+0x030)
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#define EFM32_MSC_LOCK(msc) (msc+(msc == 0x400c0000?0x3c:0x40))
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#define EFM32_MSC_LOCK(msc) (msc+(msc == 0x400c0000?0x3c:0x40))
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#define EFM32_MSC_MASSLOCK(msc) (msc+0x054)
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#define EFM32_MSC_MASSLOCK(msc) (msc+0x054)
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@ -689,16 +690,22 @@ static int efm32_flash_write(struct target_flash *f,
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if (device == NULL) {
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if (device == NULL) {
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return true;
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return true;
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}
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}
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/* Write flashloader */
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/* Write flashloader */
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target_mem_write(t, SRAM_BASE, efm32_flash_write_stub,
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target_mem_write(t, SRAM_BASE, efm32_flash_write_stub,
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sizeof(efm32_flash_write_stub));
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sizeof(efm32_flash_write_stub));
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/* Write Buffer */
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/* Write Buffer */
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target_mem_write(t, STUB_BUFFER_BASE, src, len);
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target_mem_write(t, STUB_BUFFER_BASE, src, len);
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/* Run flashloader */
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/* Run flashloader */
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return cortexm_run_stub(t, SRAM_BASE, dest, STUB_BUFFER_BASE, len, device->msc_addr);
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int ret = cortexm_run_stub(t, SRAM_BASE, dest, STUB_BUFFER_BASE, len,
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device->msc_addr);
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return 0;
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#ifdef PLATFORM_HAS_DEBUG
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/* Check the MSC_IF */
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uint32_t msc = device->msc_addr;
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uint32_t msc_if = target_mem_read32(t, EFM32_MSC_IF(msc));
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DEBUG("EFM32: Flash write done MSC_IF=%08"PRIx32"\n", msc_if);
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#endif
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return ret;
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}
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}
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/**
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/**
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