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target: rename target idcode

This commit is contained in:
Rafael Silva 2022-07-28 17:35:35 +01:00 committed by Rachel Mant
parent 8e06539eb5
commit 8238d3c020
15 changed files with 112 additions and 107 deletions
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4
src/command.c
View File

@ -359,8 +359,8 @@ static void display_target(int i, target *t, void *context)
const char attached = target_attached(t) ? '*' : ' ';
const char *const core_name = target_core_name(t);
if (!strcmp(target_driver_name(t), "ARM Cortex-M"))
gdb_outf("***%2d %c Unknown %s Designer 0x%03x Partno 0x%03x %s\n", i, attached, target_driver_name(t),
target_designer(t), target_idcode(t), core_name ? core_name : "");
gdb_outf("***%2d %c Unknown %s Designer 0x%x Part ID 0x%x %s\n", i, attached, target_driver_name(t),
target_designer(t), target_part_id(t), core_name ? core_name : "");
else
gdb_outf("%2d %c %s %s\n", i, attached, target_driver_name(t), core_name ? core_name : "");
}

2
src/include/target.h
View File

@ -52,7 +52,7 @@ bool target_attached(target *t);
const char *target_driver_name(target *t);
const char *target_core_name(target *t);
unsigned int target_designer(target *t);
unsigned int target_idcode(target *t);
unsigned int target_part_id(target *t);
/* Memory access functions */
bool target_mem_map(target *t, char *buf, size_t len);

4
src/platforms/hosted/cli.c
View File

@ -391,11 +391,11 @@ static void display_target(int i, target *t, void *context)
{
(void)context;
if (!strcmp(target_driver_name(t), "ARM Cortex-M")) {
DEBUG_INFO("***%2d%sUnknown %s Designer %3x Partno %3x %s\n",
DEBUG_INFO("***%2d%sUnknown %s Designer %x Part ID %x %s\n",
i, target_attached(t)?" * ":" ",
target_driver_name(t),
target_designer(t),
target_idcode(t),
target_part_id(t),
(target_core_name(t)) ? target_core_name(t): "");
} else {
DEBUG_INFO("*** %2d %c %s %s\n", i, target_attached(t)?'*':' ',

6
src/target/ch32f1.c
View File

@ -167,8 +167,8 @@ bool ch32f1_probe(target *t)
{
if ((t->cpuid & CPUID_PARTNO_MASK) != CORTEX_M3)
return false;
const uint32_t idcode = target_mem_read32(t, DBGMCU_IDCODE) & 0x00000fffU;
if (idcode != 0x410) // only ch32f103
const uint32_t device_id = target_mem_read32(t, DBGMCU_IDCODE) & 0x00000fffU;
if (device_id != 0x410) // only ch32f103
return false;
// try to flock (if this fails it is not a CH32 chip)
@ -178,7 +178,7 @@ bool ch32f1_probe(target *t)
if (ch32f1_flash_unlock(t))
return false;
t->idcode = idcode;
t->part_id = device_id;
uint32_t signature = target_mem_read32(t, FLASHSIZE);
uint32_t flashSize = signature & 0xFFFF;

2
src/target/cortexm.c
View File

@ -284,7 +284,7 @@ bool cortexm_probe(ADIv5_AP_t *ap)
adiv5_ap_ref(ap);
t->designer_code = ap->designer_code;
t->idcode = ap->ap_partno;
t->part_id = ap->ap_partno;
struct cortexm_priv *priv = calloc(1, sizeof(*priv));
if (!priv) { /* calloc failed: heap exhaustion */
DEBUG_WARN("calloc: failed in %s\n", __func__);

19
src/target/lpc11xx.c
View File

@ -74,8 +74,6 @@ static void lpc11xx_add_flash(target *t, const uint32_t addr, const size_t len,
bool lpc11xx_probe(target *t)
{
uint32_t idcode;
/* read the device ID register */
/* For LPC11xx & LPC11Cxx see UM10398 Rev. 12.4 Chapter 26.5.11 Table 387
* For LPC11Uxx see UM10462 Rev. 5.5 Chapter 20.13.11 Table 377
@ -85,8 +83,9 @@ bool lpc11xx_probe(target *t)
* 2) the LPC11U3x series, see UM10462 Rev.5.5 Chapter 3.1
* But see the comment for the LPC8xx series below.
*/
idcode = target_mem_read32(t, LPC11XX_DEVICE_ID);
switch (idcode) {
uint32_t device_id = target_mem_read32(t, LPC11XX_DEVICE_ID);
switch (device_id) {
case 0x0A07102B: /* LPC1110 - 4K Flash 1K SRAM */
case 0x1A07102B: /* LPC1110 - 4K Flash 1K SRAM */
case 0x0A16D02B: /* LPC1111/002 - 8K Flash 2K SRAM */
@ -159,8 +158,8 @@ bool lpc11xx_probe(target *t)
target_add_commands(t, lpc11xx_cmd_list, "LPC8N04");
return true;
}
if ((t->designer_code != JEP106_MANUFACTURER_SPECULAR) && idcode) {
DEBUG_INFO("LPC11xx: Unknown IDCODE 0x%08" PRIx32 "\n", idcode);
if ((t->designer_code != JEP106_MANUFACTURER_SPECULAR) && device_id) {
DEBUG_INFO("LPC11xx: Unknown Device ID 0x%08" PRIx32 "\n", device_id);
}
/* For LPC802, see UM11045 Rev. 1.4 Chapter 6.6.29 Table 84
* For LPC804, see UM11065 Rev. 1.0 Chapter 6.6.31 Table 87
@ -173,8 +172,8 @@ bool lpc11xx_probe(target *t)
* for the LPC8xx series is also valid for the LPC11xx "XL" and the
* LPC11U3x variants.
*/
idcode = target_mem_read32(t, LPC8XX_DEVICE_ID);
switch (idcode) {
device_id = target_mem_read32(t, LPC8XX_DEVICE_ID);
switch (device_id) {
case 0x00008021: /* LPC802M001JDH20 - 16K Flash 2K SRAM */
case 0x00008022: /* LPC802M011JDH20 */
case 0x00008023: /* LPC802M001JDH16 */
@ -273,8 +272,8 @@ bool lpc11xx_probe(target *t)
target_add_commands(t, lpc11xx_cmd_list, "LPC11xx-XL");
return true;
}
if (idcode) {
DEBUG_INFO("LPC8xx: Unknown IDCODE 0x%08" PRIx32 "\n", idcode);
if (device_id) {
DEBUG_INFO("LPC8xx: Unknown Device ID 0x%08" PRIx32 "\n", device_id);
}
return false;

7
src/target/lpc15xx.c
View File

@ -69,12 +69,12 @@ static void lpc15xx_add_flash(target *t, uint32_t addr, size_t len, size_t erase
bool
lpc15xx_probe(target *t)
{
uint32_t idcode;
uint32_t ram_size = 0;
/* read the device ID register */
idcode = target_mem_read32(t, LPC15XX_DEVICE_ID);
switch (idcode) {
const uint32_t device_id = target_mem_read32(t, LPC15XX_DEVICE_ID);
switch (device_id) {
case 0x00001549:
case 0x00001519:
ram_size = 0x9000;
@ -88,6 +88,7 @@ lpc15xx_probe(target *t)
ram_size = 0x3000;
break;
}
if (ram_size) {
t->driver = "LPC15xx";
target_add_ram(t, 0x02000000, ram_size);

41
src/target/stm32f1.c
View File

@ -118,18 +118,17 @@ static void stm32f1_add_flash(target *t, uint32_t addr, size_t length, size_t er
*/
bool gd32f1_probe(target *t)
{
uint16_t stored_idcode = t->idcode;
uint16_t device_id;
if ((t->cpuid & CPUID_PARTNO_MASK) == CORTEX_M23)
t->idcode = target_mem_read32(t, DBGMCU_IDCODE_F0) & 0xfff;
device_id = target_mem_read32(t, DBGMCU_IDCODE_F0) & 0xfff;
else
t->idcode = target_mem_read32(t, DBGMCU_IDCODE) & 0xfff;
device_id = target_mem_read32(t, DBGMCU_IDCODE) & 0xfff;
uint32_t signature = target_mem_read32(t, FLASHSIZE);
uint32_t flashSize = signature & 0xFFFF;
uint32_t ramSize = signature >> 16;
switch (t->idcode) {
switch (device_id) {
case 0x414: /* Gigadevice gd32f303 */
case 0x430:
t->driver = "GD32F3";
@ -141,10 +140,10 @@ bool gd32f1_probe(target *t)
t->driver = "GD32F1";
break;
default:
t->idcode = stored_idcode;
return false;
}
t->part_id = device_id;
t->mass_erase = stm32f1_mass_erase;
target_add_ram(t, 0x20000000, ramSize * 1024);
stm32f1_add_flash(t, 0x8000000, flashSize * 1024, 0x400);
@ -158,18 +157,17 @@ bool gd32f1_probe(target *t)
*/
bool stm32f1_probe(target *t)
{
uint16_t stored_idcode = t->idcode;
uint16_t device_id;
if ((t->cpuid & CPUID_PARTNO_MASK) == CORTEX_M0)
t->idcode = target_mem_read32(t, DBGMCU_IDCODE_F0) & 0xfff;
device_id = target_mem_read32(t, DBGMCU_IDCODE_F0) & 0xfff;
else
t->idcode = target_mem_read32(t, DBGMCU_IDCODE) & 0xfff;
device_id = target_mem_read32(t, DBGMCU_IDCODE) & 0xfff;
t->mass_erase = stm32f1_mass_erase;
size_t flash_size;
size_t block_size = 0x400;
switch (t->idcode) {
switch (device_id) {
case 0x29b: /* CS clone */
case 0x410: /* Medium density */
case 0x412: /* Low density */
@ -185,12 +183,14 @@ bool stm32f1_probe(target *t)
} else {
t->driver = "STM32F1 medium density";
}
t->part_id = device_id;
return true;
case 0x414: /* High density */
case 0x418: /* Connectivity Line */
case 0x428: /* Value Line, High Density */
t->driver = "STM32F1 VL density";
t->part_id = device_id;
target_add_ram(t, 0x20000000, 0x10000);
stm32f1_add_flash(t, 0x8000000, 0x80000, 0x800);
target_add_commands(t, stm32f1_cmd_list, "STM32 HF/CL/VL-HD");
@ -198,6 +198,7 @@ bool stm32f1_probe(target *t)
case 0x430: /* XL-density */
t->driver = "STM32F1 XL density";
t->part_id = device_id;
target_add_ram(t, 0x20000000, 0x18000);
stm32f1_add_flash(t, 0x8000000, 0x80000, 0x800);
stm32f1_add_flash(t, 0x8080000, 0x80000, 0x800);
@ -213,6 +214,7 @@ bool stm32f1_probe(target *t)
case 0x432: /* STM32F37x */
case 0x439: /* STM32F302C8 */
t->driver = "STM32F3";
t->part_id = device_id;
target_add_ram(t, 0x20000000, 0x10000);
stm32f1_add_flash(t, 0x8000000, 0x80000, 0x800);
target_add_commands(t, stm32f1_cmd_list, "STM32F3");
@ -246,7 +248,6 @@ bool stm32f1_probe(target *t)
break;
default: /* NONE */
t->idcode = stored_idcode;
return false;
}
@ -254,6 +255,8 @@ bool stm32f1_probe(target *t)
stm32f1_add_flash(t, 0x8000000, flash_size, block_size);
target_add_commands(t, stm32f1_cmd_list, "STM32F0");
t->part_id = device_id;
return true;
}
@ -276,7 +279,7 @@ static int stm32f1_flash_erase(struct target_flash *f, target_addr addr, size_t
target_addr end = addr + len - 1;
target_addr start = addr;
if (t->idcode == 0x430 && end >= FLASH_BANK_SPLIT)
if (t->part_id == 0x430 && end >= FLASH_BANK_SPLIT)
if (stm32f1_flash_unlock(t, FLASH_BANK2_OFFSET))
return -1;
@ -320,7 +323,7 @@ static int stm32f1_flash_erase(struct target_flash *f, target_addr addr, size_t
return -1;
}
}
if (t->idcode == 0x430 && end >= FLASH_BANK_SPLIT) {
if (t->part_id == 0x430 && end >= FLASH_BANK_SPLIT) {
const uint32_t status = target_mem_read32(t, FLASH_SR + FLASH_BANK2_OFFSET);
if ((status & SR_ERROR_MASK) || !(status & SR_EOP)) {
DEBUG_INFO("stm32f1 bank 2 flash erase error 0x%" PRIx32 "\n", status);
@ -365,7 +368,7 @@ static int stm32f1_flash_write(struct target_flash *f, target_addr dest, const v
}
length = len - length;
if (t->idcode == 0x430 && length) { /* Write on bank 2 */
if (t->part_id == 0x430 && length) { /* Write on bank 2 */
target_mem_write32(t, FLASH_CR + FLASH_BANK2_OFFSET, FLASH_CR_PG);
cortexm_mem_write_sized(t, dest, src, length, ALIGN_HALFWORD);
/* Read FLASH_SR to poll for BSY bit */
@ -411,7 +414,7 @@ static bool stm32f1_mass_erase(target *t)
if ((sr & SR_ERROR_MASK) || !(sr & SR_EOP))
return false;
if (t->idcode == 0x430) {
if (t->part_id == 0x430) {
if (stm32f1_flash_unlock(t, FLASH_BANK2_OFFSET))
return false;
@ -496,7 +499,7 @@ static bool stm32f1_option_write(target *t, uint32_t addr, uint16_t value)
/* Write changed values*/
bool width_word = false;
if (t->idcode == 0x410 && (t->cpuid & CPUID_PARTNO_MASK) == CORTEX_M23) {
if (t->part_id == 0x410 && (t->cpuid & CPUID_PARTNO_MASK) == CORTEX_M23) {
/* GD32E230 special case, target_mem_write16 does not work */
width_word = true;
}
@ -514,7 +517,7 @@ static bool stm32f1_cmd_option(target *t, int argc, const char **argv)
uint32_t flash_obp_rdp_key;
uint32_t rdprt;
switch (t->idcode) {
switch (t->part_id) {
case 0x422: /* STM32F30x */
case 0x432: /* STM32F37x */
case 0x438: /* STM32F303x6/8 and STM32F328 */
@ -540,7 +543,7 @@ static bool stm32f1_cmd_option(target *t, int argc, const char **argv)
if (argc == 2 && strcmp(argv[1], "erase") == 0) {
stm32f1_option_erase(t);
bool width_word = false;
if (t->idcode == 0x410 && (t->cpuid & CPUID_PARTNO_MASK) == CORTEX_M23) {
if (t->part_id == 0x410 && (t->cpuid & CPUID_PARTNO_MASK) == CORTEX_M23) {
/* GD32E230 special case, target_mem_write16 does not work */
width_word = true;
}

28
src/target/stm32f4.c
View File

@ -163,9 +163,9 @@ static void stm32f4_add_flash(target *t,
target_add_flash(t, f);
}
static char *stm32f4_get_chip_name(uint32_t idcode)
static char *stm32f4_get_chip_name(uint32_t device_id)
{
switch (idcode) {
switch (device_id) {
case ID_STM32F40X: /* F40XxE/G */
return "STM32F40x";
case ID_STM32F42X: /* F42XxG/I */
@ -208,14 +208,14 @@ static void stm32f4_detach(target *t)
bool stm32f4_probe(target *t)
{
if (t->idcode == ID_STM32F20X) {
if (t->part_id == ID_STM32F20X) {
/* F405 revision A have a wrong IDCODE, use ARM_CPUID to make the
* distinction with F205. Revision is also wrong (0x2000 instead
* of 0x1000). See F40x/F41x errata. */
if ((t->cpuid & 0xFFF0) == CORTEX_M4)
t->idcode = ID_STM32F40X;
t->part_id = ID_STM32F40X;
}
switch(t->idcode) {
switch(t->part_id) {
case ID_STM32F74X: /* F74x RM0385 Rev.4 */
case ID_STM32F76X: /* F76x F77x RM0410 */
case ID_STM32F72X: /* F72x F73x RM0431 */
@ -231,7 +231,7 @@ bool stm32f4_probe(target *t)
case ID_STM32F413: /* F413 RM0430 Rev.2, 320 kB Ram, 1.5 MB flash. */
t->mass_erase = stm32f4_mass_erase;
t->detach = stm32f4_detach;
t->driver = stm32f4_get_chip_name(t->idcode);
t->driver = stm32f4_get_chip_name(t->part_id);
t->attach = stm32f4_attach;
target_add_commands(t, stm32f4_cmd_list, t->driver);
return true;
@ -251,7 +251,7 @@ static bool stm32f4_attach(target *t)
if (!cortexm_attach(t))
return false;
switch(t->idcode) {
switch(t->part_id) {
case ID_STM32F40X:
has_ccmram = true;
max_flashsize = 1024;
@ -519,7 +519,7 @@ static bool stm32f4_mass_erase(target *t)
static bool optcr_mask(target *t, uint32_t *val)
{
switch (t->idcode) {
switch (t->part_id) {
case ID_STM32F20X:
case ID_STM32F40X:
val[0] &= ~0xF0000010;
@ -582,12 +582,12 @@ static bool stm32f4_option_write(target *t, uint32_t *val, int count)
return -1;
/* WRITE option bytes instruction */
if (((t->idcode == ID_STM32F42X) || (t->idcode == ID_STM32F46X) ||
(t->idcode == ID_STM32F72X) || (t->idcode == ID_STM32F74X) ||
(t->idcode == ID_STM32F76X)) && (count > 1))
if (((t->part_id == ID_STM32F42X) || (t->part_id == ID_STM32F46X) ||
(t->part_id == ID_STM32F72X) || (t->part_id == ID_STM32F74X) ||
(t->part_id == ID_STM32F76X)) && (count > 1))
/* Checkme: Do we need to read old value and then set it? */
target_mem_write32(t, FLASH_OPTCR + 4, val[1]);
if ((t->idcode == ID_STM32F72X) && (count > 2))
if ((t->part_id == ID_STM32F72X) && (count > 2))
target_mem_write32(t, FLASH_OPTCR + 8, val[2]);
target_mem_write32(t, FLASH_OPTCR, val[0]);
@ -614,7 +614,7 @@ static bool stm32f4_option_write(target *t, uint32_t *val, int count)
static bool stm32f4_option_write_default(target *t)
{
uint32_t val[3];
switch (t->idcode) {
switch (t->part_id) {
case ID_STM32F42X:
case ID_STM32F46X:
val[0] = 0x0FFFAAED;
@ -647,7 +647,7 @@ static bool stm32f4_cmd_option(target *t, int argc, char *argv[])
uint32_t val[3];
int count = 0, readcount = 1;
switch (t->idcode) {
switch (t->part_id) {
case ID_STM32F72X: /* STM32F72|3 */
readcount++;
/* fall through.*/

4
src/target/stm32g0.c
View File

@ -206,7 +206,7 @@ bool stm32g0_probe(target *t)
target_mem_map_free(t);
switch (t->idcode) {
switch (t->part_id) {
case STM32G03_4:
/* SRAM 8 kiB, Flash up to 64 kiB */
ram_size = (uint32_t)RAM_SIZE_G03_4;
@ -354,7 +354,7 @@ static int stm32g0_flash_erase(struct target_flash *f, target_addr addr, size_t
goto exit_cleanup;
nb_pages_to_erase = (uint16_t)((len - 1U) / f->blocksize) + 1U;
if (t->idcode == STM32G0B_C) // Dual-bank devices
if (t->part_id == STM32G0B_C) // Dual-bank devices
bank1_end_page_nb = ((f->length / 2U) - 1U) / f->blocksize;
page_nb = (uint16_t)((addr - f->start) / f->blocksize);

5
src/target/stm32h7.c
View File

@ -224,8 +224,7 @@ static void stm32h7_detach(target *t)
bool stm32h7_probe(target *t)
{
uint32_t idcode = t->idcode;
if (idcode == ID_STM32H74x || idcode == ID_STM32H7Bx || idcode == ID_STM32H72x) {
if (t->part_id == ID_STM32H74x || t->part_id == ID_STM32H7Bx || t->part_id == ID_STM32H72x) {
t->mass_erase = stm32h7_mass_erase;
t->driver = stm32h7_driver_str;
t->attach = stm32h7_attach;
@ -406,7 +405,7 @@ static bool stm32h7_uid(target *t, int argc, const char **argv)
(void)argv;
uint32_t uid = 0x1ff1e800;
if (t->idcode == ID_STM32H7Bx) {
if (t->part_id == ID_STM32H7Bx) {
uid = 0x08fff800; /* 7B3/7A3/7B0 */
}

10
src/target/stm32l0.c
View File

@ -165,7 +165,7 @@ enum stm32l_idcode_e {
static bool stm32lx_is_stm32l1(target *t)
{
switch (t->idcode) {
switch (t->part_id) {
case 0x457: /* STM32L0xx Cat1 */
case 0x425: /* STM32L0xx Cat2 */
case 0x417: /* STM32L0xx Cat3 */
@ -178,7 +178,7 @@ static bool stm32lx_is_stm32l1(target *t)
static uint32_t stm32lx_nvm_eeprom_size(target *t)
{
switch (t->idcode) {
switch (t->part_id) {
case 0x457: /* STM32L0xx Cat1 */
return STM32L0_NVM_EEPROM_CAT1_SIZE;
case 0x425: /* STM32L0xx Cat2 */
@ -194,7 +194,7 @@ static uint32_t stm32lx_nvm_eeprom_size(target *t)
static uint32_t stm32lx_nvm_phys(target *t)
{
switch (t->idcode) {
switch (t->part_id) {
case 0x457: /* STM32L0xx Cat1 */
case 0x425: /* STM32L0xx Cat2 */
case 0x417: /* STM32L0xx Cat3 */
@ -207,7 +207,7 @@ static uint32_t stm32lx_nvm_phys(target *t)
static uint32_t stm32lx_nvm_option_size(target *t)
{
switch (t->idcode) {
switch (t->part_id) {
case 0x457: /* STM32L0xx Cat1 */
case 0x425: /* STM32L0xx Cat2 */
case 0x417: /* STM32L0xx Cat3 */
@ -256,7 +256,7 @@ static void stm32l_add_eeprom(target *t, uint32_t addr, size_t length)
STM32L0xx parts as well as the STM32L1xx's. */
bool stm32l0_probe(target *t)
{
switch (t->idcode) {
switch (t->part_id) {
case 0x416: /* CAT. 1 device */
case 0x429: /* CAT. 2 device */
case 0x427: /* CAT. 3 device */

77
src/target/stm32l4.c
View File

@ -214,7 +214,7 @@ struct stm32l4_info {
uint16_t sram1; /* Normal SRAM mapped at 0x20000000*/
uint16_t sram2; /* SRAM at 0x10000000, mapped after sram1 (not L47) */
uint16_t sram3; /* SRAM mapped after SRAM1 and SRAM2 */
enum ID_STM32L4 idcode;
enum ID_STM32L4 device_id;
enum FAM_STM32L4 family;
uint8_t flags; /* Only DUAL_BANK is evaluated for now.*/
const uint32_t *flash_regs_map;
@ -222,7 +222,7 @@ struct stm32l4_info {
static struct stm32l4_info const L4info[] = {
{
.idcode = ID_STM32L41,
.device_id = ID_STM32L41,
.family = FAM_STM32L4xx,
.designator = "STM32L41x",
.sram1 = 32,
@ -231,7 +231,7 @@ static struct stm32l4_info const L4info[] = {
.flash_regs_map = stm32l4_flash_regs_map,
},
{
.idcode = ID_STM32L43,
.device_id = ID_STM32L43,
.family = FAM_STM32L4xx,
.designator = "STM32L43x",
.sram1 = 48,
@ -240,7 +240,7 @@ static struct stm32l4_info const L4info[] = {
.flash_regs_map = stm32l4_flash_regs_map,
},
{
.idcode = ID_STM32L45,
.device_id = ID_STM32L45,
.family = FAM_STM32L4xx,
.designator = "STM32L45x",
.sram1 = 128,
@ -249,7 +249,7 @@ static struct stm32l4_info const L4info[] = {
.flash_regs_map = stm32l4_flash_regs_map,
},
{
.idcode = ID_STM32L47,
.device_id = ID_STM32L47,
.family = FAM_STM32L4xx,
.designator = "STM32L47x",
.sram1 = 96,
@ -258,7 +258,7 @@ static struct stm32l4_info const L4info[] = {
.flash_regs_map = stm32l4_flash_regs_map,
},
{
.idcode = ID_STM32L49,
.device_id = ID_STM32L49,
.family = FAM_STM32L4xx,
.designator = "STM32L49x",
.sram1 = 256,
@ -267,7 +267,7 @@ static struct stm32l4_info const L4info[] = {
.flash_regs_map = stm32l4_flash_regs_map,
},
{
.idcode = ID_STM32L4R,
.device_id = ID_STM32L4R,
.family = FAM_STM32L4Rx,
.designator = "STM32L4Rx",
.sram1 = 192,
@ -277,7 +277,7 @@ static struct stm32l4_info const L4info[] = {
.flash_regs_map = stm32l4_flash_regs_map,
},
{
.idcode = ID_STM32G43,
.device_id = ID_STM32G43,
.family = FAM_STM32G4xx,
.designator = "STM32G43",
.sram1 = 22,
@ -285,7 +285,7 @@ static struct stm32l4_info const L4info[] = {
.flash_regs_map = stm32l4_flash_regs_map,
},
{
.idcode = ID_STM32G47,
.device_id = ID_STM32G47,
.family = FAM_STM32G4xx,
.designator = "STM32G47",
.sram1 = 96, /* SRAM1 and SRAM2 are mapped continuous */
@ -294,7 +294,7 @@ static struct stm32l4_info const L4info[] = {
.flash_regs_map = stm32l4_flash_regs_map,
},
{
.idcode = ID_STM32G49,
.device_id = ID_STM32G49,
.family = FAM_STM32G4xx,
.designator = "STM32G49",
.sram1 = 96, /* SRAM1 and SRAM2 are mapped continuously */
@ -303,7 +303,7 @@ static struct stm32l4_info const L4info[] = {
.flash_regs_map = stm32l4_flash_regs_map,
},
{
.idcode = ID_STM32L55,
.device_id = ID_STM32L55,
.family = FAM_STM32L55x,
.designator = "STM32L55",
.sram1 = 192, /* SRAM1 and SRAM2 are mapped continuous */
@ -312,7 +312,7 @@ static struct stm32l4_info const L4info[] = {
.flash_regs_map = stm32l5_flash_regs_map,
},
{
.idcode = ID_STM32WLXX,
.device_id = ID_STM32WLXX,
.family = FAM_STM32WLxx,
.designator = "STM32WLxx",
.sram1 = 32,
@ -321,7 +321,7 @@ static struct stm32l4_info const L4info[] = {
.flash_regs_map = stm32wl_flash_regs_map,
},
{
.idcode = ID_STM32WBXX,
.device_id = ID_STM32WBXX,
.family = FAM_STM32WBxx,
.designator = "STM32WBxx",
.sram1 = 192,
@ -331,35 +331,35 @@ static struct stm32l4_info const L4info[] = {
},
{
/* Terminator */
.idcode = 0,
.device_id = 0,
},
};
/* Retrieve chip basic information, just add to the vector to extend */
static struct stm32l4_info const * stm32l4_get_chip_info(uint32_t idcode) {
static struct stm32l4_info const * stm32l4_get_chip_info(uint32_t device_id) {
struct stm32l4_info const *p = L4info;
while (p->idcode && (p->idcode != idcode))
while (p->device_id && (p->device_id != device_id))
p++;
return p;
}
static uint32_t stm32l4_flash_read16(target *t, enum stm32l4_flash_regs reg)
{
struct stm32l4_info const *chip = stm32l4_get_chip_info(t->idcode);
struct stm32l4_info const *chip = stm32l4_get_chip_info(t->part_id);
uint32_t addr = chip->flash_regs_map[reg];
return target_mem_read16(t, addr);
}
static uint32_t stm32l4_flash_read32(target *t, enum stm32l4_flash_regs reg)
{
struct stm32l4_info const *chip = stm32l4_get_chip_info(t->idcode);
struct stm32l4_info const *chip = stm32l4_get_chip_info(t->part_id);
uint32_t addr = chip->flash_regs_map[reg];
return target_mem_read32(t, addr);
}
static void stm32l4_flash_write32(target *t, enum stm32l4_flash_regs reg, uint32_t value)
{
struct stm32l4_info const *chip = stm32l4_get_chip_info(t->idcode);
struct stm32l4_info const *chip = stm32l4_get_chip_info(t->part_id);
uint32_t addr = chip->flash_regs_map[reg];
target_mem_write32(t, addr, value);
}
@ -403,7 +403,7 @@ static bool stm32l4_attach(target *t)
return false;
/* Retrive chip information, no need to check return */
struct stm32l4_info const *chip = stm32l4_get_chip_info(t->idcode);
struct stm32l4_info const *chip = stm32l4_get_chip_info(t->part_id);
uint32_t idcodereg;
switch(chip->family) {
@ -432,7 +432,7 @@ static bool stm32l4_attach(target *t)
else
target_add_ram(t, 0x10000000, chip->sram2 << 10);
/* All L4 beside L47 alias SRAM2 after SRAM1.*/
uint32_t ramsize = (t->idcode == ID_STM32L47)?
uint32_t ramsize = (t->part_id == ID_STM32L47)?
chip->sram1 : (chip->sram1 + chip->sram2 + chip->sram3);
target_add_ram(t, 0x20000000, ramsize << 10);
@ -461,11 +461,11 @@ static bool stm32l4_attach(target *t)
// Cat 2 is always 128k with 2k pages, single bank
// Cat 3 is dual bank with an option bit to choose single 512k bank with 4k pages or dual bank as 2x256k with 2k pages
// Cat 4 is single bank with up to 512k, 2k pages
if (chip->idcode == ID_STM32G43) {
if (chip->device_id == ID_STM32G43) {
uint32_t banksize = size << 10;
stm32l4_add_flash(t, 0x08000000, banksize, 0x0800, -1);
}
else if (chip->idcode == ID_STM32G49) {
else if (chip->device_id == ID_STM32G49) {
// Announce maximum possible flash size on this chip
stm32l4_add_flash(t, 0x08000000, FLASH_SIZE_MAX_G4_CAT4, 0x0800, -1);
}
@ -510,29 +510,30 @@ static void stm32l4_detach(target *t)
bool stm32l4_probe(target *t)
{
ADIv5_AP_t *ap = cortexm_ap(t);
uint32_t idcode;
uint32_t device_id;
if (ap->dp->targetid > 1) { /* STM32L552 has invalid TARGETID 1 */
idcode = (ap->dp->targetid >> 16) & 0xfff;
/* todo: cleanup, this does not look correct, nothing in TARGETID register has offset 16 */
device_id = (ap->dp->targetid >> 16) & 0xfff;
} else {
uint32_t idcode_reg = STM32L4_DBGMCU_IDCODE_PHYS;
if (ap->dp->debug_port_id == 0x0Be12477)
idcode_reg = STM32L5_DBGMCU_IDCODE_PHYS;
idcode = target_mem_read32(t, idcode_reg) & 0xfff;
DEBUG_INFO("Idcode %08" PRIx32 "\n", idcode);
device_id = target_mem_read32(t, idcode_reg) & 0xfff;
DEBUG_INFO("Idcode %08" PRIx32 "\n", device_id);
}
struct stm32l4_info const *chip = stm32l4_get_chip_info(idcode);
struct stm32l4_info const *chip = stm32l4_get_chip_info(device_id);
if( !chip->idcode ) /* Not found */
if( !chip->device_id ) /* Not found */
return false;
t->driver = chip->designator;
switch (idcode) {
switch (device_id) {
case ID_STM32WLXX:
case ID_STM32WBXX:
if ((stm32l4_flash_read32(t, FLASH_OPTR)) & FLASH_OPTR_ESE) {
DEBUG_WARN("STM32W security enabled\n");
t->driver = (idcode == ID_STM32WLXX) ?
t->driver = (device_id == ID_STM32WLXX) ?
"STM32WLxx(secure)" : "STM32WBxx(secure)";
}
if (ap->apsel == 0) {
@ -734,15 +735,15 @@ static bool stm32l4_option_write(
static bool stm32l4_cmd_option(target *t, int argc, char *argv[])
{
if (t->idcode == ID_STM32L55) {
if (t->part_id == ID_STM32L55) {
tc_printf(t, "STM32L5 options not implemented!\n");
return false;
}
if (t->idcode == ID_STM32WBXX) {
if (t->part_id == ID_STM32WBXX) {
tc_printf(t, "STM32WBxx options not implemented!\n");
return false;
}
if (t->idcode == ID_STM32WLXX) {
if (t->part_id == ID_STM32WLXX) {
tc_printf(t, "STM32WLxx options not implemented!\n");
return false;
}
@ -766,20 +767,20 @@ static bool stm32l4_cmd_option(target *t, int argc, char *argv[])
bool res = false;
uint32_t fpec_base = L4_FPEC_BASE;
const uint8_t *i2offset = l4_i2offset;
if (t->idcode == ID_STM32L43) {/* L43x */
if (t->part_id == ID_STM32L43) {/* L43x */
len = 5;
} else if (t->idcode == ID_STM32G47) {/* G47 */
} else if (t->part_id == ID_STM32G47) {/* G47 */
i2offset = g4_i2offset;
len = 11;
for (int i = 0; i < len; i++)
values[i] = g4_values[i];
} else if ((t->idcode == ID_STM32G43) || (t->idcode == ID_STM32G49)) {
} else if ((t->part_id == ID_STM32G43) || (t->part_id == ID_STM32G49)) {
/* G4 cat 2 and 4 (single bank) */
i2offset = g4_i2offset;
len = 6;
for (int i = 0; i < len; i++)
values[i] = g4_values[i];
} else if (t->idcode == ID_STM32WLXX) {/* WLxx */
} else if (t->part_id == ID_STM32WLXX) {/* WLxx */
len = 7;
i2offset = wl_i2offset;
fpec_base = WL_FPEC_BASE;

4
src/target/target.c
View File

@ -589,9 +589,9 @@ unsigned int target_designer(target *t)
return t->designer_code;
}
unsigned int target_idcode(target *t)
unsigned int target_part_id(target *t)
{
return t->idcode;
return t->part_id;
}
uint32_t target_mem_read32(target *t, uint32_t addr)

4
src/target/target_internal.h
View File

@ -116,8 +116,10 @@ struct target_s {
/* target-defined options */
unsigned target_options;
uint16_t designer_code;
uint16_t idcode;
uint16_t part_id;
void *target_storage;
union {
bool unsafe_enabled;