sys64738
/
blackmagic
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

stm32f1.c: Use buffered direct write to flash with half word access.

This commit is contained in:
Uwe Bonnes 2018-03-15 18:27:02 +01:00
parent f1752c7a1a
commit 891d6de8eb
4 changed files with 21 additions and 57 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
src/target/flashstub/Makefile
View File

@ -11,10 +11,7 @@ endif
CFLAGS=-Os -std=gnu99 -mcpu=cortex-m0 -mthumb -I../../../libopencm3/include CFLAGS=-Os -std=gnu99 -mcpu=cortex-m0 -mthumb -I../../../libopencm3/include
ASFLAGS=-mcpu=cortex-m3 -mthumb ASFLAGS=-mcpu=cortex-m3 -mthumb
all: lmi.stub stm32l4.stub nrf51.stub \ all: lmi.stub stm32l4.stub nrf51.stub efm32.stub
stm32f1.stub efm32.stub
stm32f1.o: CFLAGS += -DSTM32F1
%.o: %.c %.o: %.c
$(Q)echo " CC $<" $(Q)echo " CC $<"

40
src/target/flashstub/stm32f1.c
View File

@ -1,40 +0,0 @@
/*
* This file is part of the Black Magic Debug project.
*
* Copyright (C) 2015 Black Sphere Technologies Ltd.
* Written by Gareth McMullin <gareth@blacksphere.co.nz>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include "libopencm3/stm32/flash.h"
#include "stub.h"
#define SR_ERROR_MASK 0x14
void __attribute__((naked))
stm32f1_flash_write_stub(uint16_t *dest, uint16_t *src, uint32_t size)
{
for (int i; i < size; i += 2) {
FLASH_CR = FLASH_CR_PG;
*dest++ = *src++;
while (FLASH_SR & FLASH_SR_BSY)
;
}
if (FLASH_SR & SR_ERROR_MASK)
stub_exit(1);
stub_exit(0);
}

1
src/target/flashstub/stm32f1.stub
View File

@ -1 +0,0 @@
0x2300, 0x4C09, 0x4293, 0xD209, 0x2601, 0x4D08, 0x602E, 0x5ACD, 0x52C5, 0x6825, 0x07ED, 0xD4FC, 0x3302, 0xE7F2, 0x2314, 0x6822, 0x421A, 0xD000, 0xBE01, 0xBE00, 0x200C, 0x4002, 0x2010, 0x4002,

32
src/target/stm32f1.c
View File

@ -72,6 +72,7 @@ static int stm32f1_flash_write(struct target_flash *f,
#define FLASH_CR_OPTPG (1 << 4) #define FLASH_CR_OPTPG (1 << 4)
#define FLASH_CR_MER (1 << 2) #define FLASH_CR_MER (1 << 2)
#define FLASH_CR_PER (1 << 1) #define FLASH_CR_PER (1 << 1)
#define FLASH_CR_PG (1 << 0)
#define FLASH_OBR_RDPRT (1 << 1) #define FLASH_OBR_RDPRT (1 << 1)
@ -93,13 +94,6 @@ static int stm32f1_flash_write(struct target_flash *f,
#define FLASHSIZE 0x1FFFF7E0 #define FLASHSIZE 0x1FFFF7E0
#define FLASHSIZE_F0 0x1FFFF7CC #define FLASHSIZE_F0 0x1FFFF7CC
static const uint16_t stm32f1_flash_write_stub[] = {
#include "flashstub/stm32f1.stub"
};
#define SRAM_BASE 0x20000000
#define STUB_BUFFER_BASE ALIGN(SRAM_BASE + sizeof(stm32f1_flash_write_stub), 4)
static void stm32f1_add_flash(target *t, static void stm32f1_add_flash(target *t,
uint32_t addr, size_t length, size_t erasesize) uint32_t addr, size_t length, size_t erasesize)
{ {
@ -109,6 +103,7 @@ static void stm32f1_add_flash(target *t,
f->blocksize = erasesize; f->blocksize = erasesize;
f->erase = stm32f1_flash_erase; f->erase = stm32f1_flash_erase;
f->write = stm32f1_flash_write; f->write = stm32f1_flash_write;
f->buf_size = erasesize;
f->erased = 0xff; f->erased = 0xff;
target_add_flash(t, f); target_add_flash(t, f);
} }
@ -226,11 +221,24 @@ static int stm32f1_flash_write(struct target_flash *f,
target_addr dest, const void *src, size_t len) target_addr dest, const void *src, size_t len)
{ {
target *t = f->t; target *t = f->t;
/* Write stub and data to target ram and set PC */ uint32_t sr;
target_mem_write(t, SRAM_BASE, stm32f1_flash_write_stub, target_mem_write32(t, FLASH_CR, FLASH_CR_PG);
sizeof(stm32f1_flash_write_stub)); cortexm_mem_write_sized(t, dest, src, len, ALIGN_HALFWORD);
target_mem_write(t, STUB_BUFFER_BASE, src, len); /* Read FLASH_SR to poll for BSY bit */
return cortexm_run_stub(t, SRAM_BASE, dest, STUB_BUFFER_BASE, len, 0); /* Wait for completion or an error */
do {
sr = target_mem_read32(t, FLASH_SR);
if(target_check_error(t)) {
DEBUG("stm32f1 flash write: comm error\n");
return -1;
}
} while (sr & FLASH_SR_BSY);
if (sr & SR_ERROR_MASK) {
DEBUG("stm32f1 flash write error 0x%" PRIx32 "\n", sr);
return -1;
}
return 0;
} }
static bool stm32f1_cmd_erase_mass(target *t) static bool stm32f1_cmd_erase_mass(target *t)