parent
87acd99fe4
commit
90534b3cf6
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@ -39,6 +39,7 @@ static inline void _gpio_set(uint32_t gpioport, uint16_t gpios)
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{
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GPIO_BSRR(gpioport) = gpios;
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#ifdef STM32F4
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/* FIXME: Check if doubling is still needed */
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GPIO_BSRR(gpioport) = gpios;
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#endif
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}
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@ -46,11 +47,14 @@ static inline void _gpio_set(uint32_t gpioport, uint16_t gpios)
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static inline void _gpio_clear(uint32_t gpioport, uint16_t gpios)
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{
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#ifndef STM32F4
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#if defined(STM32F4)
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GPIO_BSRR(gpioport) = gpios<<16;
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/* FIXME: Check if doubling is still needed */
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GPIO_BSRR(gpioport) = gpios<<16;
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#elif defined(GPIO_BRR)
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GPIO_BRR(gpioport) = gpios;
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#else
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GPIO_BSRR(gpioport) = gpios<<16;
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GPIO_BSRR(gpioport) = gpios<<16;
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#endif
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}
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#define gpio_clear _gpio_clear
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@ -118,8 +118,14 @@ void usbuart_init(void)
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USBUSART_CR1 |= USART_CR1_IDLEIE;
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/* Setup USART TX DMA */
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#if !defined(USBUSART_TDR) && defined(USBUSART_DR)
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# define USBUSART_TDR USBUSART_DR
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#endif
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#if !defined(USBUSART_RDR) && defined(USBUSART_DR)
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# define USBUSART_RDR USBUSART_DR
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#endif
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dma_channel_reset(USBUSART_DMA_BUS, USBUSART_DMA_TX_CHAN);
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dma_set_peripheral_address(USBUSART_DMA_BUS, USBUSART_DMA_TX_CHAN, (uint32_t)&USBUSART_DR);
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dma_set_peripheral_address(USBUSART_DMA_BUS, USBUSART_DMA_TX_CHAN, (uint32_t)&USBUSART_TDR);
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dma_enable_memory_increment_mode(USBUSART_DMA_BUS, USBUSART_DMA_TX_CHAN);
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dma_set_peripheral_size(USBUSART_DMA_BUS, USBUSART_DMA_TX_CHAN, DMA_PSIZE_8BIT);
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dma_set_memory_size(USBUSART_DMA_BUS, USBUSART_DMA_TX_CHAN, DMA_MSIZE_8BIT);
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@ -136,7 +142,7 @@ void usbuart_init(void)
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/* Setup USART RX DMA */
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dma_channel_reset(USBUSART_DMA_BUS, USBUSART_DMA_RX_CHAN);
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dma_set_peripheral_address(USBUSART_DMA_BUS, USBUSART_DMA_RX_CHAN, (uint32_t)&USBUSART_DR);
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dma_set_peripheral_address(USBUSART_DMA_BUS, USBUSART_DMA_RX_CHAN, (uint32_t)&USBUSART_RDR);
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dma_set_memory_address(USBUSART_DMA_BUS, USBUSART_DMA_RX_CHAN, (uint32_t)buf_rx);
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dma_set_number_of_data(USBUSART_DMA_BUS, USBUSART_DMA_RX_CHAN, RX_FIFO_SIZE);
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dma_enable_memory_increment_mode(USBUSART_DMA_BUS, USBUSART_DMA_RX_CHAN);
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