target/stm32f1: clang-format and code styling for better readability
Signed-off-by: Rafael Silva <perigoso@riseup.net>
This commit is contained in:
Rafael Silva
Rachel Mant
parent
5666fa2a2f
commit
90ed4fe31a
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@ -45,64 +45,60 @@ static bool stm32f1_cmd_option(target *t, int argc, const char **argv);
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const struct command_s stm32f1_cmd_list[] = {
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{"erase_mass", (cmd_handler)stm32f1_cmd_erase_mass, "Erase entire flash memory"},
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{"option", (cmd_handler)stm32f1_cmd_option, "Manipulate option bytes"},
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{NULL, NULL, NULL}
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{NULL, NULL, NULL},
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};
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static int stm32f1_flash_erase(struct target_flash *f,
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target_addr addr, size_t len);
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static int stm32f1_flash_write(struct target_flash *f,
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target_addr dest, const void *src, size_t len);
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static int stm32f1_flash_erase(struct target_flash *f, target_addr addr, size_t len);
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static int stm32f1_flash_write(struct target_flash *f, target_addr dest, const void *src, size_t len);
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/* Flash Program ad Erase Controller Register Map */
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#define FPEC_BASE 0x40022000
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#define FLASH_ACR (FPEC_BASE+0x00)
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#define FLASH_KEYR (FPEC_BASE+0x04)
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#define FLASH_OPTKEYR (FPEC_BASE+0x08)
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#define FLASH_SR (FPEC_BASE+0x0C)
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#define FLASH_CR (FPEC_BASE+0x10)
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#define FLASH_AR (FPEC_BASE+0x14)
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#define FLASH_OBR (FPEC_BASE+0x1C)
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#define FLASH_WRPR (FPEC_BASE+0x20)
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#define FPEC_BASE 0x40022000
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#define FLASH_ACR (FPEC_BASE + 0x00)
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#define FLASH_KEYR (FPEC_BASE + 0x04)
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#define FLASH_OPTKEYR (FPEC_BASE + 0x08)
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#define FLASH_SR (FPEC_BASE + 0x0C)
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#define FLASH_CR (FPEC_BASE + 0x10)
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#define FLASH_AR (FPEC_BASE + 0x14)
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#define FLASH_OBR (FPEC_BASE + 0x1C)
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#define FLASH_WRPR (FPEC_BASE + 0x20)
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#define FLASH_BANK2_OFFSET 0x40
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#define FLASH_BANK_SPLIT 0x08080000
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#define FLASH_CR_OBL_LAUNCH (1<<13)
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#define FLASH_CR_OPTWRE (1 << 9)
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#define FLASH_CR_LOCK (1 << 7)
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#define FLASH_CR_STRT (1 << 6)
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#define FLASH_CR_OPTER (1 << 5)
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#define FLASH_CR_OPTPG (1 << 4)
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#define FLASH_CR_MER (1 << 2)
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#define FLASH_CR_PER (1 << 1)
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#define FLASH_CR_PG (1 << 0)
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#define FLASH_CR_OBL_LAUNCH (1 << 13)
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#define FLASH_CR_OPTWRE (1 << 9)
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#define FLASH_CR_LOCK (1 << 7)
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#define FLASH_CR_STRT (1 << 6)
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#define FLASH_CR_OPTER (1 << 5)
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#define FLASH_CR_OPTPG (1 << 4)
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#define FLASH_CR_MER (1 << 2)
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#define FLASH_CR_PER (1 << 1)
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#define FLASH_CR_PG (1 << 0)
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#define FLASH_OBR_RDPRT (1 << 1)
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#define FLASH_SR_BSY (1 << 0)
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#define FLASH_SR_BSY (1 << 0)
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#define FLASH_OBP_RDP 0x1FFFF800
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#define FLASH_OBP_RDP_KEY 0x5aa5
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#define FLASH_OBP_RDP 0x1FFFF800
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#define FLASH_OBP_RDP_KEY 0x5aa5
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#define FLASH_OBP_RDP_KEY_F3 0x55AA
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#define KEY1 0x45670123
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#define KEY2 0xCDEF89AB
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#define SR_ERROR_MASK 0x14
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#define SR_EOP 0x20
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#define SR_ERROR_MASK 0x14
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#define SR_EOP 0x20
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#define DBGMCU_IDCODE 0xE0042000
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#define DBGMCU_IDCODE_F0 0x40015800
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#define DBGMCU_IDCODE 0xE0042000
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#define DBGMCU_IDCODE_F0 0x40015800
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#define FLASHSIZE 0x1FFFF7E0
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#define FLASHSIZE_F0 0x1FFFF7CC
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#define FLASHSIZE 0x1FFFF7E0
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#define FLASHSIZE_F0 0x1FFFF7CC
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static void stm32f1_add_flash(target *t,
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uint32_t addr, size_t length, size_t erasesize)
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static void stm32f1_add_flash(target *t, uint32_t addr, size_t length, size_t erasesize)
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{
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struct target_flash *f = calloc(1, sizeof(*f));
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if (!f) { /* calloc failed: heap exhaustion */
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if (!f) { /* calloc failed: heap exhaustion */
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DEBUG_WARN("calloc: failed in %s\n", __func__);
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return;
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}
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@ -124,19 +120,22 @@ static void stm32f1_add_flash(target *t,
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bool gd32f1_probe(target *t)
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{
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uint16_t stored_idcode = t->idcode;
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if ((t->cpuid & CPUID_PARTNO_MASK) == CORTEX_M23)
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t->idcode = target_mem_read32(t, DBGMCU_IDCODE_F0) & 0xfff;
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else
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t->idcode = target_mem_read32(t, DBGMCU_IDCODE) & 0xfff;
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uint32_t signature= target_mem_read32(t, FLASHSIZE);
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uint32_t flashSize=signature & 0xFFFF;
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uint32_t ramSize=signature >>16 ;
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switch(t->idcode) {
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case 0x414: /* Gigadevice gd32f303 */
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uint32_t signature = target_mem_read32(t, FLASHSIZE);
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uint32_t flashSize = signature & 0xFFFF;
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uint32_t ramSize = signature >> 16;
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switch (t->idcode) {
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case 0x414: /* Gigadevice gd32f303 */
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case 0x430:
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t->driver = "GD32F3";
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break;
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case 0x410: /* Gigadevice gd32f103, gd32e230 */
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case 0x410: /* Gigadevice gd32f103, gd32e230 */
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if ((t->cpuid & CPUID_PARTNO_MASK) == CORTEX_M23)
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t->driver = "GD32E230";
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else
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@ -146,29 +145,34 @@ bool gd32f1_probe(target *t)
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t->idcode = stored_idcode;
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return false;
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}
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target_add_ram(t, 0x20000000, ramSize*1024);
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stm32f1_add_flash(t, 0x8000000, flashSize*1024, 0x400);
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target_add_ram(t, 0x20000000, ramSize * 1024);
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stm32f1_add_flash(t, 0x8000000, flashSize * 1024, 0x400);
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target_add_commands(t, stm32f1_cmd_list, t->driver);
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return true;
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}
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/**
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\brief identify the stm32f1 chip
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*/
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bool stm32f1_probe(target *t)
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{
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uint16_t stored_idcode = t->idcode;
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if ((t->cpuid & CPUID_PARTNO_MASK) == CORTEX_M0)
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t->idcode = target_mem_read32(t, DBGMCU_IDCODE_F0) & 0xfff;
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else
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t->idcode = target_mem_read32(t, DBGMCU_IDCODE) & 0xfff;
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size_t flash_size;
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size_t block_size = 0x400;
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switch(t->idcode) {
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switch (t->idcode) {
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case 0x29b: /* CS clone */
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case 0x410: /* Medium density */
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case 0x412: /* Low density */
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case 0x420: /* Value Line, Low-/Medium density */
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case 0x410: /* Medium density */
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case 0x412: /* Low density */
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case 0x420: /* Value Line, Low-/Medium density */
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target_add_ram(t, 0x20000000, 0x5000);
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stm32f1_add_flash(t, 0x8000000, 0x20000, 0x400);
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target_add_commands(t, stm32f1_cmd_list, "STM32 LD/MD/VL-LD/VL-MD");
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@ -183,15 +187,17 @@ bool stm32f1_probe(target *t)
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t->driver = "STM32F1 medium density";
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}
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return true;
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case 0x414: /* High density */
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case 0x418: /* Connectivity Line */
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case 0x428: /* Value Line, High Density */
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case 0x414: /* High density */
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case 0x418: /* Connectivity Line */
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case 0x428: /* Value Line, High Density */
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t->driver = "STM32F1 VL density";
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target_add_ram(t, 0x20000000, 0x10000);
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stm32f1_add_flash(t, 0x8000000, 0x80000, 0x800);
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target_add_commands(t, stm32f1_cmd_list, "STM32 HF/CL/VL-HD");
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return true;
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case 0x430: /* XL-density */
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case 0x430: /* XL-density */
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t->driver = "STM32F1 XL density";
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target_add_ram(t, 0x20000000, 0x18000);
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stm32f1_add_flash(t, 0x8000000, 0x80000, 0x800);
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@ -199,41 +205,48 @@ bool stm32f1_probe(target *t)
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target_add_commands(t, stm32f1_cmd_list, "STM32 XL/VL-XL");
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return true;
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case 0x438: /* STM32F303x6/8 and STM32F328 */
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case 0x422: /* STM32F30x */
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case 0x446: /* STM32F303xD/E and STM32F398xE */
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case 0x438: /* STM32F303x6/8 and STM32F328 */
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case 0x422: /* STM32F30x */
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case 0x446: /* STM32F303xD/E and STM32F398xE */
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target_add_ram(t, 0x10000000, 0x4000);
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/* fall through */
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case 0x432: /* STM32F37x */
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case 0x439: /* STM32F302C8 */
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case 0x432: /* STM32F37x */
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case 0x439: /* STM32F302C8 */
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t->driver = "STM32F3";
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target_add_ram(t, 0x20000000, 0x10000);
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stm32f1_add_flash(t, 0x8000000, 0x80000, 0x800);
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target_add_commands(t, stm32f1_cmd_list, "STM32F3");
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return true;
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case 0x444: /* STM32F03 RM0091 Rev.7, STM32F030x[4|6] RM0360 Rev. 4*/
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case 0x444: /* STM32F03 RM0091 Rev.7, STM32F030x[4|6] RM0360 Rev. 4*/
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t->driver = "STM32F03";
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flash_size = 0x8000;
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break;
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case 0x445: /* STM32F04 RM0091 Rev.7, STM32F070x6 RM0360 Rev. 4*/
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case 0x445: /* STM32F04 RM0091 Rev.7, STM32F070x6 RM0360 Rev. 4*/
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t->driver = "STM32F04/F070x6";
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flash_size = 0x8000;
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break;
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case 0x440: /* STM32F05 RM0091 Rev.7, STM32F030x8 RM0360 Rev. 4*/
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case 0x440: /* STM32F05 RM0091 Rev.7, STM32F030x8 RM0360 Rev. 4*/
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t->driver = "STM32F05/F030x8";
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flash_size = 0x10000;
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break;
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case 0x448: /* STM32F07 RM0091 Rev.7, STM32F070xB RM0360 Rev. 4*/
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case 0x448: /* STM32F07 RM0091 Rev.7, STM32F070xB RM0360 Rev. 4*/
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t->driver = "STM32F07";
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flash_size = 0x20000;
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block_size = 0x800;
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break;
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case 0x442: /* STM32F09 RM0091 Rev.7, STM32F030xC RM0360 Rev. 4*/
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case 0x442: /* STM32F09 RM0091 Rev.7, STM32F030xC RM0360 Rev. 4*/
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t->driver = "STM32F09/F030xC";
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flash_size = 0x40000;
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block_size = 0x800;
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break;
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default: /* NONE */
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default: /* NONE */
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t->idcode = stored_idcode;
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return false;
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}
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@ -241,6 +254,7 @@ bool stm32f1_probe(target *t)
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target_add_ram(t, 0x20000000, 0x5000);
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stm32f1_add_flash(t, 0x8000000, flash_size, block_size);
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target_add_commands(t, stm32f1_cmd_list, "STM32F0");
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return true;
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}
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@ -253,11 +267,11 @@ static int stm32f1_flash_unlock(target *t, uint32_t bank_offset)
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DEBUG_WARN("unlock failed, cr: 0x%08" PRIx32 "\n", cr);
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return -1;
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}
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return 0;
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}
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static int stm32f1_flash_erase(struct target_flash *f,
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target_addr addr, size_t len)
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static int stm32f1_flash_erase(struct target_flash *f, target_addr addr, size_t len)
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{
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target *t = f->t;
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target_addr end = addr + len - 1;
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@ -266,31 +280,36 @@ static int stm32f1_flash_erase(struct target_flash *f,
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if ((t->idcode == 0x430) && (end >= FLASH_BANK_SPLIT))
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if (stm32f1_flash_unlock(t, FLASH_BANK2_OFFSET))
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return -1;
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if (addr < FLASH_BANK_SPLIT)
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if (stm32f1_flash_unlock(t, 0))
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return -1;
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while(len) {
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while (len) {
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uint32_t bank_offset = 0;
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if (addr >= FLASH_BANK_SPLIT)
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bank_offset = FLASH_BANK2_OFFSET;
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/* Flash page erase instruction */
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target_mem_write32(t, FLASH_CR + bank_offset, FLASH_CR_PER);
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/* write address to FMA */
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target_mem_write32(t, FLASH_AR + bank_offset, addr);
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/* Flash page erase start instruction */
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target_mem_write32(t, FLASH_CR + bank_offset,
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FLASH_CR_STRT | FLASH_CR_PER);
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target_mem_write32(t, FLASH_CR + bank_offset, FLASH_CR_STRT | FLASH_CR_PER);
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/* Read FLASH_SR to poll for BSY bit */
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while (target_mem_read32(t, FLASH_SR + bank_offset) & FLASH_SR_BSY)
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if(target_check_error(t)) {
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while (target_mem_read32(t, FLASH_SR + bank_offset) & FLASH_SR_BSY) {
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if (target_check_error(t)) {
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DEBUG_WARN("stm32f1 flash erase: comm error\n");
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return -1;
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}
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}
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if (len > f->blocksize)
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len -= f->blocksize;
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else
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len = 0;
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addr += f->blocksize;
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}
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@ -309,27 +328,30 @@ static int stm32f1_flash_erase(struct target_flash *f,
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return -1;
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}
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}
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return 0;
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}
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static int stm32f1_flash_write(struct target_flash *f,
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target_addr dest, const void *src, size_t len)
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static int stm32f1_flash_write(struct target_flash *f, target_addr dest, const void *src, size_t len)
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{
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target *t = f->t;
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uint32_t sr;
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size_t length = 0;
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if (dest < FLASH_BANK_SPLIT) {
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if ((dest + len - 1) >= FLASH_BANK_SPLIT)
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length = FLASH_BANK_SPLIT - dest;
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else
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length = len;
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target_mem_write32(t, FLASH_CR, FLASH_CR_PG);
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cortexm_mem_write_sized(t, dest, src, length, ALIGN_HALFWORD);
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/* Read FLASH_SR to poll for BSY bit */
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/* Wait for completion or an error */
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do {
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sr = target_mem_read32(t, FLASH_SR);
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if(target_check_error(t)) {
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if (target_check_error(t)) {
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DEBUG_WARN("stm32f1 flash write: comm error\n");
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return -1;
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}
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@ -342,6 +364,7 @@ static int stm32f1_flash_write(struct target_flash *f,
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dest += length;
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src += length;
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}
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length = len - length;
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if ((t->idcode == 0x430) && length) { /* Write on bank 2 */
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target_mem_write32(t, FLASH_CR + FLASH_BANK2_OFFSET, FLASH_CR_PG);
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@ -350,7 +373,7 @@ static int stm32f1_flash_write(struct target_flash *f,
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/* Wait for completion or an error */
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do {
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sr = target_mem_read32(t, FLASH_SR + FLASH_BANK2_OFFSET);
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if(target_check_error(t)) {
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if (target_check_error(t)) {
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DEBUG_WARN("stm32f1 flash bank2 write: comm error\n");
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return -1;
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}
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@ -361,6 +384,7 @@ static int stm32f1_flash_write(struct target_flash *f,
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return -1;
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}
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}
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return 0;
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}
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@ -368,6 +392,7 @@ static bool stm32f1_cmd_erase_mass(target *t, int argc, const char **argv)
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{
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(void)argc;
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(void)argv;
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if (stm32f1_flash_unlock(t, 0))
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return false;
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@ -377,31 +402,33 @@ static bool stm32f1_cmd_erase_mass(target *t, int argc, const char **argv)
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/* Read FLASH_SR to poll for BSY bit */
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while (target_mem_read32(t, FLASH_SR) & FLASH_SR_BSY)
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if(target_check_error(t))
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if (target_check_error(t))
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return false;
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/* Check for error */
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uint16_t sr = target_mem_read32(t, FLASH_SR);
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if ((sr & SR_ERROR_MASK) || !(sr & SR_EOP))
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return false;
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if (t->idcode == 0x430) {
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||||
if (stm32f1_flash_unlock(t, FLASH_BANK2_OFFSET))
|
||||
return false;
|
||||
|
||||
/* Flash mass erase start instruction on bank 2*/
|
||||
target_mem_write32(t, FLASH_CR + FLASH_BANK2_OFFSET, FLASH_CR_MER);
|
||||
target_mem_write32(t, FLASH_CR + FLASH_BANK2_OFFSET,
|
||||
FLASH_CR_STRT | FLASH_CR_MER);
|
||||
target_mem_write32(t, FLASH_CR + FLASH_BANK2_OFFSET, FLASH_CR_STRT | FLASH_CR_MER);
|
||||
|
||||
/* Read FLASH_SR to poll for BSY bit */
|
||||
while (target_mem_read32(t, FLASH_SR + FLASH_BANK2_OFFSET) & FLASH_SR_BSY)
|
||||
if(target_check_error(t))
|
||||
if (target_check_error(t))
|
||||
return false;
|
||||
|
||||
/* Check for error */
|
||||
sr = target_mem_read32(t, FLASH_SR + FLASH_BANK2_OFFSET);
|
||||
if ((sr & SR_ERROR_MASK) || !(sr & SR_EOP))
|
||||
return false;
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
|
|
@ -409,12 +436,13 @@ static bool stm32f1_option_erase(target *t)
|
|||
{
|
||||
/* Erase option bytes instruction */
|
||||
target_mem_write32(t, FLASH_CR, FLASH_CR_OPTER | FLASH_CR_OPTWRE);
|
||||
target_mem_write32(t, FLASH_CR,
|
||||
FLASH_CR_STRT | FLASH_CR_OPTER | FLASH_CR_OPTWRE);
|
||||
target_mem_write32(t, FLASH_CR, FLASH_CR_STRT | FLASH_CR_OPTER | FLASH_CR_OPTWRE);
|
||||
|
||||
/* Read FLASH_SR to poll for BSY bit */
|
||||
while (target_mem_read32(t, FLASH_SR) & FLASH_SR_BSY)
|
||||
if(target_check_error(t))
|
||||
if (target_check_error(t))
|
||||
return false;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
|
|
@ -422,13 +450,15 @@ static bool stm32f1_option_write_erased(target *t, uint32_t addr, uint16_t value
|
|||
{
|
||||
if (value == 0xffff)
|
||||
return true;
|
||||
|
||||
/* Erase option bytes instruction */
|
||||
target_mem_write32(t, FLASH_CR, FLASH_CR_OPTPG | FLASH_CR_OPTWRE);
|
||||
target_mem_write16(t, addr, value);
|
||||
/* Read FLASH_SR to poll for BSY bit */
|
||||
while (target_mem_read32(t, FLASH_SR) & FLASH_SR_BSY)
|
||||
if(target_check_error(t))
|
||||
if (target_check_error(t))
|
||||
return false;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
|
|
@ -439,12 +469,12 @@ static bool stm32f1_option_write(target *t, uint32_t addr, uint16_t value)
|
|||
|
||||
index = (addr - FLASH_OBP_RDP) / 2;
|
||||
if ((index < 0) || (index > 7))
|
||||
return false;
|
||||
return false;
|
||||
/* Retrieve old values */
|
||||
for (i = 0; i < 16; i = i +4) {
|
||||
uint32_t val = target_mem_read32(t, FLASH_OBP_RDP + i);
|
||||
opt_val[i/2] = val & 0xffff;
|
||||
opt_val[i/2 +1] = val >> 16;
|
||||
for (i = 0; i < 16; i = i + 4) {
|
||||
uint32_t val = target_mem_read32(t, FLASH_OBP_RDP + i);
|
||||
opt_val[i / 2] = val & 0xffff;
|
||||
opt_val[i / 2 + 1] = val >> 16;
|
||||
}
|
||||
if (opt_val[index] == value)
|
||||
return true;
|
||||
|
|
@ -455,8 +485,7 @@ static bool stm32f1_option_write(target *t, uint32_t addr, uint16_t value)
|
|||
opt_val[index] = value;
|
||||
/* Write changed values*/
|
||||
for (i = 0; i < 8; i++)
|
||||
if (!(stm32f1_option_write_erased
|
||||
(t, FLASH_OBP_RDP + i*2,opt_val[i])))
|
||||
if (!(stm32f1_option_write_erased(t, FLASH_OBP_RDP + i * 2, opt_val[i])))
|
||||
return false;
|
||||
return true;
|
||||
}
|
||||
|
|
@ -467,22 +496,26 @@ static bool stm32f1_cmd_option(target *t, int argc, const char **argv)
|
|||
uint32_t flash_obp_rdp_key;
|
||||
uint32_t rdprt;
|
||||
|
||||
switch(t->idcode) {
|
||||
case 0x422: /* STM32F30x */
|
||||
case 0x432: /* STM32F37x */
|
||||
case 0x438: /* STM32F303x6/8 and STM32F328 */
|
||||
case 0x440: /* STM32F0 */
|
||||
case 0x446: /* STM32F303xD/E and STM32F398xE */
|
||||
case 0x445: /* STM32F04 RM0091 Rev.7, STM32F070x6 RM0360 Rev. 4*/
|
||||
case 0x448: /* STM32F07 RM0091 Rev.7, STM32F070xB RM0360 Rev. 4*/
|
||||
case 0x442: /* STM32F09 RM0091 Rev.7, STM32F030xC RM0360 Rev. 4*/
|
||||
switch (t->idcode) {
|
||||
case 0x422: /* STM32F30x */
|
||||
case 0x432: /* STM32F37x */
|
||||
case 0x438: /* STM32F303x6/8 and STM32F328 */
|
||||
case 0x440: /* STM32F0 */
|
||||
case 0x446: /* STM32F303xD/E and STM32F398xE */
|
||||
case 0x445: /* STM32F04 RM0091 Rev.7, STM32F070x6 RM0360 Rev. 4*/
|
||||
case 0x448: /* STM32F07 RM0091 Rev.7, STM32F070xB RM0360 Rev. 4*/
|
||||
case 0x442: /* STM32F09 RM0091 Rev.7, STM32F030xC RM0360 Rev. 4*/
|
||||
flash_obp_rdp_key = FLASH_OBP_RDP_KEY_F3;
|
||||
break;
|
||||
default: flash_obp_rdp_key = FLASH_OBP_RDP_KEY;
|
||||
default:
|
||||
flash_obp_rdp_key = FLASH_OBP_RDP_KEY;
|
||||
}
|
||||
|
||||
rdprt = target_mem_read32(t, FLASH_OBR) & FLASH_OBR_RDPRT;
|
||||
|
||||
if (stm32f1_flash_unlock(t, 0))
|
||||
return false;
|
||||
|
||||
target_mem_write32(t, FLASH_OPTKEYR, KEY1);
|
||||
target_mem_write32(t, FLASH_OPTKEYR, KEY2);
|
||||
|
||||
|
|
@ -517,5 +550,6 @@ static bool stm32f1_cmd_option(target *t, int argc, const char **argv)
|
|||
tc_printf(t, "0x%08X: 0x%04X\n", addr, val & 0xFFFF);
|
||||
tc_printf(t, "0x%08X: 0x%04X\n", addr + 2, val >> 16);
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue