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Cleaned up some magic numbers in adiv5*

This commit is contained in:
Gareth McMullin 2011-03-05 23:43:03 +13:00
parent a139aae479
commit 91815f2d23
4 changed files with 118 additions and 55 deletions
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81
src/adiv5.c
View File

@ -42,14 +42,6 @@
#define DO_RESET_SEQ 0
#endif
/* Bits in the DP_CTRLSTAT register */
#define CSYSPWRUPACK 0x80000000L
#define CSYSPWRUPREQ 0x40000000L
#define CDBGPWRUPACK 0x20000000L
#define CDBGPWRUPREQ 0x10000000L
#define CDBGRSTACK 0x08000000L
#define CDBGRSTREQ 0x04000000L
/* This belongs elsewhere... */
target *target_list = NULL;
target *cur_target = NULL;
@ -94,13 +86,16 @@ void adiv5_dp_init(ADIv5_DP_t *dp)
dp->next = adiv5_dp_list;
adiv5_dp_list = dp;
ctrlstat = adiv5_dp_read(dp, DP_CTRLSTAT);
ctrlstat = adiv5_dp_read(dp, ADIV5_DP_CTRLSTAT);
/* Write request for system and debug power up */
adiv5_dp_write(dp, DP_CTRLSTAT, ctrlstat |= CSYSPWRUPREQ | CDBGPWRUPREQ);
adiv5_dp_write(dp, ADIV5_DP_CTRLSTAT,
ctrlstat |= ADIV5_DP_CTRLSTAT_CSYSPWRUPREQ |
ADIV5_DP_CTRLSTAT_CDBGPWRUPREQ);
/* Wait for acknowledge */
while(((ctrlstat = adiv5_dp_read(dp, DP_CTRLSTAT)) &
(CSYSPWRUPACK | CDBGPWRUPACK)) != (CSYSPWRUPACK | CDBGPWRUPACK));
while(((ctrlstat = adiv5_dp_read(dp, ADIV5_DP_CTRLSTAT)) &
(ADIV5_DP_CTRLSTAT_CSYSPWRUPACK | ADIV5_DP_CTRLSTAT_CDBGPWRUPACK)) !=
(ADIV5_DP_CTRLSTAT_CSYSPWRUPACK | ADIV5_DP_CTRLSTAT_CDBGPWRUPACK));
if(DO_RESET_SEQ) {
/* This AP reset logic is described in ADIv5, but fails to work
@ -109,21 +104,25 @@ void adiv5_dp_init(ADIv5_DP_t *dp)
*/
/* Write request for debug reset */
adiv5_dp_write(dp, DP_CTRLSTAT, ctrlstat |= CDBGRSTREQ);
adiv5_dp_write(dp, ADIV5_DP_CTRLSTAT,
ctrlstat |= ADIV5_DP_CTRLSTAT_CDBGRSTREQ);
/* Wait for acknowledge */
while(!((ctrlstat = adiv5_dp_read(dp, DP_CTRLSTAT)) & CDBGRSTACK));
while(!((ctrlstat = adiv5_dp_read(dp, ADIV5_DP_CTRLSTAT)) &
ADIV5_DP_CTRLSTAT_CDBGRSTACK));
/* Write request for debug reset release */
adiv5_dp_write(dp, DP_CTRLSTAT, ctrlstat &= ~CDBGRSTREQ);
adiv5_dp_write(dp, ADIV5_DP_CTRLSTAT,
ctrlstat &= ~ADIV5_DP_CTRLSTAT_CDBGRSTREQ);
/* Wait for acknowledge */
while(adiv5_dp_read(dp, DP_CTRLSTAT) & CDBGRSTACK);
while(adiv5_dp_read(dp, ADIV5_DP_CTRLSTAT) &
ADIV5_DP_CTRLSTAT_CDBGRSTACK);
}
/* Probe for APs on this DP */
for(int i = 0; i < 256; i++) {
uint32_t idr;
adiv5_dp_write(dp, DP_SELECT, ((uint32_t)i << 24) | 0xF0);
adiv5_dp_write(dp, ADIV5_DP_SELECT, ((uint32_t)i << 24) | 0xF0);
idr = adiv5_dp_read_ap(dp, 0x0C); /* attempt to read IDR */
if(idr) { /* We have a valid AP, adding to list */
@ -173,13 +172,13 @@ ap_mem_read_words(struct target_s *target, uint32_t *dest, uint32_t src, int len
len >>= 2;
adiv5_ap_write(t->ap, 0x00, 0xA2000052);
adiv5_dp_low_access(t->ap->dp, 1, 0, 0x04, src);
adiv5_dp_low_access(t->ap->dp, 1, 1, 0x0C, 0);
adiv5_ap_write(t->ap, ADIV5_AP_CSW, 0xA2000052);
adiv5_dp_low_access(t->ap->dp, 1, 0, ADIV5_AP_TAR, src);
adiv5_dp_low_access(t->ap->dp, 1, 1, ADIV5_AP_DRW, 0);
while(--len)
*dest++ = adiv5_dp_low_access(t->ap->dp, 1, 1, 0x0C, 0);
*dest++ = adiv5_dp_low_access(t->ap->dp, 1, 1, ADIV5_AP_DRW, 0);
*dest++ = adiv5_dp_low_access(t->ap->dp, 0, 1, DP_RDBUFF, 0);
*dest++ = adiv5_dp_low_access(t->ap->dp, 0, 1, ADIV5_DP_RDBUFF, 0);
return 0;
}
@ -190,14 +189,14 @@ ap_mem_read_bytes(struct target_s *target, uint8_t *dest, uint32_t src, int len)
struct target_ap_s *t = (void *)target;
uint32_t tmp = src;
adiv5_ap_write(t->ap, 0x00, 0xA2000050);
adiv5_dp_low_access(t->ap->dp, 1, 0, 0x04, src);
adiv5_dp_low_access(t->ap->dp, 1, 1, 0x0C, 0);
adiv5_ap_write(t->ap, ADIV5_AP_CSW, 0xA2000050);
adiv5_dp_low_access(t->ap->dp, 1, 0, ADIV5_AP_TAR, src);
adiv5_dp_low_access(t->ap->dp, 1, 1, ADIV5_AP_DRW, 0);
while(--len) {
tmp = adiv5_dp_low_access(t->ap->dp, 1, 1, 0x0C, 0);
tmp = adiv5_dp_low_access(t->ap->dp, 1, 1, ADIV5_AP_DRW, 0);
*dest++ = (tmp >> ((src++ & 0x3) << 3) & 0xFF);
}
tmp = adiv5_dp_low_access(t->ap->dp, 0, 1, DP_RDBUFF, 0);
tmp = adiv5_dp_low_access(t->ap->dp, 0, 1, ADIV5_DP_RDBUFF, 0);
*dest++ = (tmp >> ((src++ & 0x3) << 3) & 0xFF);
return 0;
@ -211,10 +210,10 @@ ap_mem_write_words(struct target_s *target, uint32_t dest, const uint32_t *src,
len >>= 2;
adiv5_ap_write(t->ap, 0x00, 0xA2000052);
adiv5_dp_low_access(t->ap->dp, 1, 0, 0x04, dest);
adiv5_ap_write(t->ap, ADIV5_AP_CSW, 0xA2000052);
adiv5_dp_low_access(t->ap->dp, 1, 0, ADIV5_AP_TAR, dest);
while(len--)
adiv5_dp_low_access(t->ap->dp, 1, 0, 0x0C, *src++);
adiv5_dp_low_access(t->ap->dp, 1, 0, ADIV5_AP_DRW, *src++);
return 0;
}
@ -225,11 +224,11 @@ ap_mem_write_bytes(struct target_s *target, uint32_t dest, const uint8_t *src, i
struct target_ap_s *t = (void *)target;
uint32_t tmp;
adiv5_ap_write(t->ap, 0x00, 0xA2000050);
adiv5_dp_low_access(t->ap->dp, 1, 0, 0x04, dest);
adiv5_ap_write(t->ap, ADIV5_AP_CSW, 0xA2000050);
adiv5_dp_low_access(t->ap->dp, 1, 0, ADIV5_AP_TAR, dest);
while(len--) {
tmp = (uint32_t)*src++ << ((dest++ & 3) << 3);
adiv5_dp_low_access(t->ap->dp, 1, 0, 0x0C, tmp);
adiv5_dp_low_access(t->ap->dp, 1, 0, ADIV5_AP_DRW, tmp);
}
return 0;
}
@ -238,21 +237,21 @@ ap_mem_write_bytes(struct target_s *target, uint32_t dest, const uint8_t *src, i
uint32_t adiv5_ap_mem_read(ADIv5_AP_t *ap, uint32_t addr)
{
adiv5_ap_write(ap, 0x00, 0xA2000052);
adiv5_ap_write(ap, 0x04, addr);
return adiv5_ap_read(ap, 0x0C);
adiv5_ap_write(ap, ADIV5_AP_CSW, 0xA2000052);
adiv5_ap_write(ap, ADIV5_AP_TAR, addr);
return adiv5_ap_read(ap, ADIV5_AP_DRW);
}
void adiv5_ap_mem_write(ADIv5_AP_t *ap, uint32_t addr, uint32_t value)
{
adiv5_ap_write(ap, 0x00, 0xA2000052);
adiv5_ap_write(ap, 0x04, addr);
adiv5_ap_write(ap, 0x0C, value);
adiv5_ap_write(ap, ADIV5_AP_CSW, 0xA2000052);
adiv5_ap_write(ap, ADIV5_AP_TAR, addr);
adiv5_ap_write(ap, ADIV5_AP_DRW, value);
}
void adiv5_ap_write(ADIv5_AP_t *ap, uint8_t addr, uint32_t value)
{
adiv5_dp_write(ap->dp, DP_SELECT,
adiv5_dp_write(ap->dp, ADIV5_DP_SELECT,
((uint32_t)ap->apsel << 24)|(addr & 0xF0));
adiv5_dp_write_ap(ap->dp, addr, value);
}
@ -260,7 +259,7 @@ void adiv5_ap_write(ADIv5_AP_t *ap, uint8_t addr, uint32_t value)
uint32_t adiv5_ap_read(ADIv5_AP_t *ap, uint8_t addr)
{
uint32_t ret;
adiv5_dp_write(ap->dp, DP_SELECT,
adiv5_dp_write(ap->dp, ADIV5_DP_SELECT,
((uint32_t)ap->apsel << 24)|(addr & 0xF0));
ret = adiv5_dp_read_ap(ap->dp, addr);
return ret;

8
src/adiv5_jtagdp.c
View File

@ -78,7 +78,7 @@ static void adiv5_jtagdp_write(ADIv5_DP_t *dp, uint8_t addr, uint32_t value)
static uint32_t adiv5_jtagdp_read(ADIv5_DP_t *dp, uint8_t addr)
{
adiv5_jtagdp_low_access(dp, 0, 1, addr, 0);
return adiv5_jtagdp_low_access(dp, 0, 1, DP_RDBUFF, 0);
return adiv5_jtagdp_low_access(dp, 0, 1, ADIV5_DP_RDBUFF, 0);
}
static void adiv5_jtagdp_write_ap(ADIv5_DP_t *dp, uint8_t addr, uint32_t value)
@ -89,13 +89,13 @@ static void adiv5_jtagdp_write_ap(ADIv5_DP_t *dp, uint8_t addr, uint32_t value)
static uint32_t adiv5_jtagdp_read_ap(ADIv5_DP_t *dp, uint8_t addr)
{
adiv5_jtagdp_low_access(dp, 1, 1, addr, 0);
return adiv5_jtagdp_low_access(dp, 0, 1, DP_RDBUFF, 0);
return adiv5_jtagdp_low_access(dp, 0, 1, ADIV5_DP_RDBUFF, 0);
}
static uint32_t adiv5_jtagdp_error(ADIv5_DP_t *dp)
{
adiv5_jtagdp_low_access(dp, 0, 1, DP_CTRLSTAT, 0);
return adiv5_jtagdp_low_access(dp, 0, 0, DP_CTRLSTAT, 0xF0000032) & 0x32;
adiv5_jtagdp_low_access(dp, 0, 1, ADIV5_DP_CTRLSTAT, 0);
return adiv5_jtagdp_low_access(dp, 0, 0, ADIV5_DP_CTRLSTAT, 0xF0000032) & 0x32;
}
static uint32_t adiv5_jtagdp_low_access(ADIv5_DP_t *dp, uint8_t APnDP, uint8_t RnW,

17
src/adiv5_swdp.c
View File

@ -107,7 +107,7 @@ static uint32_t adiv5_swdp_read_ap(ADIv5_DP_t *dp, uint8_t addr)
uint32_t ret;
adiv5_swdp_low_access(dp, 1, 1, addr, 0);
ret = adiv5_swdp_low_access(dp, 0, 1, DP_RDBUFF, 0);
ret = adiv5_swdp_low_access(dp, 0, 1, ADIV5_DP_RDBUFF, 0);
return ret;
}
@ -116,13 +116,18 @@ static uint32_t adiv5_swdp_error(ADIv5_DP_t *dp)
{
uint32_t err, clr = 0;
err = adiv5_swdp_read(dp, DP_CTRLSTAT) & 0x32;
err = adiv5_swdp_read(dp, ADIV5_DP_CTRLSTAT) &
(ADIV5_DP_CTRLSTAT_STICKYORUN | ADIV5_DP_CTRLSTAT_STICKYCMP |
ADIV5_DP_CTRLSTAT_STICKYERR);
if(err & 0x02) clr |= 0x10; /* STICKORUN */
if(err & 0x10) clr |= 0x02; /* STICKCMP */
if(err & 0x20) clr |= 0x04; /* STICKERR */
if(err & ADIV5_DP_CTRLSTAT_STICKYORUN)
clr |= ADIV5_DP_ABORT_ORUNERRCLR;
if(err & ADIV5_DP_CTRLSTAT_STICKYCMP)
clr |= ADIV5_DP_ABORT_STKCMPCLR;
if(err & ADIV5_DP_CTRLSTAT_STICKYERR)
clr |= ADIV5_DP_ABORT_STKERRCLR;
adiv5_swdp_write(dp, DP_ABORT, clr);
adiv5_swdp_write(dp, ADIV5_DP_ABORT, clr);
dp->fault = 0;
return err;

67
src/include/adiv5.h
View File

@ -25,10 +25,69 @@
#include "jtag_scan.h"
#include "target.h"
#define DP_ABORT 0x0
#define DP_CTRLSTAT 0x4
#define DP_SELECT 0x8
#define DP_RDBUFF 0xC
/* ADIv5 DP Register addresses */
#define ADIV5_DP_IDCODE 0x0
#define ADIV5_DP_ABORT 0x0
#define ADIV5_DP_CTRLSTAT 0x4
#define ADIV5_DP_SELECT 0x8
#define ADIV5_DP_RDBUFF 0xC
/* AP Abort Register (ABORT) */
/* Bits 31:5 - Reserved */
#define ADIV5_DP_ABORT_ORUNERRCLR (1 << 4)
#define ADIV5_DP_ABORT_WDERRCLR (1 << 3)
#define ADIV5_DP_ABORT_STKERRCLR (1 << 2)
#define ADIV5_DP_ABORT_STKCMPCLR (1 << 1)
/* Bits 5:1 - SW-DP only, reserved in JTAG-DP */
#define ADIV5_DP_ABORT_DAPABORT (1 << 0)
/* Control/Status Register (CTRLSTAT) */
#define ADIV5_DP_CTRLSTAT_CSYSPWRUPACK (1u << 31)
#define ADIV5_DP_CTRLSTAT_CSYSPWRUPREQ (1u << 30)
#define ADIV5_DP_CTRLSTAT_CDBGPWRUPACK (1u << 29)
#define ADIV5_DP_CTRLSTAT_CDBGPWRUPREQ (1u << 28)
#define ADIV5_DP_CTRLSTAT_CDBGRSTACK (1u << 27)
#define ADIV5_DP_CTRLSTAT_CDBGRSTREQ (1u << 26)
/* Bits 25:24 - Reserved */
/* Bits 23:12 - TRNCNT */
#define ADIV5_DP_CTRLSTAT_TRNCNT
/* Bits 11:8 - MASKLANE */
#define ADIV5_DP_CTRLSTAT_MASKLANE
/* Bits 7:6 - Reserved in JTAG-DP */
#define ADIV5_DP_CTRLSTAT_WDATAERR (1u << 7)
#define ADIV5_DP_CTRLSTAT_READOK (1u << 6)
#define ADIV5_DP_CTRLSTAT_STICKYERR (1u << 5)
#define ADIV5_DP_CTRLSTAT_STICKYCMP (1u << 4)
#define ADIV5_DP_CTRLSTAT_TRNMODE_MASK (3u << 2)
#define ADIV5_DP_CTRLSTAT_STICKYORUN (1u << 1)
#define ADIV5_DP_CTRLSTAT_ORUNDETECT (1u << 0)
/* ADIv5 MEM-AP Registers */
#define ADIV5_AP_CSW 0x00
#define ADIV5_AP_TAR 0x04
/* 0x08 - Reserved */
#define ADIV5_AP_DRW 0x0C
#define ADIV5_AP_DB(x) (0x10 + (4*(x)))
/* 0x20:0xF0 - Reserved */
#define ADIV5_AP_CFG 0xF4
#define ADIV5_AP_BASE 0xF8
#define ADIV5_AP_IDR 0xFC
/* AP Control and Status Word (CSW) */
#define ADIV5_AP_CSW_DBGSWENABLE (1u << 31)
/* Bits 30:24 - Prot (Implementation defined) */
#define ADIV5_AP_CSW_SPIDEN (1u << 23)
/* Bits 22:12 - Reserved */
/* Bits 11:8 - Mode, must be zero */
#define ADIV5_AP_CSW_TRINPROG (1u << 7)
#define ADIV5_AP_CSW_DEVICEEN (1u << 6)
#define ADIV5_AP_CSW_ADDRINC_SINGLE (1u << 4)
/* Bit 3 - Reserved */
#define ADIV5_AP_CSW_SIZE_BYTE (0u << 0)
#define ADIV5_AP_CSW_SIZE_HALFWORD (1u << 0)
#define ADIV5_AP_CSW_SIZE_WORD (2u << 0)
#define ADIV5_AP_CSW_SIZE_MASK (7u << 0)
/* Try to keep this somewhat absract for later adding SW-DP */