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target/stm32: Use t->idcode with probe.

This commit is contained in:
Uwe Bonnes 2020-09-30 19:03:34 +02:00
parent 44bfb62715
commit 91d1ef8bf6
6 changed files with 12 additions and 39 deletions
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3
src/target/adiv5.h
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@ -86,6 +86,9 @@
#define ADIV5_AP_BASE ADIV5_AP_REG(0xF8)
#define ADIV5_AP_IDR ADIV5_AP_REG(0xFC)
/* Known designers seen in SYSROM-PIDR. Ignore Bit 7 from the designer bits*/
#define AP_DESIGNER_ARM 0x43b
/* AP Control and Status Word (CSW) */
#define ADIV5_AP_CSW_DBGSWENABLE (1u << 31)
/* Bits 30:24 - Prot, Implementation defined, for Cortex-M3: */

7
src/target/stm32f1.c
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@ -118,9 +118,10 @@ static void stm32f1_add_flash(target *t,
bool stm32f1_probe(target *t)
{
if (t->t_designer == AP_DESIGNER_ARM)
t->idcode = target_mem_read32(t, DBGMCU_IDCODE) & 0xfff;
size_t flash_size;
size_t block_size = 0x400;
t->idcode = target_mem_read32(t, DBGMCU_IDCODE) & 0xfff;
switch(t->idcode) {
case 0x410: /* Medium density */
case 0x412: /* Low density */
@ -167,10 +168,6 @@ bool stm32f1_probe(target *t)
stm32f1_add_flash(t, 0x8000000, 0x80000, 0x800);
target_add_commands(t, stm32f1_cmd_list, "STM32F3");
return true;
}
t->idcode = target_mem_read32(t, DBGMCU_IDCODE_F0) & 0xfff;
switch(t->idcode) {
case 0x444: /* STM32F03 RM0091 Rev.7, STM32F030x[4|6] RM0360 Rev. 4*/
t->driver = "STM32F03";
flash_size = 0x8000;

16
src/target/stm32f4.c
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@ -204,22 +204,15 @@ static void stm32f7_detach(target *t)
bool stm32f4_probe(target *t)
{
ADIv5_AP_t *ap = cortexm_ap(t);
uint32_t idcode;
idcode = (ap->dp->targetid >> 16) & 0xfff;
if (!idcode)
idcode = target_mem_read32(t, DBGMCU_IDCODE) & 0xFFF;
if (idcode == ID_STM32F20X) {
if (t->idcode == ID_STM32F20X) {
/* F405 revision A have a wrong IDCODE, use ARM_CPUID to make the
* distinction with F205. Revision is also wrong (0x2000 instead
* of 0x1000). See F40x/F41x errata. */
uint32_t cpuid = target_mem_read32(t, ARM_CPUID);
if ((cpuid & 0xFFF0) == 0xC240)
idcode = ID_STM32F40X;
t->idcode = ID_STM32F40X;
}
switch(idcode) {
switch(t->idcode) {
case ID_STM32F74X: /* F74x RM0385 Rev.4 */
case ID_STM32F76X: /* F76x F77x RM0410 */
case ID_STM32F72X: /* F72x F73x RM0431 */
@ -235,8 +228,7 @@ bool stm32f4_probe(target *t)
case ID_STM32F412: /* F412 RM0402 Rev.4, 256 kB Ram */
case ID_STM32F401E: /* F401 D/E RM0368 Rev.3 */
case ID_STM32F413: /* F413 RM0430 Rev.2, 320 kB Ram, 1.5 MB flash. */
t->idcode = idcode;
t->driver = stm32f4_get_chip_name(idcode);
t->driver = stm32f4_get_chip_name(t->idcode);
t->attach = stm32f4_attach;
target_add_commands(t, stm32f4_cmd_list, t->driver);
return true;

5
src/target/stm32h7.c
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@ -221,10 +221,7 @@ static void stm32h7_detach(target *t)
bool stm32h7_probe(target *t)
{
ADIv5_AP_t *ap = cortexm_ap(t);
uint32_t idcode = (ap->dp->targetid >> 16) & 0xfff;
if (idcode == ID_STM32H74x) {
t->idcode = idcode;
if (t->idcode == ID_STM32H74x) {
t->driver = stm32h74_driver_str;
t->attach = stm32h7_attach;
t->detach = stm32h7_detach;

11
src/target/stm32l0.c
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@ -268,31 +268,22 @@ static void stm32l_add_eeprom(target *t, uint32_t addr, size_t length)
STM32L0xx parts as well as the STM32L1xx's. */
bool stm32l0_probe(target* t)
{
uint32_t idcode;
idcode = target_mem_read32(t, STM32L1_DBGMCU_IDCODE_PHYS) & 0xfff;
switch (idcode) {
switch (t->idcode) {
case 0x416: /* CAT. 1 device */
case 0x429: /* CAT. 2 device */
case 0x427: /* CAT. 3 device */
case 0x436: /* CAT. 4 device */
case 0x437: /* CAT. 5 device */
t->idcode = idcode;
t->driver = "STM32L1x";
target_add_ram(t, 0x20000000, 0x14000);
stm32l_add_flash(t, 0x8000000, 0x80000, 0x100);
//stm32l_add_eeprom(t, 0x8080000, 0x4000);
target_add_commands(t, stm32lx_cmd_list, "STM32L1x");
return true;
}
idcode = target_mem_read32(t, STM32L0_DBGMCU_IDCODE_PHYS) & 0xfff;
switch (idcode) {
case 0x457: /* STM32L0xx Cat1 */
case 0x425: /* STM32L0xx Cat2 */
case 0x417: /* STM32L0xx Cat3 */
case 0x447: /* STM32L0xx Cat5 */
t->idcode = idcode;
t->driver = "STM32L0x";
target_add_ram(t, 0x20000000, 0x5000);
stm32l_add_flash(t, 0x8000000, 0x10000, 0x80);

9
src/target/stm32l4.c
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@ -373,18 +373,11 @@ static void stm32l4_detach(target *t)
bool stm32l4_probe(target *t)
{
uint32_t idcode_reg = STM32L4_DBGMCU_IDCODE_PHYS;
ADIv5_AP_t *ap = cortexm_ap(t);
if (ap->dp->idcode == 0x0BC11477)
idcode_reg = STM32G0_DBGMCU_IDCODE_PHYS;
uint32_t idcode = target_mem_read32(t, idcode_reg) & 0xfff;
struct stm32l4_info const *chip = stm32l4_get_chip_info(idcode);
struct stm32l4_info const *chip = stm32l4_get_chip_info(t->idcode);
if( !chip->idcode ) /* Not found */
return false;
t->idcode = idcode;
t->driver = chip->designator;
t->attach = stm32l4_attach;
t->detach = stm32l4_detach;