Atmel SAMD20 support
This commit is contained in:
Richard Eoin Meadows
Gareth McMullin
parent
9d9ecb572e
commit
945a2802d5
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@ -31,6 +31,7 @@ SRC = \
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nrf51.c \
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platform.c \
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sam3x.c \
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samd20.c \
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stm32f1.c \
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stm32f4.c \
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stm32l1.c \
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@ -384,6 +384,7 @@ cortexm_probe(struct target_s *target)
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PROBE(lpc43xx_probe);
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PROBE(sam3x_probe);
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PROBE(nrf51_probe);
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PROBE(samd20_probe);
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PROBE(lmi_probe);
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#undef PROBE
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@ -213,6 +213,7 @@ bool lpc11xx_probe(struct target_s *target);
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bool lpc43xx_probe(struct target_s *target);
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bool sam3x_probe(struct target_s *target);
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bool nrf51_probe(struct target_s *target);
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bool samd20_probe(struct target_s *target);
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#endif
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@ -0,0 +1,586 @@
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/*
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* This file is part of the Black Magic Debug project.
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*
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* Copyright (C) 2014 Richard Meadows <richardeoin>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/* This file implements Atmel SAM D20 target specific functions for
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* detecting the device, providing the XML memory map and Flash memory
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* programming.
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*/
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include "general.h"
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#include "jtagtap.h"
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#include "adiv5.h"
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#include "target.h"
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#include "command.h"
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#include "gdb_packet.h"
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static int samd20_flash_erase(struct target_s *target, uint32_t addr, int len);
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static int samd20_flash_write(struct target_s *target, uint32_t dest,
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const uint8_t *src, int len);
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static bool samd20_cmd_erase_all(target *t);
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static bool samd20_cmd_lock_flash(target *t);
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static bool samd20_cmd_unlock_flash(target *t);
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static bool samd20_cmd_read_userrow(target *t);
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static bool samd20_cmd_serial(target *t);
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static bool samd20_cmd_mbist(target *t);
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const struct command_s samd20_cmd_list[] = {
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{"erase_mass", (cmd_handler)samd20_cmd_erase_all, "Erase entire flash memory"},
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{"lock_flash", (cmd_handler)samd20_cmd_lock_flash, "Locks flash against spurious commands"},
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{"unlock_flash", (cmd_handler)samd20_cmd_unlock_flash, "Unlocks flash"},
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{"user_row", (cmd_handler)samd20_cmd_read_userrow, "Prints user row from flash"},
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{"serial", (cmd_handler)samd20_cmd_serial, "Prints serial number"},
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{"mbist", (cmd_handler)samd20_cmd_mbist, "Runs the built-in memory test"},
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{NULL, NULL, NULL}
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};
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/**
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* 256KB Flash Max., 32KB RAM Max. The smallest unit of erase is the
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* one row = 256 bytes.
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*/
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static const char samd20_xml_memory_map[] = "<?xml version=\"1.0\"?>"
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/* "<!DOCTYPE memory-map "
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" PUBLIC \"+//IDN gnu.org//DTD GDB Memory Map V1.0//EN\""
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" \"http://sourceware.org/gdb/gdb-memory-map.dtd\">"*/
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"<memory-map>"
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" <memory type=\"flash\" start=\"0x0\" length=\"0x40000\">"
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" <property name=\"blocksize\">0x100</property>"
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" </memory>"
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" <memory type=\"ram\" start=\"0x20000000\" length=\"0x8000\"/>"
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"</memory-map>";
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/* Non-Volatile Memory Controller (NVMC) Parameters */
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#define SAMD20_ROW_SIZE 256
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#define SAMD20_PAGE_SIZE 64
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/* Non-Volatile Memory Controller (NVMC) Registers */
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#define SAMD20_NVMC 0x41004000
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#define SAMD20_NVMC_CMD (SAMD20_NVMC + 0x0)
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#define SAMD20_NVMC_PARAM (SAMD20_NVMC + 0x08)
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#define SAMD20_NVMC_INTFLAG (SAMD20_NVMC + 0x14)
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#define SAMD20_NVMC_STATUS (SAMD20_NVMC + 0x18)
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#define SAMD20_NVMC_ADDRESS (SAMD20_NVMC + 0x1C)
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/* Command Register (CMD) */
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#define SAMD20_CMD_KEY 0xA500
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#define SAMD20_CMD_ERASEROW 0x0002
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#define SAMD20_CMD_WRITEPAGE 0x0004
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#define SAMD20_CMD_ERASEAUXROW 0x0005
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#define SAMD20_CMD_WRITEAUXPAGE 0x0006
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#define SAMD20_CMD_LOCK 0x0040
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#define SAMD20_CMD_UNLOCK 0x0041
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#define SAMD20_CMD_PAGEBUFFERCLEAR 0x0044
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/* Interrupt Flag Register (INTFLAG) */
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#define SAMD20_NVMC_READY (1 << 0)
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/* Non-Volatile Memory Calibration and Auxiliary Registers */
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#define SAMD20_NVM_USER_ROW_LOW 0x00804000
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#define SAMD20_NVM_USER_ROW_HIGH 0x00804004
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#define SAMD20_NVM_CALIBRATION 0x00806020
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#define SAMD20_NVM_SERIAL(n) (0x0080A00C + (0x30 * ((n + 3) / 4)) + \
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(0x4 * n))
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/* Device Service Unit (DSU) Registers */
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#define SAMD20_DSU 0x41002000
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#define SAMD20_DSU_CTRLSTAT (SAMD20_DSU + 0x0)
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#define SAMD20_DSU_ADDRESS (SAMD20_DSU + 0x4)
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#define SAMD20_DSU_LENGTH (SAMD20_DSU + 0x8)
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#define SAMD20_DSU_DID (SAMD20_DSU + 0x018)
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#define SAMD20_DSU_PID(n) (SAMD20_DSU + 0x1FE0 + \
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(0x4 * (n % 4)) - (0x10 * (n / 4)))
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#define SAMD20_DSU_CID(n) (SAMD20_DSU + 0x1FF0 + \
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(0x4 * (n % 4)))
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/* Control and Status Register (CTRLSTAT) */
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#define SAMD20_CTRL_CHIP_ERASE (1 << 4)
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#define SAMD20_CTRL_MBIST (1 << 3)
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#define SAMD20_CTRL_CRC (1 << 2)
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#define SAMD20_STATUSA_FAIL (1 << 11)
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#define SAMD20_STATUSA_CRSTEXT (1 << 9)
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#define SAMD20_STATUSA_DONE (1 << 8)
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/* Device Identification Register (DID) */
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#define SAMD20_DID_MASK 0xFFBF0000
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#define SAMD20_DID_CONST_VALUE 0x10000000
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#define SAMD20_DID_DEVSEL_MASK 0x0F
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/* Peripheral ID */
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#define SAMD20_PID_MASK 0x00F7FFFF
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#define SAMD20_PID_CONST_VALUE 0x0001FCD0
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/* Component ID */
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#define SAMD20_CID_VALUE 0xB105100D
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#define CORTEXM_PPB_BASE 0xE0000000
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#define CORTEXM_SCS_BASE (CORTEXM_PPB_BASE + 0xE000)
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#define CORTEXM_AIRCR (CORTEXM_SCS_BASE + 0xD0C)
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#define CORTEXM_CFSR (CORTEXM_SCS_BASE + 0xD28)
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#define CORTEXM_HFSR (CORTEXM_SCS_BASE + 0xD2C)
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#define CORTEXM_DFSR (CORTEXM_SCS_BASE + 0xD30)
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#define CORTEXM_CPACR (CORTEXM_SCS_BASE + 0xD88)
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#define CORTEXM_DHCSR (CORTEXM_SCS_BASE + 0xDF0)
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#define CORTEXM_DCRSR (CORTEXM_SCS_BASE + 0xDF4)
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#define CORTEXM_DCRDR (CORTEXM_SCS_BASE + 0xDF8)
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#define CORTEXM_DEMCR (CORTEXM_SCS_BASE + 0xDFC)
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/* Application Interrupt and Reset Control Register (AIRCR) */
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#define CORTEXM_AIRCR_VECTKEY (0x05FA << 16)
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/* Bits 31:16 - Read as VECTKETSTAT, 0xFA05 */
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#define CORTEXM_AIRCR_ENDIANESS (1 << 15)
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/* Bits 15:11 - Unused, reserved */
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#define CORTEXM_AIRCR_PRIGROUP (7 << 8)
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/* Bits 7:3 - Unused, reserved */
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#define CORTEXM_AIRCR_SYSRESETREQ (1 << 2)
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#define CORTEXM_AIRCR_VECTCLRACTIVE (1 << 1)
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#define CORTEXM_AIRCR_VECTRESET (1 << 0)
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/* Debug Fault Status Register (DFSR) */
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/* Bits 31:5 - Reserved */
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#define CORTEXM_DFSR_RESETALL 0x1F
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#define CORTEXM_DFSR_EXTERNAL (1 << 4)
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#define CORTEXM_DFSR_VCATCH (1 << 3)
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#define CORTEXM_DFSR_DWTTRAP (1 << 2)
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#define CORTEXM_DFSR_BKPT (1 << 1)
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#define CORTEXM_DFSR_HALTED (1 << 0)
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/* Debug Halting Control and Status Register (DHCSR) */
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/* This key must be written to bits 31:16 for write to take effect */
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#define CORTEXM_DHCSR_DBGKEY 0xA05F0000
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/* Bits 31:26 - Reserved */
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#define CORTEXM_DHCSR_S_RESET_ST (1 << 25)
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#define CORTEXM_DHCSR_S_RETIRE_ST (1 << 24)
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/* Bits 23:20 - Reserved */
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#define CORTEXM_DHCSR_S_LOCKUP (1 << 19)
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#define CORTEXM_DHCSR_S_SLEEP (1 << 18)
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#define CORTEXM_DHCSR_S_HALT (1 << 17)
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#define CORTEXM_DHCSR_S_REGRDY (1 << 16)
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/* Bits 15:6 - Reserved */
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#define CORTEXM_DHCSR_C_SNAPSTALL (1 << 5) /* v7m only */
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/* Bit 4 - Reserved */
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#define CORTEXM_DHCSR_C_MASKINTS (1 << 3)
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#define CORTEXM_DHCSR_C_STEP (1 << 2)
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#define CORTEXM_DHCSR_C_HALT (1 << 1)
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#define CORTEXM_DHCSR_C_DEBUGEN (1 << 0)
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/* Utility */
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#define MINIMUM(a,b) ((a < b) ? a : b)
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/**
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* Reads the SAM D20 Peripheral ID
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*/
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uint64_t samd20_read_pid(struct target_s *target)
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{
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ADIv5_AP_t *ap = adiv5_target_ap(target);
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uint64_t pid = 0;
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uint8_t i, j;
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/* Five PID registers to read LSB first */
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for (i = 0, j = 0; i < 5; i++, j += 8)
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pid |= (adiv5_ap_mem_read(ap, SAMD20_DSU_PID(i)) & 0xFF) << j;
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return pid;
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}
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/**
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* Reads the SAM D20 Component ID
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*/
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uint32_t samd20_read_cid(struct target_s *target)
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{
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ADIv5_AP_t *ap = adiv5_target_ap(target);
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uint64_t cid = 0;
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uint8_t i, j;
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/* Four CID registers to read LSB first */
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for (i = 0, j = 0; i < 4; i++, j += 8)
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cid |= (adiv5_ap_mem_read(ap, SAMD20_DSU_CID(i)) & 0xFF) << j;
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return cid;
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}
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/**
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* Overloads the default cortexm reset function with a version that
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* removes the target from extended reset where required.
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*/
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static void
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samd20_reset(struct target_s *target)
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{
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ADIv5_AP_t *ap = adiv5_target_ap(target);
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jtagtap_srst(true);
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jtagtap_srst(false);
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/* Read DHCSR here to clear S_RESET_ST bit before reset */
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adiv5_ap_mem_read(ap, CORTEXM_DHCSR);
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/* Request system reset from NVIC: SRST doesn't work correctly */
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/* This could be VECTRESET: 0x05FA0001 (reset only core)
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* or SYSRESETREQ: 0x05FA0004 (system reset)
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*/
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adiv5_ap_mem_write(ap, CORTEXM_AIRCR,
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CORTEXM_AIRCR_VECTKEY | CORTEXM_AIRCR_SYSRESETREQ);
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/* Exit extended reset */
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if (adiv5_ap_mem_read(ap, SAMD20_DSU_CTRLSTAT) &
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SAMD20_STATUSA_CRSTEXT) {
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/* Write bit to clear from extended reset */
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adiv5_ap_mem_write(ap, SAMD20_DSU_CTRLSTAT,
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SAMD20_STATUSA_CRSTEXT);
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}
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/* Poll for release from reset */
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while(adiv5_ap_mem_read(ap, CORTEXM_DHCSR) & CORTEXM_DHCSR_S_RESET_ST);
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/* Reset DFSR flags */
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adiv5_ap_mem_write(ap, CORTEXM_DFSR, CORTEXM_DFSR_RESETALL);
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/* Clear any target errors */
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target_check_error(target);
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}
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char variant_string[30];
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bool samd20_probe(struct target_s *target)
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{
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ADIv5_AP_t *ap = adiv5_target_ap(target);
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uint32_t cid = samd20_read_cid(target);
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uint32_t pid = samd20_read_pid(target);
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/* Check the ARM Coresight Component and Perhiperal IDs */
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if (cid == SAMD20_CID_VALUE &&
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(pid & SAMD20_PID_MASK) == SAMD20_PID_CONST_VALUE) {
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/* Read the Device ID */
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uint32_t did = adiv5_ap_mem_read(ap, SAMD20_DSU_DID);
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/* If the Device ID matches */
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if ((did & SAMD20_DID_MASK) == SAMD20_DID_CONST_VALUE) {
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uint8_t devsel = did & SAMD20_DID_DEVSEL_MASK;
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/* Pin Variant */
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char pin_variant;
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switch (devsel / 5) {
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case 0: pin_variant = 'J'; break;
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case 1: pin_variant = 'G'; break;
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case 2: pin_variant = 'E'; break;
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default: pin_variant = 'u'; break;
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}
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/* Mem Variant */
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uint8_t mem_variant = 18 - (devsel % 5);
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/* Part String */
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sprintf(variant_string, "Atmel SAMD20%c%dA",
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pin_variant, mem_variant);
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/* Setup Target */
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target->driver = variant_string;
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target->reset = samd20_reset;
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target->xml_mem_map = samd20_xml_memory_map;
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target->flash_erase = samd20_flash_erase;
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target->flash_write = samd20_flash_write;
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target_add_commands(target, samd20_cmd_list, "SAMD20");
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/* Release the target from extended reset to make attach possible */
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if (adiv5_ap_mem_read(ap, SAMD20_DSU_CTRLSTAT) &
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SAMD20_STATUSA_CRSTEXT) {
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/* Write bit to clear from extended reset */
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adiv5_ap_mem_write(ap, SAMD20_DSU_CTRLSTAT,
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SAMD20_STATUSA_CRSTEXT);
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}
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return true;
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}
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}
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return false;
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}
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/**
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* Temporary (until next reset) flash memory locking / unlocking
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*/
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static void samd20_lock_current_address(struct target_s *target)
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{
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ADIv5_AP_t *ap = adiv5_target_ap(target);
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/* Issue the unlock command */
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adiv5_ap_mem_write(ap, SAMD20_NVMC_CMD, SAMD20_CMD_KEY | SAMD20_CMD_LOCK);
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}
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static void samd20_unlock_current_address(struct target_s *target)
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{
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ADIv5_AP_t *ap = adiv5_target_ap(target);
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/* Issue the unlock command */
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adiv5_ap_mem_write(ap, SAMD20_NVMC_CMD, SAMD20_CMD_KEY | SAMD20_CMD_UNLOCK);
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}
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/**
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* Erase flash row by row
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*/
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static int samd20_flash_erase(struct target_s *target, uint32_t addr, int len)
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{
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ADIv5_AP_t *ap = adiv5_target_ap(target);
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addr &= ~(SAMD20_ROW_SIZE - 1);
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len &= ~(SAMD20_ROW_SIZE - 1);
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while (len) {
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/* Write address of first word in row to erase it */
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/* Must be shifted right for 16-bit address, see Datasheet §20.8.8 Address */
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adiv5_ap_mem_write(ap, SAMD20_NVMC_ADDRESS, addr >> 1);
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/* Unlock */
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samd20_unlock_current_address(target);
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/* Issue the erase command */
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adiv5_ap_mem_write(ap, SAMD20_NVMC_CMD, SAMD20_CMD_KEY | SAMD20_CMD_ERASEROW);
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/* Poll for NVM Ready */
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while ((adiv5_ap_mem_read(ap, SAMD20_NVMC_INTFLAG) & SAMD20_NVMC_READY) == 0)
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if(target_check_error(target))
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return -1;
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/* Lock */
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samd20_lock_current_address(target);
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addr += SAMD20_ROW_SIZE;
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len -= SAMD20_ROW_SIZE;
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}
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return 0;
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}
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/**
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* Write flash page by page
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*/
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static int samd20_flash_write(struct target_s *target, uint32_t dest,
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const uint8_t *src, int len)
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{
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ADIv5_AP_t *ap = adiv5_target_ap(target);
|
||||
|
||||
/* Find the size of our 32-bit data buffer */
|
||||
uint32_t offset = dest % 4;
|
||||
uint32_t words = (offset + len + 3) / 4;
|
||||
uint32_t data[words], i = 0;
|
||||
|
||||
/* Populate the data buffer */
|
||||
memset((uint8_t *)data, 0xFF, words * 4);
|
||||
memcpy((uint8_t *)data + offset, src, len);
|
||||
|
||||
/* The address of the first word involved in the write */
|
||||
uint32_t addr = dest & ~0x3;
|
||||
/* The address of the last word involved in the write */
|
||||
uint32_t end = (dest + len - 1) & ~0x3;
|
||||
|
||||
/* The start address of the first page involved in the write */
|
||||
uint32_t first_page = dest & ~(SAMD20_PAGE_SIZE - 1);
|
||||
/* The start address of the last page involved in the write */
|
||||
uint32_t last_page = (dest + len - 1) & ~(SAMD20_PAGE_SIZE - 1);
|
||||
uint32_t end_of_this_page;
|
||||
|
||||
|
||||
for (uint32_t page = first_page; page <= last_page; page += SAMD20_PAGE_SIZE) {
|
||||
end_of_this_page = page + (SAMD20_PAGE_SIZE - 4);
|
||||
|
||||
if (addr > page || (page == last_page && end < end_of_this_page)) {
|
||||
|
||||
/* Partial, manual page write */
|
||||
for (; addr <= MINIMUM(end, end_of_this_page); addr += 4, i++) {
|
||||
adiv5_ap_mem_write(ap, addr, data[i]);
|
||||
}
|
||||
|
||||
/* Unlock */
|
||||
samd20_unlock_current_address(target);
|
||||
|
||||
/* Issue the write page command */
|
||||
adiv5_ap_mem_write(ap, SAMD20_NVMC_CMD,
|
||||
SAMD20_CMD_KEY | SAMD20_CMD_WRITEPAGE);
|
||||
} else {
|
||||
/* Write first word to set address */
|
||||
adiv5_ap_mem_write(ap, addr, data[i]); addr += 4; i++;
|
||||
|
||||
/* Unlock */
|
||||
samd20_unlock_current_address(target);
|
||||
|
||||
/* Full, automatic page write */
|
||||
for (; addr < page + SAMD20_PAGE_SIZE; addr += 4, i++) {
|
||||
adiv5_ap_mem_write(ap, addr, data[i]);
|
||||
}
|
||||
}
|
||||
|
||||
/* Poll for NVM Ready */
|
||||
while ((adiv5_ap_mem_read(ap, SAMD20_NVMC_INTFLAG) & SAMD20_NVMC_READY) == 0)
|
||||
if(target_check_error(target))
|
||||
return -1;
|
||||
|
||||
/* Lock */
|
||||
samd20_lock_current_address(target);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* Uses the Device Service Unit to erase the entire flash
|
||||
*/
|
||||
static bool samd20_cmd_erase_all(target *t)
|
||||
{
|
||||
ADIv5_AP_t *ap = adiv5_target_ap(t);
|
||||
|
||||
/* Erase all */
|
||||
adiv5_ap_mem_write(ap, SAMD20_DSU_CTRLSTAT, SAMD20_CTRL_CHIP_ERASE);
|
||||
|
||||
/* Poll for DSU Ready */
|
||||
while ((adiv5_ap_mem_read(ap, SAMD20_DSU_CTRLSTAT) & SAMD20_STATUSA_DONE) == 0)
|
||||
if(target_check_error(t))
|
||||
return false;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
/**
|
||||
* Sets the NVM region lock bits in the User Row. This value is read
|
||||
* at startup as the default value for the lock bits, and hence does
|
||||
* not take effect until a reset.
|
||||
*
|
||||
* 0x0000 = Lock, 0xFFFF = Unlock (default)
|
||||
*/
|
||||
static bool samd20_set_flashlock(target *t, uint16_t value)
|
||||
{
|
||||
ADIv5_AP_t *ap = adiv5_target_ap(t);
|
||||
|
||||
uint32_t high = adiv5_ap_mem_read(ap, SAMD20_NVM_USER_ROW_HIGH);
|
||||
uint32_t low = adiv5_ap_mem_read(ap, SAMD20_NVM_USER_ROW_LOW);
|
||||
|
||||
/* Write address of a word in the row to erase it */
|
||||
/* Must be shifted right for 16-bit address, see Datasheet §20.8.8 Address */
|
||||
adiv5_ap_mem_write(ap, SAMD20_NVMC_ADDRESS, SAMD20_NVM_USER_ROW_LOW >> 1);
|
||||
|
||||
/* Issue the erase command */
|
||||
adiv5_ap_mem_write(ap, SAMD20_NVMC_CMD, SAMD20_CMD_KEY | SAMD20_CMD_ERASEAUXROW);
|
||||
|
||||
/* Poll for NVM Ready */
|
||||
while ((adiv5_ap_mem_read(ap, SAMD20_NVMC_INTFLAG) & SAMD20_NVMC_READY) == 0)
|
||||
if(target_check_error(t))
|
||||
return -1;
|
||||
|
||||
/* Modify the high byte of the user row */
|
||||
high = (high & 0x0000FFFF) | ((value << 16) & 0xFFFF0000);
|
||||
|
||||
/* Write back */
|
||||
adiv5_ap_mem_write(ap, SAMD20_NVM_USER_ROW_LOW, low);
|
||||
adiv5_ap_mem_write(ap, SAMD20_NVM_USER_ROW_HIGH, high);
|
||||
|
||||
/* Issue the page write command */
|
||||
adiv5_ap_mem_write(ap, SAMD20_NVMC_CMD,
|
||||
SAMD20_CMD_KEY | SAMD20_CMD_WRITEAUXPAGE);
|
||||
|
||||
return true;
|
||||
}
|
||||
static bool samd20_cmd_lock_flash(target *t)
|
||||
{
|
||||
return samd20_set_flashlock(t, 0x0000);
|
||||
}
|
||||
static bool samd20_cmd_unlock_flash(target *t)
|
||||
{
|
||||
return samd20_set_flashlock(t, 0xFFFF);
|
||||
}
|
||||
static bool samd20_cmd_read_userrow(target *t)
|
||||
{
|
||||
ADIv5_AP_t *ap = adiv5_target_ap(t);
|
||||
|
||||
gdb_outf("User Row: 0x%08x%08x\n",
|
||||
adiv5_ap_mem_read(ap, SAMD20_NVM_USER_ROW_HIGH),
|
||||
adiv5_ap_mem_read(ap, SAMD20_NVM_USER_ROW_LOW));
|
||||
|
||||
return true;
|
||||
}
|
||||
/**
|
||||
* Reads the 128-bit serial number from the NVM
|
||||
*/
|
||||
static bool samd20_cmd_serial(target *t)
|
||||
{
|
||||
ADIv5_AP_t *ap = adiv5_target_ap(t);
|
||||
|
||||
gdb_outf("Serial Number: 0x");
|
||||
|
||||
for (uint32_t i = 0; i < 4; i++) {
|
||||
gdb_outf("%08x", adiv5_ap_mem_read(ap, SAMD20_NVM_SERIAL(i)));
|
||||
}
|
||||
|
||||
gdb_outf("\n");
|
||||
|
||||
return true;
|
||||
}
|
||||
/**
|
||||
* Returns the size (in bytes) of the current SAM D20's flash memory.
|
||||
*/
|
||||
static uint32_t samd20_flash_size(target *t)
|
||||
{
|
||||
ADIv5_AP_t *ap = adiv5_target_ap(t);
|
||||
|
||||
/* Read the Device ID */
|
||||
uint32_t did = adiv5_ap_mem_read(ap, SAMD20_DSU_DID);
|
||||
|
||||
/* Mask off the device select bits */
|
||||
uint8_t devsel = did & SAMD20_DID_DEVSEL_MASK;
|
||||
|
||||
/* Shift the maximum flash size (256KB) down as appropriate */
|
||||
return (0x40000 >> (devsel % 5));
|
||||
}
|
||||
/**
|
||||
* Runs the Memory Built In Self Test (MBIST)
|
||||
*/
|
||||
static bool samd20_cmd_mbist(target *t)
|
||||
{
|
||||
ADIv5_AP_t *ap = adiv5_target_ap(t);
|
||||
|
||||
/* Write the memory parameters to the DSU */
|
||||
adiv5_ap_mem_write(ap, SAMD20_DSU_ADDRESS, 0);
|
||||
adiv5_ap_mem_write(ap, SAMD20_DSU_LENGTH, samd20_flash_size(t));
|
||||
|
||||
/* Clear the fail bit */
|
||||
adiv5_ap_mem_write(ap, SAMD20_DSU_CTRLSTAT, SAMD20_STATUSA_FAIL);
|
||||
|
||||
/* Write the MBIST command */
|
||||
adiv5_ap_mem_write(ap, SAMD20_DSU_CTRLSTAT, SAMD20_CTRL_MBIST);
|
||||
|
||||
/* Poll for DSU Ready */
|
||||
while ((adiv5_ap_mem_read(ap, SAMD20_DSU_CTRLSTAT) & SAMD20_STATUSA_DONE) == 0)
|
||||
if(target_check_error(t))
|
||||
return false;
|
||||
|
||||
/* Test the fail bit in Status A */
|
||||
if (adiv5_ap_mem_read(ap, SAMD20_DSU_CTRLSTAT) & SAMD20_STATUSA_FAIL) {
|
||||
gdb_outf("MBIST Fail @ 0x%08x\n",
|
||||
adiv5_ap_mem_read(ap, SAMD20_DSU_ADDRESS));
|
||||
} else {
|
||||
gdb_outf("MBIST Passed!\n");
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
Loading…
Reference in New Issue