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Clean up debug format strings.

This commit is contained in:
Gareth McMullin 2016-09-25 16:07:01 -07:00
parent 966f360515
commit 9a8cef04e0
4 changed files with 16 additions and 13 deletions
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12
src/target/adiv5.c
View File

@ -270,7 +270,8 @@ static void adiv5_component_probe(ADIv5_AP_t *ap, uint32_t addr)
/* CIDR preamble sanity check */ /* CIDR preamble sanity check */
if ((cidr & ~CID_CLASS_MASK) != CID_PREAMBLE) { if ((cidr & ~CID_CLASS_MASK) != CID_PREAMBLE) {
DEBUG("0x%X: 0x%X <- does not match preamble (0x%X)\n", addr, cidr, CID_PREAMBLE); DEBUG("0x%"PRIx32": 0x%"PRIx32" <- does not match preamble (0x%X)\n",
addr, cidr, CID_PREAMBLE);
return; return;
} }
@ -293,7 +294,8 @@ static void adiv5_component_probe(ADIv5_AP_t *ap, uint32_t addr)
* any components by other designers. * any components by other designers.
*/ */
if ((pidr & ~(PIDR_REV_MASK | PIDR_PN_MASK)) != PIDR_ARM_BITS) { if ((pidr & ~(PIDR_REV_MASK | PIDR_PN_MASK)) != PIDR_ARM_BITS) {
DEBUG("0x%X: 0x%"PRIx64" <- does not match ARM JEP-106\n", addr, pidr); DEBUG("0x%"PRIx32": 0x%"PRIx64" <- does not match ARM JEP-106\n",
addr, pidr);
return; return;
} }
@ -305,7 +307,7 @@ static void adiv5_component_probe(ADIv5_AP_t *ap, uint32_t addr)
int i; int i;
for (i = 0; pidr_pn_bits[i].arch != aa_end; i++) { for (i = 0; pidr_pn_bits[i].arch != aa_end; i++) {
if (pidr_pn_bits[i].part_number == part_number) { if (pidr_pn_bits[i].part_number == part_number) {
DEBUG("0x%X: %s - %s %s\n", addr, DEBUG("0x%"PRIx32": %s - %s %s\n", addr,
cidc_debug_strings[cid_class], cidc_debug_strings[cid_class],
pidr_pn_bits[i].type, pidr_pn_bits[i].type,
pidr_pn_bits[i].full); pidr_pn_bits[i].full);
@ -334,7 +336,7 @@ static void adiv5_component_probe(ADIv5_AP_t *ap, uint32_t addr)
} }
} }
if (pidr_pn_bits[i].arch == aa_end) { if (pidr_pn_bits[i].arch == aa_end) {
DEBUG("0x%X: %s - Unknown (PIDR = 0x%"PRIx64")\n", addr, DEBUG("0x%"PRIx32": %s - Unknown (PIDR = 0x%"PRIx64")\n", addr,
cidc_debug_strings[cid_class], pidr); cidc_debug_strings[cid_class], pidr);
} }
} }
@ -377,7 +379,7 @@ ADIv5_AP_t *adiv5_new_ap(ADIv5_DP_t *dp, uint8_t apsel)
ap->csw &= ~ADIV5_AP_CSW_TRINPROG; ap->csw &= ~ADIV5_AP_CSW_TRINPROG;
} }
DEBUG(" AP %3d: IDR=%08X CFG=%08X BASE=%08X CSW=%08X\n", DEBUG(" AP %3d: IDR=%08"PRIx32" CFG=%08"PRIx32" BASE=%08"PRIx32" CSW=%08"PRIx32"\n",
apsel, ap->idr, ap->cfg, ap->base, ap->csw); apsel, ap->idr, ap->cfg, ap->base, ap->csw);
return ap; return ap;

11
src/target/cortexa.c
View File

@ -211,7 +211,8 @@ static uint32_t va_to_pa(target *t, uint32_t va)
if (par & 1) if (par & 1)
priv->mmu_fault = true; priv->mmu_fault = true;
uint32_t pa = (par & ~0xfff) | (va & 0xfff); uint32_t pa = (par & ~0xfff) | (va & 0xfff);
DEBUG("%s: VA = 0x%08X, PAR = 0x%08X, PA = 0x%08X\n", __func__, va, par, pa); DEBUG("%s: VA = 0x%08"PRIx32", PAR = 0x%08"PRIx32", PA = 0x%08"PRIX32"\n",
__func__, va, par, pa);
return pa; return pa;
} }
@ -412,7 +413,7 @@ bool cortexa_attach(target *t)
dbgdscr |= DBGDSCR_HDBGEN | DBGDSCR_ITREN; dbgdscr |= DBGDSCR_HDBGEN | DBGDSCR_ITREN;
dbgdscr = (dbgdscr & ~DBGDSCR_EXTDCCMODE_MASK) | DBGDSCR_EXTDCCMODE_STALL; dbgdscr = (dbgdscr & ~DBGDSCR_EXTDCCMODE_MASK) | DBGDSCR_EXTDCCMODE_STALL;
apb_write(t, DBGDSCR, dbgdscr); apb_write(t, DBGDSCR, dbgdscr);
DEBUG("DBGDSCR = 0x%08x\n", dbgdscr); DEBUG("DBGDSCR = 0x%08"PRIx32"\n", dbgdscr);
target_halt_request(t); target_halt_request(t);
tries = 10; tries = 10;
@ -604,7 +605,7 @@ static enum target_halt_reason cortexa_halt_poll(target *t, target_addr *watch)
if (!(dbgdscr & DBGDSCR_HALTED)) /* Not halted */ if (!(dbgdscr & DBGDSCR_HALTED)) /* Not halted */
return TARGET_HALT_RUNNING; return TARGET_HALT_RUNNING;
DEBUG("%s: DBGDSCR = 0x%08x\n", __func__, dbgdscr); DEBUG("%s: DBGDSCR = 0x%08"PRIx32"\n", __func__, dbgdscr);
/* Reenable DBGITR */ /* Reenable DBGITR */
dbgdscr |= DBGDSCR_ITREN; dbgdscr |= DBGDSCR_ITREN;
apb_write(t, DBGDSCR, dbgdscr); apb_write(t, DBGDSCR, dbgdscr);
@ -631,7 +632,7 @@ void cortexa_halt_resume(target *t, bool step)
if (step) { if (step) {
uint32_t addr = priv->reg_cache.r[15]; uint32_t addr = priv->reg_cache.r[15];
uint32_t bas = bp_bas(addr, (priv->reg_cache.cpsr & CPSR_THUMB) ? 2 : 4); uint32_t bas = bp_bas(addr, (priv->reg_cache.cpsr & CPSR_THUMB) ? 2 : 4);
DEBUG("step 0x%08x %x\n", addr, bas); DEBUG("step 0x%08"PRIx32" %"PRIx32"\n", addr, bas);
/* Set match any breakpoint */ /* Set match any breakpoint */
apb_write(t, DBGBVR(0), priv->reg_cache.r[15] & ~3); apb_write(t, DBGBVR(0), priv->reg_cache.r[15] & ~3);
apb_write(t, DBGBCR(0), DBGBCR_INST_MISMATCH | bas | apb_write(t, DBGBCR(0), DBGBCR_INST_MISMATCH | bas |
@ -658,7 +659,7 @@ void cortexa_halt_resume(target *t, bool step)
do { do {
apb_write(t, DBGDRCR, DBGDRCR_CSE | DBGDRCR_RRQ); apb_write(t, DBGDRCR, DBGDRCR_CSE | DBGDRCR_RRQ);
dbgdscr = apb_read(t, DBGDSCR); dbgdscr = apb_read(t, DBGDSCR);
DEBUG("%s: DBGDSCR = 0x%08x\n", __func__, dbgdscr); DEBUG("%s: DBGDSCR = 0x%08"PRIx32"\n", __func__, dbgdscr);
} while (!(dbgdscr & DBGDSCR_RESTARTED)); } while (!(dbgdscr & DBGDSCR_RESTARTED));
} }

4
src/target/cortexm.c
View File

@ -841,8 +841,8 @@ static int cortexm_hostio_request(target *t)
uint32_t syscall = arm_regs[0]; uint32_t syscall = arm_regs[0];
int32_t ret = 0; int32_t ret = 0;
DEBUG("syscall 0x%x (%x %x %x %x)\n", syscall, DEBUG("syscall 0"PRIx32"%"PRIx32" (%"PRIx32" %"PRIx32" %"PRIx32" %"PRIx32")\n",
params[0], params[1], params[2], params[3]); syscall, params[0], params[1], params[2], params[3]);
switch (syscall) { switch (syscall) {
case SYS_OPEN:{ /* open */ case SYS_OPEN:{ /* open */
/* Translate stupid fopen modes to open flags. /* Translate stupid fopen modes to open flags.

2
src/target/sam3x.c
View File

@ -254,7 +254,7 @@ bool sam3x_probe(target *t)
static int static int
sam3x_flash_cmd(target *t, uint32_t base, uint8_t cmd, uint16_t arg) sam3x_flash_cmd(target *t, uint32_t base, uint8_t cmd, uint16_t arg)
{ {
DEBUG("%s: base = 0x%08x cmd = 0x%02X, arg = 0x%06X\n", DEBUG("%s: base = 0x%08"PRIx32" cmd = 0x%02X, arg = 0x%06X\n",
__func__, base, cmd, arg); __func__, base, cmd, arg);
target_mem_write32(t, EEFC_FCR(base), target_mem_write32(t, EEFC_FCR(base),
EEFC_FCR_FKEY | cmd | ((uint32_t)arg << 8)); EEFC_FCR_FKEY | cmd | ((uint32_t)arg << 8));