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adiv5: Additional decoding.

This commit is contained in:
Uwe Bonnes 2020-11-07 15:44:16 +01:00 committed by UweBonnes
parent d78d7838d3
commit 9ac5adfcef
2 changed files with 8 additions and 0 deletions
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5
src/target/adiv5.c
View File

@ -608,6 +608,8 @@ ADIv5_AP_t *adiv5_new_ap(ADIv5_DP_t *dp, uint8_t apsel)
uint32_t cfg = adiv5_ap_read(ap, ADIV5_AP_CFG);
DEBUG_INFO("AP %3d: IDR=%08"PRIx32" CFG=%08"PRIx32" BASE=%08" PRIx32
" CSW=%08"PRIx32"\n", apsel, ap->idr, cfg, ap->base, ap->csw);
DEBUG_INFO("AP#0 IDR = 0x%08" PRIx32 " (AHB-AP var%x rev%x)\n",
ap->idr, (ap->idr >> 4) & 0xf, ap->idr >> 28);
#endif
adiv5_ap_ref(ap);
return ap;
@ -615,6 +617,9 @@ ADIv5_AP_t *adiv5_new_ap(ADIv5_DP_t *dp, uint8_t apsel)
void adiv5_dp_init(ADIv5_DP_t *dp)
{
DEBUG_INFO("DPIDR 0x%08" PRIx32 " (v%d %srev%d)\n", dp->idcode,
(dp->idcode >> 12) & 0xf,
(dp->idcode & 0x10000) ? "MINDP " : "", dp->idcode >> 28);
volatile uint32_t ctrlstat = 0;
#if PC_HOSTED == 1
platform_adiv5_dp_defaults(dp);

3
src/target/cortexm.c
View File

@ -329,6 +329,9 @@ bool cortexm_probe(ADIv5_AP_t *ap)
default:
DEBUG_WARN("Unexpected CortexM CPUID partno %04x\n", cpuid_partno);
}
DEBUG_INFO("CPUID 0x%08" PRIx32 " (%s var %x rev %x)\n", t->cpuid,
t->core, (t->cpuid & CPUID_REVISION_MASK) >> 20,
t->cpuid & CPUID_PATCH_MASK);
t->attach = cortexm_attach;
t->detach = cortexm_detach;