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stm32h7/f7: Store DBGMCU_CR on attach() and restore on detach(). 

On STM32[FH]7, DBG_SLEEP must be set for debugging.
This commit is contained in:
Uwe Bonnes 2018-09-10 22:58:49 +02:00 committed by Gareth McMullin
parent 8d6092b73f
commit 9ce05ae67b
3 changed files with 19 additions and 0 deletions
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9
src/target/stm32f4.c
View File

@ -183,6 +183,12 @@ char *stm32f4_get_chip_name(uint32_t idcode)
}
}
static void stm32f7_detach(target *t)
{
target_mem_write32(t, DBGMCU_CR, t->target_storage);
cortexm_detach(t);
}
bool stm32f4_probe(target *t)
{
ADIv5_AP_t *ap = cortexm_ap(t);
@ -204,6 +210,8 @@ bool stm32f4_probe(target *t)
case ID_STM32F74X: /* F74x RM0385 Rev.4 */
case ID_STM32F76X: /* F76x F77x RM0410 */
case ID_STM32F72X: /* F72x F73x RM0431 */
t->detach = stm32f7_detach;
/* fall through */
case ID_STM32F40X:
case ID_STM32F42X: /* 427/437 */
case ID_STM32F46X: /* 469/479 */
@ -283,6 +291,7 @@ static bool stm32f4_attach(target *t)
target_mem_map_free(t);
uint32_t flashsize = target_mem_read32(t, flashsize_base) & 0xffff;
if (is_f7) {
t->target_storage = target_mem_read32(t, DBGMCU_CR);
target_mem_write32(t, DBGMCU_CR, DBG_SLEEP);
target_add_ram(t, 0x00000000, 0x4000); /* 16 k ITCM Ram */
target_add_ram(t, 0x20000000, 0x20000); /* 128 k DTCM Ram */

9
src/target/stm32h7.c
View File

@ -178,6 +178,8 @@ static bool stm32h7_attach(target *t)
return false;
/* RM0433 Rev 4 is not really clear, what bits are needed.
* Set all possible relevant bits for now. */
uint32_t dbgmcu_cr = target_mem_read32(t, DBGMCU_CR);
t->target_storage = dbgmcu_cr;
target_mem_write32(t, DBGMCU_CR, DBGSLEEP_D1 | D1DBGCKEN);
/* If IWDG runs as HARDWARE watchdog (44.3.4) erase
* will be aborted by the Watchdog and erase fails!
@ -188,6 +190,12 @@ static bool stm32h7_attach(target *t)
return true;
}
static void stm32h7_detach(target *t)
{
target_mem_write32(t, DBGMCU_CR, t->target_storage);
cortexm_detach(t);
}
bool stm32h7_probe(target *t)
{
ADIv5_AP_t *ap = cortexm_ap(t);
@ -196,6 +204,7 @@ bool stm32h7_probe(target *t)
t->idcode = idcode;
t->driver = stm32h74_driver_str;
t->attach = stm32h7_attach;
t->detach = stm32h7_detach;
target_add_commands(t, stm32h7_cmd_list, stm32h74_driver_str);
target_add_ram(t, 0x00000000, 0x10000); /* ITCM Ram, 64 k */
target_add_ram(t, 0x20000000, 0x20000); /* DTCM Ram, 128 k */

1
src/target/target_internal.h
View File

@ -108,6 +108,7 @@ struct target_s {
/* target-defined options */
unsigned target_options;
uint32_t idcode;
uint32_t target_storage;
struct target_ram *ram;
struct target_flash *flash;