stm32l4: Build Memory Map during attach.
Reading target registers while target not halted may fail and result in invalid memory map.
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@ -142,46 +142,65 @@ static void stm32l4_add_flash(target *t,
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target_add_flash(t, f);
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}
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static bool stm32l4_attach(target *t);
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bool stm32l4_probe(target *t)
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{
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uint32_t idcode;
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uint32_t size;
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uint32_t options;
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uint32_t bank1_start = 0x08040000;
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idcode = target_mem_read32(t, DBGMCU_IDCODE) & 0xFFF;
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switch(idcode) {
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case 0x461: /* L496/RM0351 */
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case 0x415: /* L471/RM0392, L475/RM0395, L476/RM0351 */
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case 0x462: /* L45x L46x / RM0394 */
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case 0x435: /* L43x L44x / RM0394 */
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t->idcode = idcode;
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t->driver = "STM32L4";
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t->attach = stm32l4_attach;
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target_add_commands(t, stm32l4_cmd_list, "STM32L4");
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return true;
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default:
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return false;
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}
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}
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static bool stm32l4_attach(target *t)
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{
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uint32_t size = (target_mem_read32(t, FLASH_SIZE_REG) & 0xffff);
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uint32_t bank1_start = 0x08080000; /* default split on 1MiB devices*/
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if (!cortexm_attach(t))
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return false;
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target_mem_map_free(t);
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switch(t->idcode) {
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case 0x461: /* L496/RM0351 */
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case 0x415: /* L471/RM0392, L475/RM0395, L476/RM0351 */
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t->driver = stm32l4_driver_str;
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if (idcode == 0x415) {
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if (t->idcode == 0x415) {
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target_add_ram(t, 0x10000000, 0x08000);
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target_add_ram(t, 0x20000000, 0x18000);
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} else {
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target_add_ram(t, 0x10000000, 0x10000);
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target_add_ram(t, 0x20000000, 0x40000);
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}
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size = (target_mem_read32(t, FLASH_SIZE_REG) & 0xffff);
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options = target_mem_read32(t, FLASH_OPTR);
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uint32_t options = target_mem_read32(t, FLASH_OPTR);
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/* Only 256 and 512 kiB devices evaluate OR_DUALBANK*/
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if ((size < 0x400) && (options & OR_DUALBANK))
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bank1_start = 0x08000000 + (size << 9);
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stm32l4_add_flash(t, 0x08000000, size << 10, PAGE_SIZE, bank1_start);
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target_add_commands(t, stm32l4_cmd_list, "STM32L4 Dual bank");
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return true;
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case 0x462: /* L45x L46x / RM0394 */
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case 0x435: /* L43x L44x / RM0394 */
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t->driver = stm32l4_driver_str;
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if (idcode == 0x452) {
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if (t->idcode == 0x452) {
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target_add_ram(t, 0x10000000, 0x08000);
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target_add_ram(t, 0x20000000, 0x20000);
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} else {
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target_add_ram(t, 0x10000000, 0x04000);
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target_add_ram(t, 0x20000000, 0x0c000);
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}
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size = (target_mem_read32(t, FLASH_SIZE_REG) & 0xffff);
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options = target_mem_read32(t, FLASH_OPTR);
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stm32l4_add_flash(t, 0x08000000, size << 10, PAGE_SIZE, bank1_start);
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target_add_commands(t, stm32l4_cmd_list, "STM32L4");
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return true;
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}
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return false;
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