Merge pull request #896 from RadinnAB/for-upstream
Add nRF51 erase UICR command and fix some warnings
This commit is contained in:
commit
a0dbb2a787
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@ -436,27 +436,27 @@ handle_v_packet(char *packet, int plen)
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} else if (!strncmp(packet, "vRun", 4)) {
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/* Parse command line for get_cmdline semihosting call */
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char cmdline[83];
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char *pbuf = cmdline;
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char *pcmdline = cmdline;
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char *tok = packet + 4;
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if (*tok == ';') tok++;
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*cmdline='\0';
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while(*tok != '\0') {
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if(strlen(cmdline)+3 >= sizeof(cmdline)) break;
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if (*tok == ';') {
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*pbuf++=' ';
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*pbuf='\0';
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*pcmdline++=' ';
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*pcmdline='\0';
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tok++;
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continue;
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}
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if (isxdigit(*tok) && isxdigit(*(tok+1))) {
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unhexify(pbuf, tok, 2);
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if ((*pbuf == ' ') || (*pbuf == '\\')) {
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*(pbuf+1)=*pbuf;
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*pbuf++='\\';
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unhexify(pcmdline, tok, 2);
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if ((*pcmdline == ' ') || (*pcmdline == '\\')) {
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*(pcmdline+1)=*pcmdline;
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*pcmdline++='\\';
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}
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pbuf++;
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pcmdline++;
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tok+=2;
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*pbuf='\0';
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*pcmdline='\0';
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continue;
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}
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break;
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@ -21,7 +21,9 @@
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#ifndef __GENERAL_H
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#define __GENERAL_H
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#define _GNU_SOURCE
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#if !defined(_GNU_SOURCE)
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# define _GNU_SOURCE
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#endif
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#if !defined(__USE_MINGW_ANSI_STDIO)
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# define __USE_MINGW_ANSI_STDIO 1
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#endif
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@ -57,18 +59,21 @@ enum BMP_DEBUG {
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* BMP PC-Hosted is the preferred way. Printing DEBUG_WARN
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* and DEBUG_INFO is kept for comptibiluty.
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*/
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# if defined(ENABLE_DEBUG)
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# define DEBUG_WARN printf
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# define DEBUG_INFO printf
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# else
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# define DEBUG_WARN(...)
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# define DEBUG_INFO(...)
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# if !defined(PLATFORM_PRINTF)
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# define PLATFORM_PRINTF printf
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# endif
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# define DEBUG_GDB(...)
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# define DEBUG_TARGET(...)
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# define DEBUG_PROBE(...)
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# define DEBUG_WIRE(...)
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# define DEBUG_GDB_WIRE(...)
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# if defined(ENABLE_DEBUG)
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# define DEBUG_WARN PLATFORM_PRINTF
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# define DEBUG_INFO PLATFORM_PRINTF
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# else
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# define DEBUG_WARN(...) do {} while(0)
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# define DEBUG_INFO(...) do {} while(0)
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# endif
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# define DEBUG_GDB(...) do {} while(0)
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# define DEBUG_TARGET(...) do {} while(0)
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# define DEBUG_PROBE(...) do {} while(0)
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# define DEBUG_WIRE(...) do {} while(0)
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# define DEBUG_GDB_WIRE(...) do {} while(0)
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#else
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# include <stdarg.h>
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extern int cl_debuglevel;
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@ -51,7 +51,7 @@ static int cdcacm_gdb_dtr = 1;
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static void cdcacm_set_modem_state(usbd_device *dev, int iface, bool dsr, bool dcd);
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static const struct usb_device_descriptor dev = {
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static const struct usb_device_descriptor dev_desc = {
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.bLength = USB_DT_DEVICE_SIZE,
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.bDescriptorType = USB_DT_DEVICE,
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.bcdUSB = 0x0200,
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@ -551,7 +551,7 @@ void cdcacm_init(void)
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serial_no_read(serial_no);
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usbdev = usbd_init(&USB_DRIVER, &dev, &config, usb_strings,
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usbdev = usbd_init(&USB_DRIVER, &dev_desc, &config, usb_strings,
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sizeof(usb_strings)/sizeof(char *),
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usbd_control_buffer, sizeof(usbd_control_buffer));
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@ -63,7 +63,7 @@ static struct {
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} prog;
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static uint8_t current_error;
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const struct usb_device_descriptor dev = {
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const struct usb_device_descriptor dev_desc = {
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.bLength = USB_DT_DEVICE_SIZE,
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.bDescriptorType = USB_DT_DEVICE,
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.bcdUSB = 0x0200,
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@ -293,7 +293,7 @@ void dfu_init(const usbd_driver *driver)
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{
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get_dev_unique_id(serial_no);
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usbdev = usbd_init(driver, &dev, &config,
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usbdev = usbd_init(driver, &dev_desc, &config,
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usb_strings, 4,
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usbd_control_buffer, sizeof(usbd_control_buffer));
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@ -334,7 +334,7 @@ static bool cortexm_prepare(ADIv5_AP_t *ap)
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uint32_t dhcsr_ctl = CORTEXM_DHCSR_DBGKEY | CORTEXM_DHCSR_C_DEBUGEN |
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CORTEXM_DHCSR_C_HALT;
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uint32_t dhcsr_valid = CORTEXM_DHCSR_S_HALT | CORTEXM_DHCSR_C_DEBUGEN;
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#ifdef PLATFORM_HAS_DEBUG
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#if defined(ENABLE_DEBUG) && defined(PLATFORM_HAS_DEBUG)
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uint32_t start_time = platform_time_ms();
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#endif
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uint32_t dhcsr;
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@ -125,12 +125,12 @@ int adiv5_swdp_scan(uint32_t targetid)
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initial_dp->seq_out(0xE79E, 16); /* 0b0111100111100111 */
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dp_line_reset(initial_dp);
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initial_dp->fault = 0;
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volatile struct exception e;
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TRY_CATCH (e, EXCEPTION_ALL) {
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volatile struct exception e2;
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TRY_CATCH (e2, EXCEPTION_ALL) {
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idcode = initial_dp->low_access(initial_dp, ADIV5_LOW_READ,
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ADIV5_DP_IDCODE, 0);
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}
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if (e.type) {
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if (e2.type) {
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DEBUG_WARN("No usable DP found\n");
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return -1;
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}
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@ -526,7 +526,7 @@ bool cortexm_attach(target *t)
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platform_timeout timeout;
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platform_timeout_set(&timeout, 1000);
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while (1) {
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uint32_t dhcsr = target_mem_read32(t, CORTEXM_DHCSR);
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dhcsr = target_mem_read32(t, CORTEXM_DHCSR);
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if (!(dhcsr & CORTEXM_DHCSR_S_RESET_ST))
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break;
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if (platform_timeout_is_expired(&timeout)) {
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@ -572,8 +572,8 @@ static void cortexm_regs_read(target *t, void *data)
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for(i = 0; i < sizeof(regnum_cortex_m) / 4; i++)
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*regs++ = base_regs[regnum_cortex_m[i]];
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if (t->target_options & TOPT_FLAVOUR_V7MF)
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for(size_t t = 0; t < sizeof(regnum_cortex_mf) / 4; t++)
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*regs++ = ap->dp->ap_reg_read(ap, regnum_cortex_mf[t]);
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for(i = 0; i < sizeof(regnum_cortex_mf) / 4; i++)
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*regs++ = ap->dp->ap_reg_read(ap, regnum_cortex_mf[i]);
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}
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#else
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if (0) {}
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@ -31,6 +31,7 @@ static int nrf51_flash_write(struct target_flash *f,
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target_addr dest, const void *src, size_t len);
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static bool nrf51_cmd_erase_all(target *t, int argc, const char **argv);
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static bool nrf51_cmd_erase_uicr(target *t, int argc, const char **argv);
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static bool nrf51_cmd_read_hwid(target *t, int argc, const char **argv);
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static bool nrf51_cmd_read_fwid(target *t, int argc, const char **argv);
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static bool nrf51_cmd_read_deviceid(target *t, int argc, const char **argv);
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@ -41,6 +42,7 @@ static bool nrf51_cmd_read(target *t, int argc, const char **argv);
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const struct command_s nrf51_cmd_list[] = {
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{"erase_mass", (cmd_handler)nrf51_cmd_erase_all, "Erase entire flash memory"},
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{"erase_uicr", (cmd_handler)nrf51_cmd_erase_uicr, "Erase UICR registers"},
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{"read", (cmd_handler)nrf51_cmd_read, "Read device parameters"},
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{NULL, NULL, NULL}
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};
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@ -244,6 +246,31 @@ static bool nrf51_cmd_erase_all(target *t, int argc, const char **argv)
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return true;
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}
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static bool nrf51_cmd_erase_uicr(target *t, int argc, const char **argv)
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{
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(void)argc;
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(void)argv;
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tc_printf(t, "erase..\n");
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/* Enable erase */
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target_mem_write32(t, NRF51_NVMC_CONFIG, NRF51_NVMC_CONFIG_EEN);
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/* Poll for NVMC_READY */
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while (target_mem_read32(t, NRF51_NVMC_READY) == 0)
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if(target_check_error(t))
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return false;
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/* Erase UICR */
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target_mem_write32(t, NRF51_NVMC_ERASEUICR, 1);
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/* Poll for NVMC_READY */
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while (target_mem_read32(t, NRF51_NVMC_READY) == 0)
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if(target_check_error(t))
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return false;
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return true;
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}
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static bool nrf51_cmd_read_hwid(target *t, int argc, const char **argv)
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{
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(void)argc;
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@ -248,7 +248,7 @@ bool sam3x_probe(target *t)
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case CHIPID_CIDR_ARCH_SAM4SDC | CHIPID_CIDR_EPROC_CM4:
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t->driver = "Atmel SAM4S";
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target_add_ram(t, 0x20000000, 0x400000);
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size_t size = sam_flash_size(cidr);
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size = sam_flash_size(cidr);
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if (size <= 0x80000) {
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/* Smaller devices have a single bank */
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sam4_add_flash(t, SAM4S_EEFC_BASE(0), 0x400000, size);
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@ -386,7 +386,7 @@ static bool stm32f1_cmd_erase_mass(target *t, int argc, const char **argv)
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if(target_check_error(t))
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return false;
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/* Check for error */
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uint16_t sr = target_mem_read32(t, FLASH_SR + FLASH_BANK2_OFFSET);
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sr = target_mem_read32(t, FLASH_SR + FLASH_BANK2_OFFSET);
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if ((sr & SR_ERROR_MASK) || !(sr & SR_EOP))
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return false;
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}
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@ -384,9 +384,9 @@ static int stm32f4_flash_erase(struct target_flash *f, target_addr addr,
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stm32f4_flash_unlock(t);
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enum align psize = ALIGN_WORD;
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for (struct target_flash *f = t->flash; f; f = f->next) {
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if (f->write == stm32f4_flash_write) {
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psize = ((struct stm32f4_flash *)f)->psize;
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for (struct target_flash *currf = t->flash; currf; currf = currf->next) {
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if (currf->write == stm32f4_flash_write) {
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psize = ((struct stm32f4_flash *)currf)->psize;
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}
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}
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while(len) {
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@ -276,7 +276,7 @@ int target_flash_done(target *t)
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if (tmp)
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return tmp;
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if (f->done) {
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int tmp = f->done(f);
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tmp = f->done(f);
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if (tmp)
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return tmp;
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}
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