parent
eca3a8dd8f
commit
a0e42e229b
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@ -216,7 +216,7 @@ static const struct {
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extern bool cortexa_probe(ADIv5_AP_t *apb, uint32_t debug_base);
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void adiv5_dp_ref(ADIv5_DP_t *dp)
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static void adiv5_dp_ref(ADIv5_DP_t *dp)
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{
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dp->refcnt++;
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}
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@ -226,7 +226,7 @@ void adiv5_ap_ref(ADIv5_AP_t *ap)
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ap->refcnt++;
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}
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void adiv5_dp_unref(ADIv5_DP_t *dp)
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static void adiv5_dp_unref(ADIv5_DP_t *dp)
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{
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if (--(dp->refcnt) == 0)
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free(dp);
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@ -186,9 +186,7 @@ void adiv5_dp_init(ADIv5_DP_t *dp);
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void adiv5_dp_write(ADIv5_DP_t *dp, uint16_t addr, uint32_t value);
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ADIv5_AP_t *adiv5_new_ap(ADIv5_DP_t *dp, uint8_t apsel);
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void adiv5_dp_ref(ADIv5_DP_t *dp);
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void adiv5_ap_ref(ADIv5_AP_t *ap);
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void adiv5_dp_unref(ADIv5_DP_t *dp);
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void adiv5_ap_unref(ADIv5_AP_t *ap);
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void adiv5_ap_write(ADIv5_AP_t *ap, uint16_t addr, uint32_t value);
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@ -53,11 +53,12 @@ const struct command_s cortexm_cmd_list[] = {
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static void cortexm_regs_read(target *t, void *data);
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static void cortexm_regs_write(target *t, const void *data);
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static uint32_t cortexm_pc_read(target *t);
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ssize_t cortexm_reg_read(target *t, int reg, void *data, size_t max);
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ssize_t cortexm_reg_write(target *t, int reg, const void *data, size_t max);
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static ssize_t cortexm_reg_read(target *t, int reg, void *data, size_t max);
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static ssize_t cortexm_reg_write(target *t, int reg, const void *data, size_t max);
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static void cortexm_reset(target *t);
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static enum target_halt_reason cortexm_halt_poll(target *t, target_addr *watch);
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static void cortexm_halt_resume(target *t, bool step);
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static void cortexm_halt_request(target *t);
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static int cortexm_fault_unwind(target *t);
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@ -549,7 +550,7 @@ int cortexm_mem_write_sized(
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return target_check_error(t);
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}
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int dcrsr_regnum(target *t, unsigned reg)
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static int dcrsr_regnum(target *t, unsigned reg)
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{
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if (reg < sizeof(regnum_cortex_m) / 4) {
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return regnum_cortex_m[reg];
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@ -561,7 +562,7 @@ int dcrsr_regnum(target *t, unsigned reg)
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return -1;
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}
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}
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ssize_t cortexm_reg_read(target *t, int reg, void *data, size_t max)
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static ssize_t cortexm_reg_read(target *t, int reg, void *data, size_t max)
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{
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if (max < 4)
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return -1;
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@ -571,7 +572,7 @@ ssize_t cortexm_reg_read(target *t, int reg, void *data, size_t max)
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return 4;
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}
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ssize_t cortexm_reg_write(target *t, int reg, const void *data, size_t max)
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static ssize_t cortexm_reg_write(target *t, int reg, const void *data, size_t max)
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{
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if (max < 4)
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return -1;
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@ -713,7 +714,7 @@ static enum target_halt_reason cortexm_halt_poll(target *t, target_addr *watch)
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return TARGET_HALT_BREAKPOINT;
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}
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void cortexm_halt_resume(target *t, bool step)
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static void cortexm_halt_resume(target *t, bool step)
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{
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struct cortexm_priv *priv = t->priv;
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uint32_t dhcsr = CORTEXM_DHCSR_DBGKEY | CORTEXM_DHCSR_C_DEBUGEN;
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@ -175,7 +175,6 @@ ADIv5_AP_t *cortexm_ap(target *t);
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bool cortexm_attach(target *t);
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void cortexm_detach(target *t);
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void cortexm_halt_resume(target *t, bool step);
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int cortexm_run_stub(target *t, uint32_t loadaddr,
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uint32_t r0, uint32_t r1, uint32_t r2, uint32_t r3);
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int cortexm_mem_write_sized(
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@ -104,7 +104,7 @@ bool lmi_probe(target *t)
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return false;
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}
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int lmi_flash_erase(struct target_flash *f, target_addr addr, size_t len)
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static int lmi_flash_erase(struct target_flash *f, target_addr addr, size_t len)
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{
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target *t = f->t;
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@ -128,7 +128,7 @@ int lmi_flash_erase(struct target_flash *f, target_addr addr, size_t len)
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return 0;
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}
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int lmi_flash_write(struct target_flash *f,
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static int lmi_flash_write(struct target_flash *f,
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target_addr dest, const void *src, size_t len)
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{
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target *t = f->t;
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@ -329,7 +329,7 @@ samd20_revB_detach(target *t)
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static void
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samd20_revB_halt_resume(target *t, bool step)
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{
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cortexm_halt_resume(t, step);
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target_halt_resume(t, step);
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/* ---- Additional ---- */
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/* Exit extended reset */
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@ -518,7 +518,7 @@ static bool stm32f4_cmd_erase_mass(target *t, int argc, const char **argv)
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* * Documentation for F413 with OPTCR default = 0ffffffed seems wrong!
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*/
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bool optcr_mask(target *t, uint32_t *val)
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static bool optcr_mask(target *t, uint32_t *val)
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{
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switch (t->idcode) {
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case ID_STM32F20X:
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