STM32L55: Detect, memory map, read and flash write. Options handling missing.
Only non-secure states considered!
This commit is contained in:
Uwe Bonnes
UweBonnes
parent
db17f2caa8
commit
a6a8606edb
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@ -400,10 +400,6 @@ bool cortexm_probe(ADIv5_AP_t *ap)
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PROBE(stm32l0_probe);
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PROBE(stm32l4_probe);
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PROBE(stm32g0_probe);
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if (ap->ap_partno == 0x472) {
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t->driver = "STM32L552(no flash)";
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target_halt_resume(t, 0);
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}
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break;
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case AP_DESIGNER_CYPRESS:
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DEBUG_WARN("Unhandled Cypress device\n");
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@ -1,7 +1,7 @@
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/*
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* This file is part of the Black Magic Debug project.
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*
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* Copyright (C) 2015, 2017 - 2020 Uwe Bonnes
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* Copyright (C) 2015, 2017 - 2021 Uwe Bonnes
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* <bon@elektron.ikp.physik.tu-darmstadt.de>
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*
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* This program is free software: you can redistribute it and/or modify
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@ -51,21 +51,36 @@ const struct command_s stm32l4_cmd_list[] = {
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{NULL, NULL, NULL}
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};
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static int stm32l4_flash_erase(struct target_flash *f, target_addr addr, size_t len);
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static int stm32l4_flash_write(struct target_flash *f,
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target_addr dest, const void *src, size_t len);
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/* Flash Program ad Erase Controller Register Map */
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#define FPEC_BASE 0x40022000
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#define FLASH_ACR (FPEC_BASE+0x00)
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#define FLASH_KEYR (FPEC_BASE+0x08)
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#define FLASH_OPTKEYR (FPEC_BASE+0x0c)
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#define FLASH_SR (FPEC_BASE+0x10)
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#define FLASH_CR (FPEC_BASE+0x14)
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#define FLASH_OPTR (FPEC_BASE+0x20)
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#define L4_FLASH_ACR (FPEC_BASE+0x00)
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#define L4_FLASH_KEYR (FPEC_BASE+0x08)
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#define L4_FLASH_OPTKEYR (FPEC_BASE+0x0c)
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#define L4_FLASH_SR (FPEC_BASE+0x10)
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#define L4_FLASH_CR (FPEC_BASE+0x14)
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#define L4_FLASH_OPTR (FPEC_BASE+0x20)
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//#define FLASH_OPTCR (FPEC_BASE+0x14)
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#define L5_FPEC_BASE 0x40022000
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#define L5_FLASH_ACR (L5_FPEC_BASE+0x00)
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#define L5_FLASH_KEYR (L5_FPEC_BASE+0x08)
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#define L5_FLASH_OPTKEYR (L5_FPEC_BASE+0x10)
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#define L5_FLASH_SR (L5_FPEC_BASE+0x20)
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#define L5_FLASH_CR (L5_FPEC_BASE+0x28)
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#define L5_FLASH_OPTR (L5_FPEC_BASE+0x40)
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#define L5_FLASH_OPTR_TZEN (1 << 31)
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#define FLASH_KEYR(x) ((x == ID_STM32L55) ? L5_FLASH_KEYR : L4_FLASH_KEYR)
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#define FLASH_SR(x) ((x == ID_STM32L55) ? L5_FLASH_SR : L4_FLASH_SR)
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#define FLASH_CR(x) ((x == ID_STM32L55) ? L5_FLASH_CR : L4_FLASH_CR)
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#define FLASH_OPTR(x) ((x == ID_STM32L55) ? L5_FLASH_OPTR : L4_FLASH_OPTR)
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#define FLASH_OPTKEYR(x) ((x == ID_STM32L55) ? L5_FLASH_OPTKEYR : L4_FLASH_OPTKEYR)
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#define FLASH_CR_PG (1 << 0)
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#define FLASH_CR_PER (1 << 1)
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#define FLASH_CR_MER1 (1 << 2)
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@ -107,7 +122,7 @@ static int stm32l4_flash_write(struct target_flash *f,
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#define OR_DUALBANK (1 << 21)
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/* Used in STM32L47R*/
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#define OR_DB1M (1 << 21)
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/* Used in STM32L47R and STM32G47 */
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/* Used in STM32L47R, STM32G47 and STM32L55*/
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#define OR_DBANK (1 << 22)
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#define DBGMCU_CR(dbgmcureg) (dbgmcureg + 0x04)
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@ -117,8 +132,11 @@ static int stm32l4_flash_write(struct target_flash *f,
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enum {
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STM32L4_DBGMCU_IDCODE_PHYS = 0xe0042000,
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STM32L5_DBGMCU_IDCODE_PHYS = 0xe0044000,
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};
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#define FLASH_SIZE_REG 0x1FFF75E0
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#define L4_FLASH_SIZE_REG 0x1FFF75E0
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#define L5_FLASH_SIZE_REG 0x0bfa05e0
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#define FLASH_SIZE_REG(x) ((x == ID_STM32L55) ? L5_FLASH_SIZE_REG : L4_FLASH_SIZE_REG)
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struct stm32l4_flash {
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struct target_flash f;
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@ -138,6 +156,7 @@ enum ID_STM32L4 {
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ID_STM32L4R = 0x470u, /* RM0432, Rev.5 */
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ID_STM32G43 = 0x468u, /* RM0440, Rev.1 */
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ID_STM32G47 = 0x469u, /* RM0440, Rev.1 */
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ID_STM32L55 = 0x472u, /* RM0438, Rev.4 */
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};
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enum FAM_STM32L4 {
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@ -145,6 +164,7 @@ enum FAM_STM32L4 {
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FAM_STM32L4Rx = 2,
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FAM_STM32WBxx = 4,
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FAM_STM32G4xx = 5,
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FAM_STM32L55x,
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};
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#define DUAL_BANK 0x80u
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@ -160,7 +180,7 @@ struct stm32l4_info {
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uint8_t flags; /* Only DUAL_BANK is evaluated for now.*/
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};
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struct stm32l4_info const L4info[] = {
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static struct stm32l4_info const L4info[] = {
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{
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.idcode = ID_STM32L41,
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.family = FAM_STM32L4xx,
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@ -221,10 +241,18 @@ struct stm32l4_info const L4info[] = {
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.idcode = ID_STM32G47,
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.family = FAM_STM32G4xx,
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.designator = "STM32G47",
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.sram1 = 96, /* SRAM1 and SRAM2 are mapped contigiously */
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.sram1 = 96, /* SRAM1 and SRAM2 are mapped continuous */
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.sram2 = 32, /* CCM SRAM is mapped as per SRAM2 on G4 */
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.flags = 2,
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},
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{
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.idcode = ID_STM32L55,
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.family = FAM_STM32L55x,
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.designator = "STM32L55",
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.sram1 = 192, /* SRAM1 and SRAM2 are mapped continuous */
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.sram2 = 64,
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.flags = 2,
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},
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{
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/* Terminator */
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.idcode = 0,
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@ -263,6 +291,17 @@ static void stm32l4_add_flash(target *t,
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sf->bank1_start = bank1_start;
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target_add_flash(t, f);
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}
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#define L5_RCC_APB1ENR1 0x50021058
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#define L5_RCC_APB1ENR1_PWREN (1 << 28)
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#define L5_PWR_CR1 0x50007000
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#define L5_PWR_CR1_VOS (3 << 9)
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/* For flash programming, L5 needs to be in VOS 0 or 1 while reset set 2 (or even 3?) */
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static void stm32l5_flash_enable(target *t)
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{
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target_mem_write32(t, L5_RCC_APB1ENR1, L5_RCC_APB1ENR1_PWREN);
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uint32_t pwr_cr1 = target_mem_read32(t, L5_PWR_CR1) & ~L5_PWR_CR1_VOS;
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target_mem_write32(t, L5_PWR_CR1, pwr_cr1);
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}
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static bool stm32l4_attach(target *t)
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{
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@ -273,9 +312,16 @@ static bool stm32l4_attach(target *t)
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struct stm32l4_info const *chip = stm32l4_get_chip_info(t->idcode);
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uint32_t idcodereg = STM32L4_DBGMCU_IDCODE_PHYS;
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uint32_t idcodereg;
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switch(chip->family) {
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case FAM_STM32L55x:
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idcodereg = STM32L5_DBGMCU_IDCODE_PHYS;
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stm32l5_flash_enable(t);
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break;
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default:
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idcodereg = STM32L4_DBGMCU_IDCODE_PHYS;
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break;
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}
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/* Save DBGMCU_CR to restore it when detaching*/
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struct stm32l4_priv_s *priv_storage = calloc(1, sizeof(*priv_storage));
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priv_storage->dbgmcu_cr = target_mem_read32(t, DBGMCU_CR(idcodereg));
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@ -284,20 +330,22 @@ static bool stm32l4_attach(target *t)
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/* Enable debugging during all low power modes*/
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target_mem_write32(t, DBGMCU_CR(idcodereg), DBGMCU_CR_DBG_SLEEP | DBGMCU_CR_DBG_STANDBY | DBGMCU_CR_DBG_STOP);
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/* Free previously loaded memory map */
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target_mem_map_free(t);
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/* Add RAM to memory map */
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target_add_ram(t, 0x10000000, chip->sram2 << 10);
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/* Add Code RAM to memory map */
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if (chip->family == FAM_STM32L55x)
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target_add_ram(t, 0x0A000000, (chip->sram1 + chip->sram2) << 10);
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else
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target_add_ram(t, 0x10000000, chip->sram2 << 10);
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/* All L4 beside L47 alias SRAM2 after SRAM1.*/
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uint32_t ramsize = (t->idcode == ID_STM32L47)?
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chip->sram1 : (chip->sram1 + chip->sram2 + chip->sram3);
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target_add_ram(t, 0x20000000, ramsize << 10);
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uint32_t size = target_mem_read16(t, FLASH_SIZE_REG(t->idcode));
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/* Add the flash to memory map. */
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uint32_t size = target_mem_read16(t, FLASH_SIZE_REG);
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uint32_t options = target_mem_read32(t, FLASH_OPTR);
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uint32_t options = target_mem_read32(t, FLASH_OPTR(t->idcode));
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if (chip->family == FAM_STM32L4Rx) {
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/* rm0432 Rev. 2 does not mention 1 MB devices or explain DB1M.*/
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@ -306,6 +354,13 @@ static bool stm32l4_attach(target *t)
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stm32l4_add_flash(t, 0x08100000, 0x00100000, 0x1000, 0x08100000);
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} else
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stm32l4_add_flash(t, 0x08000000, 0x00200000, 0x2000, -1);
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} else if (chip->family == FAM_STM32L55x) {
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/* FIXME: Test behaviour on 256 k devices */
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if (options & OR_DBANK) {
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stm32l4_add_flash(t, 0x08000000, 0x00040000, 0x0800, 0x08040000);
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stm32l4_add_flash(t, 0x08040000, 0x00040000, 0x0800, 0x08040000);
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} else
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stm32l4_add_flash(t, 0x08000000, 0x00080000, 0x0800, -1);
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} else if (chip->family == FAM_STM32G4xx) {
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// RM0440 describes G43x as Category 2, G47x/G48x as Category 3 devices
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// Cat 2 is always 128k with 2k pages, single bank
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@ -337,7 +392,7 @@ static bool stm32l4_attach(target *t)
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stm32l4_add_flash(t, 0x08000000, size << 10, 0x800, -1);
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/* Clear all errors in the status register. */
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target_mem_write32(t, FLASH_SR, target_mem_read32(t, FLASH_SR));
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target_mem_write32(t, FLASH_SR(t->idcode), target_mem_read32(t, FLASH_SR(t->idcode)));
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return true;
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}
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@ -354,7 +409,18 @@ static void stm32l4_detach(target *t)
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bool stm32l4_probe(target *t)
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{
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struct stm32l4_info const *chip = stm32l4_get_chip_info(t->idcode);
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uint32_t idcode_reg = STM32L4_DBGMCU_IDCODE_PHYS;
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ADIv5_AP_t *ap = cortexm_ap(t);
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if (ap->dp->idcode == 0x0Be12477) {
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idcode_reg = STM32L5_DBGMCU_IDCODE_PHYS;
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if ((target_mem_read32(t, L5_FLASH_OPTR)) & L5_FLASH_OPTR_TZEN) {
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DEBUG_WARN("STM32L5 Trust Zone enabled\n");
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}
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}
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uint32_t idcode = target_mem_read32(t, idcode_reg) & 0xfff;
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DEBUG_INFO("Read %" PRIx32 ": %" PRIx32 "\n", idcode_reg, idcode);
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struct stm32l4_info const *chip = stm32l4_get_chip_info(idcode);
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if( !chip->idcode ) /* Not found */
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return false;
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@ -368,10 +434,10 @@ bool stm32l4_probe(target *t)
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static void stm32l4_flash_unlock(target *t)
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{
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if (target_mem_read32(t, FLASH_CR) & FLASH_CR_LOCK) {
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if ((target_mem_read32(t, FLASH_CR(t->idcode))) & FLASH_CR_LOCK) {
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/* Enable FPEC controller access */
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target_mem_write32(t, FLASH_KEYR, KEY1);
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target_mem_write32(t, FLASH_KEYR, KEY2);
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target_mem_write32(t, FLASH_KEYR(t->idcode), KEY1);
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target_mem_write32(t, FLASH_KEYR(t->idcode), KEY2);
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}
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}
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@ -386,11 +452,11 @@ static int stm32l4_flash_erase(struct target_flash *f, target_addr addr, size_t
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stm32l4_flash_unlock(t);
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/* Read FLASH_SR to poll for BSY bit */
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while(target_mem_read32(t, FLASH_SR) & FLASH_SR_BSY)
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while(target_mem_read32(t, FLASH_SR(t->idcode)) & FLASH_SR_BSY)
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if(target_check_error(t))
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return -1;
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/* Fixme: OPTVER always set after reset! Wrong option defaults?*/
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target_mem_write32(t, FLASH_SR, target_mem_read32(t, FLASH_SR));
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target_mem_write32(t, FLASH_SR(t->idcode), target_mem_read32(t, FLASH_SR(t->idcode)));
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page = (addr - 0x08000000) / blocksize;
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while(len) {
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uint32_t cr;
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@ -399,13 +465,13 @@ static int stm32l4_flash_erase(struct target_flash *f, target_addr addr, size_t
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if (addr >= bank1_start)
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cr |= FLASH_CR_BKER;
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/* Flash page erase instruction */
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target_mem_write32(t, FLASH_CR, cr);
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target_mem_write32(t, FLASH_CR(t->idcode), cr);
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/* write address to FMA */
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cr |= FLASH_CR_STRT;
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target_mem_write32(t, FLASH_CR, cr);
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target_mem_write32(t, FLASH_CR(t->idcode), cr);
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/* Read FLASH_SR to poll for BSY bit */
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while(target_mem_read32(t, FLASH_SR) & FLASH_SR_BSY)
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while(target_mem_read32(t, FLASH_SR(t->idcode)) & FLASH_SR_BSY)
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if(target_check_error(t))
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return -1;
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if (len > blocksize)
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@ -417,7 +483,7 @@ static int stm32l4_flash_erase(struct target_flash *f, target_addr addr, size_t
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}
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/* Check for error */
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sr = target_mem_read32(t, FLASH_SR);
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sr = target_mem_read32(t, FLASH_SR(t->idcode));
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if(sr & FLASH_SR_ERROR_MASK)
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return -1;
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@ -428,12 +494,12 @@ static int stm32l4_flash_write(struct target_flash *f,
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target_addr dest, const void *src, size_t len)
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{
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target *t = f->t;
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target_mem_write32(t, FLASH_CR, FLASH_CR_PG);
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target_mem_write32(t, FLASH_CR(t->idcode), FLASH_CR_PG);
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target_mem_write(t, dest, src, len);
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/* Wait for completion or an error */
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uint32_t sr;
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do {
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sr = target_mem_read32(t, FLASH_SR);
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sr = target_mem_read32(t, FLASH_SR(t->idcode));
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if (target_check_error(t)) {
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DEBUG_WARN("stm32l4 flash write: comm error\n");
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return -1;
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@ -452,18 +518,18 @@ static bool stm32l4_cmd_erase(target *t, uint32_t action)
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stm32l4_flash_unlock(t);
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/* Erase time is 25 ms. No need for a spinner.*/
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/* Flash erase action start instruction */
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target_mem_write32(t, FLASH_CR, action);
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target_mem_write32(t, FLASH_CR, action | FLASH_CR_STRT);
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target_mem_write32(t, FLASH_CR(t->idcode), action);
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target_mem_write32(t, FLASH_CR(t->idcode), action | FLASH_CR_STRT);
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/* Read FLASH_SR to poll for BSY bit */
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while (target_mem_read32(t, FLASH_SR) & FLASH_SR_BSY) {
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while (target_mem_read32(t, FLASH_SR(t->idcode)) & FLASH_SR_BSY) {
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if(target_check_error(t)) {
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return false;
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}
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}
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/* Check for error */
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uint16_t sr = target_mem_read32(t, FLASH_SR);
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uint16_t sr = target_mem_read32(t, FLASH_SR(t->idcode));
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if (sr & FLASH_SR_ERROR_MASK)
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return false;
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return true;
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@ -503,22 +569,22 @@ static bool stm32l4_option_write(
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{
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tc_printf(t, "Device will lose connection. Rescan!\n");
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stm32l4_flash_unlock(t);
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target_mem_write32(t, FLASH_OPTKEYR, OPTKEY1);
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target_mem_write32(t, FLASH_OPTKEYR, OPTKEY2);
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while (target_mem_read32(t, FLASH_SR) & FLASH_SR_BSY)
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target_mem_write32(t, FLASH_OPTKEYR(t->idcode), OPTKEY1);
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target_mem_write32(t, FLASH_OPTKEYR(t->idcode), OPTKEY2);
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while (target_mem_read32(t, FLASH_SR(t->idcode)) & FLASH_SR_BSY)
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if(target_check_error(t))
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return true;
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for (int i = 0; i < len; i++)
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target_mem_write32(t, FPEC_BASE + i2offset[i], values[i]);
|
||||
target_mem_write32(t, FLASH_CR, FLASH_CR_OPTSTRT);
|
||||
while (target_mem_read32(t, FLASH_SR) & FLASH_SR_BSY)
|
||||
target_mem_write32(t, FLASH_CR(t->idcode), FLASH_CR_OPTSTRT);
|
||||
while (target_mem_read32(t, FLASH_SR(t->idcode)) & FLASH_SR_BSY)
|
||||
if(target_check_error(t))
|
||||
return true;
|
||||
target_mem_write32(t, FLASH_CR, FLASH_CR_OBL_LAUNCH);
|
||||
while (target_mem_read32(t, FLASH_CR) & FLASH_CR_OBL_LAUNCH)
|
||||
target_mem_write32(t, FLASH_CR(t->idcode), FLASH_CR_OBL_LAUNCH);
|
||||
while (target_mem_read32(t, FLASH_CR(t->idcode)) & FLASH_CR_OBL_LAUNCH)
|
||||
if(target_check_error(t))
|
||||
return true;
|
||||
target_mem_write32(t, FLASH_CR, FLASH_CR_LOCK);
|
||||
target_mem_write32(t, FLASH_CR(t->idcode), FLASH_CR_LOCK);
|
||||
return false;
|
||||
}
|
||||
|
||||
|
|
@ -540,6 +606,10 @@ static bool stm32l4_option_write(
|
|||
|
||||
static bool stm32l4_cmd_option(target *t, int argc, char *argv[])
|
||||
{
|
||||
if (t->idcode == ID_STM32L55) {
|
||||
tc_printf(t, "STM32L5 options not implemented!\n");
|
||||
return false;
|
||||
}
|
||||
static const uint32_t g4_values[11] = {
|
||||
0xFFEFF8AA, 0xFFFFFFFF, 0x00FF0000, 0xFF00FFFF, 0xFF00FFFF, 0xFF00FF00,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0xFF00FFFF, 0xFF00FFFF, 0xFF00FF00
|
||||
|
|
|
|||
Loading…
Reference in New Issue