target/efm32: flash read write return bool
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@ -45,8 +45,8 @@
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#define SRAM_BASE 0x20000000
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#define STUB_BUFFER_BASE ALIGN(SRAM_BASE + sizeof(efm32_flash_write_stub), 4)
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static int efm32_flash_erase(target_flash_s *f, target_addr_t addr, size_t len);
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static int efm32_flash_write(target_flash_s *f, target_addr_t dest, const void *src, size_t len);
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static bool efm32_flash_erase(target_flash_s *f, target_addr_t addr, size_t len);
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static bool efm32_flash_write(target_flash_s *f, target_addr_t dest, const void *src, size_t len);
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static bool efm32_mass_erase(target *t);
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static const uint16_t efm32_flash_write_stub[] = {
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@ -595,7 +595,7 @@ bool efm32_probe(target *t)
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}
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/* Erase flash row by row */
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static int efm32_flash_erase(target_flash_s *f, target_addr_t addr, size_t len)
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static bool efm32_flash_erase(target_flash_s *f, target_addr_t addr, size_t len)
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{
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target *t = f->t;
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@ -622,7 +622,7 @@ static int efm32_flash_erase(target_flash_s *f, target_addr_t addr, size_t len)
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/* Poll MSC Busy */
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while ((target_mem_read32(t, EFM32_MSC_STATUS(msc)) & EFM32_MSC_STATUS_BUSY)) {
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if (target_check_error(t))
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return -1;
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return false;
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}
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addr += f->blocksize;
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@ -632,11 +632,11 @@ static int efm32_flash_erase(target_flash_s *f, target_addr_t addr, size_t len)
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len = 0;
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}
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return 0;
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return true;
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}
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/* Write flash page by page */
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static int efm32_flash_write(target_flash_s *f, target_addr_t dest, const void *src, size_t len)
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static bool efm32_flash_write(target_flash_s *f, target_addr_t dest, const void *src, size_t len)
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{
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(void)len;
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@ -651,7 +651,7 @@ static int efm32_flash_write(target_flash_s *f, target_addr_t dest, const void *
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/* Write Buffer */
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target_mem_write(t, STUB_BUFFER_BASE, src, len);
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/* Run flashloader */
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int ret = cortexm_run_stub(t, SRAM_BASE, dest, STUB_BUFFER_BASE, len, priv_storage->device->msc_addr);
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const bool ret = cortexm_run_stub(t, SRAM_BASE, dest, STUB_BUFFER_BASE, len, priv_storage->device->msc_addr) == 0;
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#ifdef ENABLE_DEBUG
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/* Check the MSC_IF */
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