Further cleanup of adiv5*
This commit is contained in:
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b8462dd1f2
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@ -7,7 +7,7 @@ VPATH += $(HOST)
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BUILDDATE := `date +"%Y%m%d"`
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BUILDDATE := `date +"%Y%m%d"`
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CFLAGS += -Wall -Wextra -Wno-pointer-sign -Wno-char-subscripts\
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CFLAGS += -Wall -Wextra -Wno-pointer-sign -Wno-char-subscripts\
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-O0 -std=gnu99 -g3 -DBUILDDATE=\"$(BUILDDATE)\"\
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-Os -std=gnu99 -g3 -DBUILDDATE=\"$(BUILDDATE)\"\
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-I. -Iinclude -I$(HOST) \
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-I. -Iinclude -I$(HOST) \
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-DVERSION_SUFFIX=\"`../scripts/setlocalversion`\"
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-DVERSION_SUFFIX=\"`../scripts/setlocalversion`\"
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94
src/adiv5.c
94
src/adiv5.c
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@ -50,11 +50,6 @@ target *last_target = NULL;
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static const char adiv5_driver_str[] = "ARM ADIv5 MEM-AP";
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static const char adiv5_driver_str[] = "ARM ADIv5 MEM-AP";
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ADIv5_DP_t *adiv5_dp_list;
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ADIv5_DP_t *adiv5_dp_list;
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/*
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ADIv5_DP_t adiv5_dps[5];
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int adiv5_dp_count;
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*/
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ADIv5_AP_t adiv5_aps[5];
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ADIv5_AP_t adiv5_aps[5];
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int adiv5_ap_count;
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int adiv5_ap_count;
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@ -120,54 +115,55 @@ void adiv5_dp_init(ADIv5_DP_t *dp)
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/* Probe for APs on this DP */
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/* Probe for APs on this DP */
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for(int i = 0; i < 256; i++) {
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for(int i = 0; i < 256; i++) {
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uint32_t idr;
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ADIv5_AP_t *ap = &adiv5_aps[adiv5_ap_count];
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target *t;
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adiv5_dp_write(dp, ADIV5_DP_SELECT, ((uint32_t)i << 24) | 0xF0);
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/* Assume valid and try to read IDR */
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idr = adiv5_dp_read_ap(dp, 0x0C); /* attempt to read IDR */
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ap->dp = dp;
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ap->apsel = i;
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ap->idr = adiv5_ap_read(ap, ADIV5_AP_IDR);
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if(idr) { /* We have a valid AP, adding to list */
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if(!ap->idr) /* IDR Invalid - Should we not continue here? */
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target *t;
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break;
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adiv5_aps[adiv5_ap_count].dp = dp;
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/* We have a valid AP, adding to list */
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adiv5_aps[adiv5_ap_count].apsel = i;
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ap->cfg = adiv5_ap_read(ap, ADIV5_AP_CFG);
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adiv5_aps[adiv5_ap_count].idr = idr;
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ap->base = adiv5_ap_read(ap, ADIV5_AP_BASE);
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adiv5_aps[adiv5_ap_count].cfg = adiv5_dp_read_ap(dp, 0x04);
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/* Should probe further here... */
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adiv5_aps[adiv5_ap_count].base = adiv5_dp_read_ap(dp, 0x08);
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/* Should probe further here... */
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/* Prepend to target list... */
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/* Prepend to target list... */
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t = target_list;
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t = (void*)calloc(1, sizeof(struct target_ap_s));
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target_list = (void*)calloc(1, sizeof(struct target_ap_s));
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t->next = target_list;
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target_list->next = t;
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target_list = t;
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((struct target_ap_s *)target_list)->ap = &adiv5_aps[adiv5_ap_count];
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((struct target_ap_s *)t)->ap = ap;
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target_list->driver = adiv5_driver_str;
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t->driver = adiv5_driver_str;
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target_list->check_error = ap_check_error;
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t->check_error = ap_check_error;
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target_list->mem_read_words = ap_mem_read_words;
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t->mem_read_words = ap_mem_read_words;
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target_list->mem_write_words = ap_mem_write_words;
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t->mem_write_words = ap_mem_write_words;
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target_list->mem_read_bytes = ap_mem_read_bytes;
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t->mem_read_bytes = ap_mem_read_bytes;
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target_list->mem_write_bytes = ap_mem_write_bytes;
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t->mem_write_bytes = ap_mem_write_bytes;
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/* The rest sould only be added after checking ROM table */
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/* The rest sould only be added after checking ROM table */
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cm3_probe((void*)target_list);
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cm3_probe(t);
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adiv5_ap_count++;
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adiv5_ap_count++;
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} else break;
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}
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}
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}
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}
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void adiv5_dp_write_ap(ADIv5_DP_t *dp, uint8_t addr, uint32_t value)
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void adiv5_dp_write_ap(ADIv5_DP_t *dp, uint8_t addr, uint32_t value)
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{
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{
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adiv5_dp_low_access(dp, 1, 0, addr, value);
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adiv5_dp_low_access(dp, ADIV5_LOW_AP, ADIV5_LOW_WRITE, addr, value);
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}
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}
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uint32_t adiv5_dp_read_ap(ADIv5_DP_t *dp, uint8_t addr)
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uint32_t adiv5_dp_read_ap(ADIv5_DP_t *dp, uint8_t addr)
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{
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{
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uint32_t ret;
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uint32_t ret;
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adiv5_dp_low_access(dp, 1, 1, addr, 0);
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adiv5_dp_low_access(dp, ADIV5_LOW_AP, ADIV5_LOW_READ, addr, 0);
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ret = adiv5_dp_low_access(dp, 0, 1, ADIV5_DP_RDBUFF, 0);
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ret = adiv5_dp_low_access(dp, ADIV5_LOW_DP, ADIV5_LOW_READ,
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ADIV5_DP_RDBUFF, 0);
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return ret;
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return ret;
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}
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}
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@ -188,12 +184,16 @@ ap_mem_read_words(struct target_s *target, uint32_t *dest, uint32_t src, int len
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len >>= 2;
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len >>= 2;
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adiv5_ap_write(t->ap, ADIV5_AP_CSW, 0xA2000052);
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adiv5_ap_write(t->ap, ADIV5_AP_CSW, 0xA2000052);
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adiv5_dp_low_access(t->ap->dp, 1, 0, ADIV5_AP_TAR, src);
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adiv5_dp_low_access(t->ap->dp, ADIV5_LOW_AP, ADIV5_LOW_WRITE,
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adiv5_dp_low_access(t->ap->dp, 1, 1, ADIV5_AP_DRW, 0);
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ADIV5_AP_TAR, src);
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adiv5_dp_low_access(t->ap->dp, ADIV5_LOW_AP, ADIV5_LOW_READ,
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ADIV5_AP_DRW, 0);
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while(--len)
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while(--len)
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*dest++ = adiv5_dp_low_access(t->ap->dp, 1, 1, ADIV5_AP_DRW, 0);
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*dest++ = adiv5_dp_low_access(t->ap->dp, ADIV5_LOW_AP,
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ADIV5_LOW_READ, ADIV5_AP_DRW, 0);
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*dest++ = adiv5_dp_low_access(t->ap->dp, 0, 1, ADIV5_DP_RDBUFF, 0);
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*dest++ = adiv5_dp_low_access(t->ap->dp, ADIV5_LOW_DP, ADIV5_LOW_READ,
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ADIV5_DP_RDBUFF, 0);
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return 0;
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return 0;
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}
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}
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@ -205,8 +205,10 @@ ap_mem_read_bytes(struct target_s *target, uint8_t *dest, uint32_t src, int len)
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uint32_t tmp = src;
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uint32_t tmp = src;
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adiv5_ap_write(t->ap, ADIV5_AP_CSW, 0xA2000050);
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adiv5_ap_write(t->ap, ADIV5_AP_CSW, 0xA2000050);
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adiv5_dp_low_access(t->ap->dp, 1, 0, ADIV5_AP_TAR, src);
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adiv5_dp_low_access(t->ap->dp, ADIV5_LOW_AP, ADIV5_LOW_WRITE,
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adiv5_dp_low_access(t->ap->dp, 1, 1, ADIV5_AP_DRW, 0);
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ADIV5_AP_TAR, src);
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adiv5_dp_low_access(t->ap->dp, ADIV5_LOW_AP, ADIV5_LOW_READ,
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ADIV5_AP_DRW, 0);
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while(--len) {
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while(--len) {
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tmp = adiv5_dp_low_access(t->ap->dp, 1, 1, ADIV5_AP_DRW, 0);
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tmp = adiv5_dp_low_access(t->ap->dp, 1, 1, ADIV5_AP_DRW, 0);
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*dest++ = (tmp >> ((src++ & 0x3) << 3) & 0xFF);
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*dest++ = (tmp >> ((src++ & 0x3) << 3) & 0xFF);
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@ -226,9 +228,11 @@ ap_mem_write_words(struct target_s *target, uint32_t dest, const uint32_t *src,
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len >>= 2;
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len >>= 2;
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adiv5_ap_write(t->ap, ADIV5_AP_CSW, 0xA2000052);
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adiv5_ap_write(t->ap, ADIV5_AP_CSW, 0xA2000052);
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adiv5_dp_low_access(t->ap->dp, 1, 0, ADIV5_AP_TAR, dest);
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adiv5_dp_low_access(t->ap->dp, ADIV5_LOW_AP, ADIV5_LOW_WRITE,
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ADIV5_AP_TAR, dest);
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while(len--)
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while(len--)
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adiv5_dp_low_access(t->ap->dp, 1, 0, ADIV5_AP_DRW, *src++);
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adiv5_dp_low_access(t->ap->dp, ADIV5_LOW_AP, ADIV5_LOW_WRITE,
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ADIV5_AP_DRW, *src++);
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return 0;
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return 0;
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}
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}
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@ -240,10 +244,12 @@ ap_mem_write_bytes(struct target_s *target, uint32_t dest, const uint8_t *src, i
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uint32_t tmp;
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uint32_t tmp;
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adiv5_ap_write(t->ap, ADIV5_AP_CSW, 0xA2000050);
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adiv5_ap_write(t->ap, ADIV5_AP_CSW, 0xA2000050);
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adiv5_dp_low_access(t->ap->dp, 1, 0, ADIV5_AP_TAR, dest);
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adiv5_dp_low_access(t->ap->dp, ADIV5_LOW_AP, ADIV5_LOW_WRITE,
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ADIV5_AP_TAR, dest);
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while(len--) {
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while(len--) {
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tmp = (uint32_t)*src++ << ((dest++ & 3) << 3);
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tmp = (uint32_t)*src++ << ((dest++ & 3) << 3);
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adiv5_dp_low_access(t->ap->dp, 1, 0, ADIV5_AP_DRW, tmp);
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adiv5_dp_low_access(t->ap->dp, ADIV5_LOW_AP, ADIV5_LOW_WRITE,
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ADIV5_AP_DRW, tmp);
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}
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}
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return 0;
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return 0;
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}
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}
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@ -56,9 +56,7 @@ void adiv5_jtag_dp_handler(jtag_dev_t *dev)
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dp->dp_write = adiv5_jtagdp_write;
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dp->dp_write = adiv5_jtagdp_write;
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dp->dp_read = adiv5_jtagdp_read;
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dp->dp_read = adiv5_jtagdp_read;
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dp->error = adiv5_jtagdp_error;
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dp->error = adiv5_jtagdp_error;
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dp->low_access = adiv5_jtagdp_low_access;
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dp->low_access = adiv5_jtagdp_low_access;
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adiv5_dp_init(dp);
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adiv5_dp_init(dp);
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@ -66,19 +64,22 @@ void adiv5_jtag_dp_handler(jtag_dev_t *dev)
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static void adiv5_jtagdp_write(ADIv5_DP_t *dp, uint8_t addr, uint32_t value)
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static void adiv5_jtagdp_write(ADIv5_DP_t *dp, uint8_t addr, uint32_t value)
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{
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{
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adiv5_jtagdp_low_access(dp, 0, 0, addr, value);
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adiv5_jtagdp_low_access(dp, ADIV5_LOW_DP, ADIV5_LOW_WRITE, addr, value);
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}
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}
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static uint32_t adiv5_jtagdp_read(ADIv5_DP_t *dp, uint8_t addr)
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static uint32_t adiv5_jtagdp_read(ADIv5_DP_t *dp, uint8_t addr)
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{
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{
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adiv5_jtagdp_low_access(dp, 0, 1, addr, 0);
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adiv5_jtagdp_low_access(dp, ADIV5_LOW_DP, ADIV5_LOW_READ, addr, 0);
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return adiv5_jtagdp_low_access(dp, 0, 1, ADIV5_DP_RDBUFF, 0);
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return adiv5_jtagdp_low_access(dp, ADIV5_LOW_DP, ADIV5_LOW_READ,
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ADIV5_DP_RDBUFF, 0);
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}
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}
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static uint32_t adiv5_jtagdp_error(ADIv5_DP_t *dp)
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static uint32_t adiv5_jtagdp_error(ADIv5_DP_t *dp)
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{
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{
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adiv5_jtagdp_low_access(dp, 0, 1, ADIV5_DP_CTRLSTAT, 0);
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adiv5_jtagdp_low_access(dp, ADIV5_LOW_DP, ADIV5_LOW_READ,
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return adiv5_jtagdp_low_access(dp, 0, 0, ADIV5_DP_CTRLSTAT, 0xF0000032) & 0x32;
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ADIV5_DP_CTRLSTAT, 0);
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return adiv5_jtagdp_low_access(dp, ADIV5_LOW_DP, ADIV5_LOW_WRITE,
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ADIV5_DP_CTRLSTAT, 0xF0000032) & 0x32;
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}
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}
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static uint32_t adiv5_jtagdp_low_access(ADIv5_DP_t *dp, uint8_t APnDP, uint8_t RnW,
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static uint32_t adiv5_jtagdp_low_access(ADIv5_DP_t *dp, uint8_t APnDP, uint8_t RnW,
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@ -84,12 +84,12 @@ int adiv5_swdp_scan(void)
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static void adiv5_swdp_write(ADIv5_DP_t *dp, uint8_t addr, uint32_t value)
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static void adiv5_swdp_write(ADIv5_DP_t *dp, uint8_t addr, uint32_t value)
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{
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{
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adiv5_swdp_low_access(dp, 0, 0, addr, value);
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adiv5_swdp_low_access(dp, ADIV5_LOW_DP, ADIV5_LOW_WRITE, addr, value);
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}
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}
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static uint32_t adiv5_swdp_read(ADIv5_DP_t *dp, uint8_t addr)
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static uint32_t adiv5_swdp_read(ADIv5_DP_t *dp, uint8_t addr)
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{
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{
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return adiv5_swdp_low_access(dp, 0, 1, addr, 0);
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return adiv5_swdp_low_access(dp, ADIV5_LOW_DP, ADIV5_LOW_READ, addr, 0);
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}
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}
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static uint32_t adiv5_swdp_error(ADIv5_DP_t *dp)
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static uint32_t adiv5_swdp_error(ADIv5_DP_t *dp)
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@ -76,19 +76,29 @@
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/* AP Control and Status Word (CSW) */
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/* AP Control and Status Word (CSW) */
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#define ADIV5_AP_CSW_DBGSWENABLE (1u << 31)
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#define ADIV5_AP_CSW_DBGSWENABLE (1u << 31)
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/* Bits 30:24 - Prot (Implementation defined) */
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/* Bits 30:24 - Prot, Implementation defined, for Cortex-M3: */
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#define ADIV5_AP_CSW_MASTERTYPE_DEBUG (1u << 29)
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#define ADIV5_AP_CSW_HPROT1 (1u << 25)
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#define ADIV5_AP_CSW_SPIDEN (1u << 23)
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#define ADIV5_AP_CSW_SPIDEN (1u << 23)
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/* Bits 22:12 - Reserved */
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/* Bits 22:12 - Reserved */
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/* Bits 11:8 - Mode, must be zero */
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/* Bits 11:8 - Mode, must be zero */
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#define ADIV5_AP_CSW_TRINPROG (1u << 7)
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#define ADIV5_AP_CSW_TRINPROG (1u << 7)
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#define ADIV5_AP_CSW_DEVICEEN (1u << 6)
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#define ADIV5_AP_CSW_DEVICEEN (1u << 6)
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#define ADIV5_AP_CSW_ADDRINC_NONE (0u << 4)
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#define ADIV5_AP_CSW_ADDRINC_SINGLE (1u << 4)
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#define ADIV5_AP_CSW_ADDRINC_SINGLE (1u << 4)
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#define ADIV5_AP_CSW_ADDRINC_PACKED (2u << 4)
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#define ADIV5_AP_CSW_ADDRINC_MASK (3u << 4)
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/* Bit 3 - Reserved */
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/* Bit 3 - Reserved */
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#define ADIV5_AP_CSW_SIZE_BYTE (0u << 0)
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#define ADIV5_AP_CSW_SIZE_BYTE (0u << 0)
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#define ADIV5_AP_CSW_SIZE_HALFWORD (1u << 0)
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#define ADIV5_AP_CSW_SIZE_HALFWORD (1u << 0)
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#define ADIV5_AP_CSW_SIZE_WORD (2u << 0)
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#define ADIV5_AP_CSW_SIZE_WORD (2u << 0)
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#define ADIV5_AP_CSW_SIZE_MASK (7u << 0)
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#define ADIV5_AP_CSW_SIZE_MASK (7u << 0)
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/* Constants to make RnW and APnDP parameters more clear in code */
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#define ADIV5_LOW_WRITE 0
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#define ADIV5_LOW_READ 1
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#define ADIV5_LOW_DP 0
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#define ADIV5_LOW_AP 1
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/* Try to keep this somewhat absract for later adding SW-DP */
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/* Try to keep this somewhat absract for later adding SW-DP */
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typedef struct ADIv5_DP_s {
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typedef struct ADIv5_DP_s {
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