adiv5: Fix the MINDP case introduced with dd28fa5743
#925
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@ -324,14 +324,23 @@ static uint32_t cortexm_initial_halt(ADIv5_AP_t *ap)
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uint32_t dhcsr_valid = CORTEXM_DHCSR_S_HALT | CORTEXM_DHCSR_C_DEBUGEN;
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uint32_t dhcsr;
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bool reset_seen = false;
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adiv5_ap_write(ap, ADIV5_AP_CSW, ap->csw | ADIV5_AP_CSW_SIZE_WORD);
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adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, ADIV5_AP_TAR, CORTEXM_DHCSR);
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if (!(ap->dp->idcode & ADIV5_MINDP)) {
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adiv5_ap_write(ap, ADIV5_AP_CSW, ap->csw | ADIV5_AP_CSW_SIZE_WORD);
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adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, ADIV5_AP_TAR,
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CORTEXM_DHCSR);
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}
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while (!platform_timeout_is_expired(&to)) {
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if (!(ap->dp->idcode & ADIV5_MINDP))
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if (!(ap->dp->idcode & ADIV5_MINDP)) {
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adiv5_dp_write(ap->dp, ADIV5_DP_CTRLSTAT,
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ctrlstat | (0xfff * ADIV5_DP_CTRLSTAT_TRNCNT));
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adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, ADIV5_AP_DRW, dhcsr_ctl);
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dhcsr = adiv5_dp_low_access(ap->dp, ADIV5_LOW_READ, ADIV5_AP_DRW, 0);
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adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, ADIV5_AP_DRW,
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dhcsr_ctl);
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dhcsr = adiv5_dp_low_access(
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ap->dp, ADIV5_LOW_READ, ADIV5_AP_DRW, 0);
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} else {
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adiv5_mem_write(ap, CORTEXM_DHCSR, &dhcsr_ctl, sizeof(dhcsr_ctl));
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dhcsr = adiv5_mem_read32(ap, CORTEXM_DHCSR);
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}
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/* ADIV5_DP_CTRLSTAT_READOK is always set e.g. on STM32F7 even so
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CORTEXM_DHCS reads nonsense*/
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/* On a sleeping STM32F7, invalid DHCSR reads with e.g. 0xffffffff and
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