Rewrite STM32F4 stub in C and use new interface.
This commit is contained in:
Gareth McMullin
parent
8ddb186b35
commit
acfd258aa7
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@ -8,7 +8,7 @@ ifneq ($(V), 1)
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Q = @
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endif
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CFLAGS=-mcpu=cortex-m3 -mthumb -I../libopencm3/include
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CFLAGS=-Os -std=gnu99 -mcpu=cortex-m3 -mthumb -I../libopencm3/include
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ASFLAGS=-mcpu=cortex-m3 -mthumb
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all: lmi.stub stm32f4.stub nrf51.stub stm32f1.stub
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@ -17,6 +17,10 @@ stm32f1.o: stm32f1.c
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$(Q)echo " CC $<"
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$(Q)$(CC) $(CFLAGS) -DSTM32F1 -o $@ -c $<
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stm32f4.o: stm32f4.c
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$(Q)echo " CC $<"
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$(Q)$(CC) $(CFLAGS) -DSTM32F4 -o $@ -c $<
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%.o: %.s
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$(Q)echo " AS $<"
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$(Q)$(AS) $(ASFLAGS) -o $@ $<
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@ -0,0 +1,40 @@
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/*
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* This file is part of the Black Magic Debug project.
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*
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* Copyright (C) 2015 Black Sphere Technologies Ltd.
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* Written by Gareth McMullin <gareth@blacksphere.co.nz>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "libopencm3/stm32/flash.h"
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#include "stub.h"
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#define SR_ERROR_MASK 0xF2
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void __attribute__((naked))
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stm32f4_flash_write_stub(uint32_t *dest, uint32_t *src, uint32_t size)
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{
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for (int i = 0; i < size; i += 4) {
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FLASH_CR = FLASH_CR_PROGRAM_X32 | FLASH_CR_PG;
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*dest++ = *src++;
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while (FLASH_SR & FLASH_SR_BSY)
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;
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}
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if (FLASH_SR & SR_ERROR_MASK)
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stub_exit(1);
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stub_exit(0);
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}
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@ -1,44 +0,0 @@
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.global _start
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_start:
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ldr r0, _flashbase
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ldr r1, _addr
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mov r2, pc
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add r2, #(_data - . - 2)
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ldr r3, _size
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ldr r5, _cr
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_next:
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cbz r3, _done
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@ Write PG command to FLASH_CR
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str r5, [r0, #0x10]
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@ Write data to flash (word)
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ldr r4, [r2]
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str r4, [r1]
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_wait: @ Wait for BSY bit to clear
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ldrh r4, [r0, #0x0E]
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mov r6, #1
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tst r4, r6
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bne _wait
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sub r3, #4
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add r1, #4
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add r2, #4
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b _next
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_done:
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bkpt
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@.align 4
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.org 0x28
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_cr:
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.word 0x00000201
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_flashbase:
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.word 0x40023C00
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_addr:
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.word 0x0800bf78
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_size:
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.word 8
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_data:
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.word 0xAAAAAAAA
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.word 0xBBBBBBBB
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.word 0xCCCCCCCC
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@ -0,0 +1 @@
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0x2300, 0x4293, 0x4C09, 0xD20B, 0x4D09, 0xF240, 0x2601, 0x602E, 0x58CD, 0x50C5, 0x6825, 0xF415, 0x3F80, 0xD1FB, 0x3304, 0xE7F0, 0x6823, 0xF013, 0x0FF2, 0xD000, 0xBE01, 0xBE00, 0x3C0C, 0x4002, 0x3C10, 0x4002,
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@ -33,6 +33,7 @@
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#include "general.h"
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#include "adiv5.h"
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#include "target.h"
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#include "cortexm.h"
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#include "command.h"
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#include "gdb_packet.h"
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@ -120,44 +121,12 @@ static const char stm32f4_xml_memory_map[] = "<?xml version=\"1.0\"?>"
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/* This routine is uses word access. Only usable on target voltage >2.7V */
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static const uint16_t stm32f4_flash_write_stub[] = {
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// _start:
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0x480a, // ldr r0, [pc, #40] // _flashbase
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0x490b, // ldr r1, [pc, #44] // _addr
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0x467a, // mov r2, pc
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0x3230, // adds r2, #48
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0x4b0a, // ldr r3, [pc, #36] // _size
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0x4d07, // ldr r5, [pc, #28] // _cr
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// _next:
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0xb153, // cbz r3, _done
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0x6105, // str r5, [r0, #16]
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0x6814, // ldr r4, [r2]
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0x600c, // str r4, [r1]
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// _wait:
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0x89c4, // ldrb r4, [r0, #14]
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0x2601, // movs r6, #1
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0x4234, // tst r4, r6
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0xd1fb, // bne _wait
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0x3b04, // subs r3, #4
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0x3104, // adds r1, #4
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0x3204, // adds r2, #4
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0xe7f3, // b _next
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// _done:
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0xbe00, // bkpt
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0x0000,
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// .org 0x28
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//_cr:
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0x0201, 0x0000, //.word 0x00000201 (Value to write to FLASH_CR) */
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// _flashbase:
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0x3c00, 0x4002, // .word 0x40023c00 (FPEC_BASE)
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// _addr:
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// 0x0000, 0x0000,
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// _size:
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// 0x0000, 0x0000,
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// _data:
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// ...
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#include "../flashstub/stm32f4.stub"
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};
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#define SRAM_BASE 0x20000000
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#define STUB_BUFFER_BASE ALIGN(SRAM_BASE + sizeof(stm32f4_flash_write_stub), 4)
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bool stm32f4_probe(struct target_s *target)
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{
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uint32_t idcode;
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@ -239,34 +208,19 @@ static int stm32f4_flash_write(struct target_s *target, uint32_t dest,
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const uint8_t *src, size_t len)
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{
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uint32_t offset = dest % 4;
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uint32_t words = (offset + len + 3) / 4;
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uint32_t data[2 + words];
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uint16_t sr;
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uint8_t data[ALIGN(offset + len, 4)];
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/* Construct data buffer used by stub */
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data[0] = dest - offset;
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data[1] = words * 4; /* length must always be a multiple of 4 */
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data[2] = 0xFFFFFFFF; /* pad partial words with all 1s to avoid */
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data[words + 1] = 0xFFFFFFFF; /* damaging overlapping areas */
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memcpy((uint8_t *)&data[2] + offset, src, len);
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/* pad partial words with all 1s to avoid damaging overlapping areas */
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memset(data, 0xff, sizeof(data));
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memcpy((uint8_t *)data + offset, src, len);
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/* Write stub and data to target ram and set PC */
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target_mem_write(target, 0x20000000, stm32f4_flash_write_stub, 0x30);
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target_mem_write(target, 0x20000030, data, sizeof(data));
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target_pc_write(target, 0x20000000);
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if(target_check_error(target))
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return -1;
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/* Execute the stub */
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target_halt_resume(target, 0);
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while(!target_halt_wait(target));
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/* Check for error */
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sr = target_mem_read32(target, FLASH_SR);
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if(sr & SR_ERROR_MASK)
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return -1;
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return 0;
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/* Write buffer to target ram call stub */
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target_mem_write(target, STUB_BUFFER_BASE, data, sizeof(data));
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return cortexm_run_stub(target, SRAM_BASE, stm32f4_flash_write_stub,
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sizeof(stm32f4_flash_write_stub),
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dest - offset, STUB_BUFFER_BASE, sizeof(data),
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0);
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}
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static bool stm32f4_cmd_erase_mass(target *t)
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