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misc: Renamed CORTEXM_TOPT_INHIBIT_NRST to clarify usage and align naming

This commit is contained in:
dragonmux 2022-06-25 17:26:02 -04:00 committed by Piotr Esden-Tempski
parent 5edf549b48
commit b226c53d13
8 changed files with 12 additions and 14 deletions
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4
src/target/cortexm.c
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@ -742,7 +742,7 @@ static void cortexm_reset(target *t)
/* Read DHCSR here to clear S_RESET_ST bit before reset */ /* Read DHCSR here to clear S_RESET_ST bit before reset */
target_mem_read32(t, CORTEXM_DHCSR); target_mem_read32(t, CORTEXM_DHCSR);
platform_timeout to; platform_timeout to;
if ((t->target_options & CORTEXM_TOPT_INHIBIT_SRST) == 0) { if ((t->target_options & CORTEXM_TOPT_INHIBIT_NRST) == 0) {
platform_nrst_set_val(true); platform_nrst_set_val(true);
platform_nrst_set_val(false); platform_nrst_set_val(false);
/* Some NRF52840 users saw invalid SWD transaction with /* Some NRF52840 users saw invalid SWD transaction with
@ -752,7 +752,7 @@ static void cortexm_reset(target *t)
uint32_t dhcsr = target_mem_read32(t, CORTEXM_DHCSR); uint32_t dhcsr = target_mem_read32(t, CORTEXM_DHCSR);
if ((dhcsr & CORTEXM_DHCSR_S_RESET_ST) == 0) { if ((dhcsr & CORTEXM_DHCSR_S_RESET_ST) == 0) {
/* No reset seen yet, maybe as nRST is not connected, or device has /* No reset seen yet, maybe as nRST is not connected, or device has
* CORTEXM_TOPT_INHIBIT_SRST set. * CORTEXM_TOPT_INHIBIT_NRST set.
* Trigger reset by AIRCR.*/ * Trigger reset by AIRCR.*/
target_mem_write32(t, CORTEXM_AIRCR, target_mem_write32(t, CORTEXM_AIRCR,
CORTEXM_AIRCR_VECTKEY | CORTEXM_AIRCR_SYSRESETREQ); CORTEXM_AIRCR_VECTKEY | CORTEXM_AIRCR_SYSRESETREQ);

3
src/target/cortexm.h
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@ -170,7 +170,7 @@ extern unsigned cortexm_wait_timeout;
#define ARM_THUMB_BREAKPOINT 0xBE00 #define ARM_THUMB_BREAKPOINT 0xBE00
#define CORTEXM_XPSR_THUMB (1 << 24) #define CORTEXM_XPSR_THUMB (1 << 24)
#define CORTEXM_TOPT_INHIBIT_SRST (1 << 2) #define CORTEXM_TOPT_INHIBIT_NRST (1 << 2)
enum cortexm_types { enum cortexm_types {
CORTEX_M0 = 0xc200, CORTEX_M0 = 0xc200,
@ -196,4 +196,3 @@ int cortexm_mem_write_sized(
target *t, target_addr dest, const void *src, size_t len, enum align align); target *t, target_addr dest, const void *src, size_t len, enum align align);
#endif #endif

2
src/target/efm32.c
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@ -648,7 +648,7 @@ bool efm32_probe(target *t)
device->name, part_number, flash_kib, device->description); device->name, part_number, flash_kib, device->description);
/* Setup Target */ /* Setup Target */
t->target_options |= CORTEXM_TOPT_INHIBIT_SRST; t->target_options |= CORTEXM_TOPT_INHIBIT_NRST;
t->driver = priv_storage->efm32_variant_string; t->driver = priv_storage->efm32_variant_string;
tc_printf(t, "flash size %d page size %d\n", flash_size, flash_page_size); tc_printf(t, "flash size %d page size %d\n", flash_size, flash_page_size);
target_add_ram (t, SRAM_BASE, ram_size); target_add_ram (t, SRAM_BASE, ram_size);

6
src/target/lmi.c
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@ -91,21 +91,21 @@ bool lmi_probe(target *t)
/* On Tiva targets, asserting nRST results in the debug /* On Tiva targets, asserting nRST results in the debug
* logic also being reset. We can't assert nRST and must * logic also being reset. We can't assert nRST and must
* only use the AIRCR SYSRESETREQ. */ * only use the AIRCR SYSRESETREQ. */
t->target_options |= CORTEXM_TOPT_INHIBIT_SRST; t->target_options |= CORTEXM_TOPT_INHIBIT_NRST;
return true; return true;
case 0x1022: /* TM4C1230C3PM */ case 0x1022: /* TM4C1230C3PM */
t->driver = lmi_driver_str; t->driver = lmi_driver_str;
target_add_ram(t, 0x20000000, 0x6000); target_add_ram(t, 0x20000000, 0x6000);
lmi_add_flash(t, 0x10000); lmi_add_flash(t, 0x10000);
t->target_options |= CORTEXM_TOPT_INHIBIT_SRST; t->target_options |= CORTEXM_TOPT_INHIBIT_NRST;
return true; return true;
case 0x101F: /* TM4C1294NCPDT */ case 0x101F: /* TM4C1294NCPDT */
t->driver = lmi_driver_str; t->driver = lmi_driver_str;
target_add_ram(t, 0x20000000, 0x40000); target_add_ram(t, 0x20000000, 0x40000);
lmi_add_flash(t, 0x100000); lmi_add_flash(t, 0x100000);
t->target_options |= CORTEXM_TOPT_INHIBIT_SRST; t->target_options |= CORTEXM_TOPT_INHIBIT_NRST;
return true; return true;
} }
return false; return false;

3
src/target/lpc43xx.c
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@ -107,7 +107,7 @@ bool lpc43xx_probe(target *t)
0x1B010000, 0x70000, 0x10000); 0x1B010000, 0x70000, 0x10000);
target_add_commands(t, lpc43xx_cmd_list, "LPC43xx"); target_add_commands(t, lpc43xx_cmd_list, "LPC43xx");
target_add_ram(t, 0x1B080000, 0xE4F80000UL); target_add_ram(t, 0x1B080000, 0xE4F80000UL);
t->target_options |= CORTEXM_TOPT_INHIBIT_SRST; t->target_options |= CORTEXM_TOPT_INHIBIT_NRST;
} }
break; break;
case 0x4100C200: case 0x4100C200:
@ -262,4 +262,3 @@ static void lpc43xx_wdt_pet(target *t)
target_mem_write32(t, LPC43XX_WDT_FEED, 0xFF); target_mem_write32(t, LPC43XX_WDT_FEED, 0xFF);
} }
} }

2
src/target/lpc546xx.c
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@ -161,7 +161,7 @@ bool lpc546xx_probe(target *t)
*/ */
target_add_ram(t, 0x20000000, 0x28000); target_add_ram(t, 0x20000000, 0x28000);
target_add_commands(t, lpc546xx_cmd_list, "Lpc546xx"); target_add_commands(t, lpc546xx_cmd_list, "Lpc546xx");
t->target_options |= CORTEXM_TOPT_INHIBIT_SRST; t->target_options |= CORTEXM_TOPT_INHIBIT_NRST;
return true; return true;
} }

4
src/target/nrf51.c
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@ -135,7 +135,7 @@ bool nrf51_probe(target *t)
((info_part & 0x00ff000) == 0x52000)) { ((info_part & 0x00ff000) == 0x52000)) {
uint32_t ram_size = target_mem_read32(t, NRF52_INFO_RAM); uint32_t ram_size = target_mem_read32(t, NRF52_INFO_RAM);
t->driver = "Nordic nRF52"; t->driver = "Nordic nRF52";
t->target_options |= CORTEXM_TOPT_INHIBIT_SRST; t->target_options |= CORTEXM_TOPT_INHIBIT_NRST;
target_add_ram(t, 0x20000000, ram_size * 1024); target_add_ram(t, 0x20000000, ram_size * 1024);
nrf51_add_flash(t, 0, page_size * code_size, page_size); nrf51_add_flash(t, 0, page_size * code_size, page_size);
nrf51_add_flash(t, NRF51_UICR, page_size, page_size); nrf51_add_flash(t, NRF51_UICR, page_size, page_size);
@ -147,7 +147,7 @@ bool nrf51_probe(target *t)
* IDCODE is kept as '0', as deciphering is hard and * IDCODE is kept as '0', as deciphering is hard and
* there is later no usage.*/ * there is later no usage.*/
target_add_ram(t, 0x20000000, 0x8000); target_add_ram(t, 0x20000000, 0x8000);
t->target_options |= CORTEXM_TOPT_INHIBIT_SRST; t->target_options |= CORTEXM_TOPT_INHIBIT_NRST;
nrf51_add_flash(t, 0, page_size * code_size, page_size); nrf51_add_flash(t, 0, page_size * code_size, page_size);
nrf51_add_flash(t, NRF51_UICR, page_size, page_size); nrf51_add_flash(t, NRF51_UICR, page_size, page_size);
target_add_commands(t, nrf51_cmd_list, "nRF51"); target_add_commands(t, nrf51_cmd_list, "nRF51");

2
src/target/rp.c
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@ -520,7 +520,7 @@ bool rp_probe(target *t)
t->target_storage = (void*)priv_storage; t->target_storage = (void*)priv_storage;
t->driver = RP_ID; t->driver = RP_ID;
t->target_options |= CORTEXM_TOPT_INHIBIT_SRST; t->target_options |= CORTEXM_TOPT_INHIBIT_NRST;
t->attach = rp_attach; t->attach = rp_attach;
t->detach = rp_detach; t->detach = rp_detach;
target_add_commands(t, rp_cmd_list, RP_ID); target_add_commands(t, rp_cmd_list, RP_ID);