target: stm32l4: add support for STM32WLxx
This adds support for the STM32WL series in stm32l4.c. These parts have the same flash registers layout as the L4 series, but a different base. Since there are already two sets of registers in this target file, this adds support for register maps that can be customized for each device ID.
This commit is contained in:
Fabio Baltieri
UweBonnes
parent
21b80949ff
commit
beaccf2714
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@ -56,31 +56,12 @@ static int stm32l4_flash_write(struct target_flash *f,
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target_addr dest, const void *src, size_t len);
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/* Flash Program ad Erase Controller Register Map */
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#define FPEC_BASE 0x40022000
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#define L4_FLASH_ACR (FPEC_BASE+0x00)
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#define L4_FLASH_KEYR (FPEC_BASE+0x08)
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#define L4_FLASH_OPTKEYR (FPEC_BASE+0x0c)
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#define L4_FLASH_SR (FPEC_BASE+0x10)
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#define L4_FLASH_CR (FPEC_BASE+0x14)
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#define L4_FLASH_OPTR (FPEC_BASE+0x20)
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//#define FLASH_OPTCR (FPEC_BASE+0x14)
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#define L5_FPEC_BASE 0x40022000
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#define L5_FLASH_ACR (L5_FPEC_BASE+0x00)
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#define L5_FLASH_KEYR (L5_FPEC_BASE+0x08)
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#define L5_FLASH_OPTKEYR (L5_FPEC_BASE+0x10)
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#define L5_FLASH_SR (L5_FPEC_BASE+0x20)
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#define L5_FLASH_CR (L5_FPEC_BASE+0x28)
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#define L5_FLASH_OPTR (L5_FPEC_BASE+0x40)
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#define L4_FPEC_BASE 0x40022000
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#define L5_FPEC_BASE 0x40022000
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#define WL_FPEC_BASE 0x58004000
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#define L5_FLASH_OPTR_TZEN (1 << 31)
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#define FLASH_KEYR(x) ((x == ID_STM32L55) ? L5_FLASH_KEYR : L4_FLASH_KEYR)
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#define FLASH_SR(x) ((x == ID_STM32L55) ? L5_FLASH_SR : L4_FLASH_SR)
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#define FLASH_CR(x) ((x == ID_STM32L55) ? L5_FLASH_CR : L4_FLASH_CR)
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#define FLASH_OPTR(x) ((x == ID_STM32L55) ? L5_FLASH_OPTR : L4_FLASH_OPTR)
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#define FLASH_OPTKEYR(x) ((x == ID_STM32L55) ? L5_FLASH_OPTKEYR : L4_FLASH_OPTKEYR)
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#define FLASH_CR_PG (1 << 0)
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#define FLASH_CR_PER (1 << 1)
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#define FLASH_CR_MER1 (1 << 2)
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@ -138,7 +119,6 @@ enum {
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};
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#define L4_FLASH_SIZE_REG 0x1FFF75E0
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#define L5_FLASH_SIZE_REG 0x0bfa05e0
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#define FLASH_SIZE_REG(x) ((x == ID_STM32L55) ? L5_FLASH_SIZE_REG : L4_FLASH_SIZE_REG)
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struct stm32l4_flash {
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struct target_flash f;
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@ -160,6 +140,7 @@ enum ID_STM32L4 {
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ID_STM32G47 = 0x469u, /* RM0440, Rev.1 */
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ID_STM32G49 = 0x479u, /* RM0440, Rev.6 */
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ID_STM32L55 = 0x472u, /* RM0438, Rev.4 */
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ID_STM32WLXX = 0x497u, /* RM0461, Rev.3, RM453, Rev.1 */
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};
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enum FAM_STM32L4 {
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@ -167,12 +148,50 @@ enum FAM_STM32L4 {
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FAM_STM32L4Rx = 2,
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FAM_STM32WBxx = 4,
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FAM_STM32G4xx = 5,
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FAM_STM32L55x,
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FAM_STM32L55x = 6,
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FAM_STM32WLxx = 7,
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};
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#define DUAL_BANK 0x80u
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#define RAM_COUNT_MSK 0x07u
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enum stm32l4_flash_regs {
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FLASH_KEYR,
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FLASH_OPTKEYR,
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FLASH_SR,
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FLASH_CR,
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FLASH_OPTR,
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FLASHSIZE,
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FLASH_REGS_COUNT
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};
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static const uint32_t stm32l4_flash_regs_map[FLASH_REGS_COUNT] = {
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L4_FPEC_BASE + 0x08, /* KEYR */
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L4_FPEC_BASE + 0x0c, /* OPTKEYR */
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L4_FPEC_BASE + 0x10, /* SR */
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L4_FPEC_BASE + 0x14, /* CR */
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L4_FPEC_BASE + 0x20, /* OPTR */
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L4_FLASH_SIZE_REG, /* FLASHSIZE */
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};
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static const uint32_t stm32l5_flash_regs_map[FLASH_REGS_COUNT] = {
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L5_FPEC_BASE + 0x08, /* KEYR */
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L5_FPEC_BASE + 0x10, /* OPTKEYR */
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L5_FPEC_BASE + 0x20, /* SR */
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L5_FPEC_BASE + 0x28, /* CR */
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L5_FPEC_BASE + 0x40, /* OPTR */
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L5_FLASH_SIZE_REG, /* FLASHSIZE */
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};
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static const uint32_t stm32wl_flash_regs_map[FLASH_REGS_COUNT] = {
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WL_FPEC_BASE + 0x08, /* KEYR */
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WL_FPEC_BASE + 0x0c, /* OPTKEYR */
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WL_FPEC_BASE + 0x10, /* SR */
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WL_FPEC_BASE + 0x14, /* CR */
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WL_FPEC_BASE + 0x20, /* OPTR */
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L4_FLASH_SIZE_REG, /* FLASHSIZE */
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};
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struct stm32l4_info {
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char designator[10];
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uint16_t sram1; /* Normal SRAM mapped at 0x20000000*/
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@ -181,6 +200,7 @@ struct stm32l4_info {
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enum ID_STM32L4 idcode;
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enum FAM_STM32L4 family;
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uint8_t flags; /* Only DUAL_BANK is evaluated for now.*/
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const uint32_t *flash_regs_map;
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};
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static struct stm32l4_info const L4info[] = {
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@ -191,6 +211,7 @@ static struct stm32l4_info const L4info[] = {
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.sram1 = 32,
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.sram2 = 8,
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.flags = 2,
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.flash_regs_map = stm32l4_flash_regs_map,
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},
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{
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.idcode = ID_STM32L43,
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@ -199,6 +220,7 @@ static struct stm32l4_info const L4info[] = {
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.sram1 = 48,
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.sram2 = 16,
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.flags = 2,
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.flash_regs_map = stm32l4_flash_regs_map,
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},
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{
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.idcode = ID_STM32L45,
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@ -207,6 +229,7 @@ static struct stm32l4_info const L4info[] = {
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.sram1 = 128,
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.sram2 = 32,
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.flags = 2,
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.flash_regs_map = stm32l4_flash_regs_map,
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},
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{
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.idcode = ID_STM32L47,
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@ -215,6 +238,7 @@ static struct stm32l4_info const L4info[] = {
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.sram1 = 96,
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.sram2 = 32,
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.flags = 2 | DUAL_BANK,
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.flash_regs_map = stm32l4_flash_regs_map,
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},
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{
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.idcode = ID_STM32L49,
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@ -223,6 +247,7 @@ static struct stm32l4_info const L4info[] = {
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.sram1 = 256,
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.sram2 = 64,
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.flags = 2 | DUAL_BANK,
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.flash_regs_map = stm32l4_flash_regs_map,
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},
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{
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.idcode = ID_STM32L4R,
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@ -232,6 +257,7 @@ static struct stm32l4_info const L4info[] = {
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.sram2 = 64,
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.sram3 = 384,
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.flags = 3 | DUAL_BANK,
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.flash_regs_map = stm32l4_flash_regs_map,
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},
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{
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.idcode = ID_STM32G43,
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@ -239,6 +265,7 @@ static struct stm32l4_info const L4info[] = {
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.designator = "STM32G43",
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.sram1 = 22,
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.sram2 = 10,
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.flash_regs_map = stm32l4_flash_regs_map,
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},
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{
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.idcode = ID_STM32G47,
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@ -247,6 +274,7 @@ static struct stm32l4_info const L4info[] = {
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.sram1 = 96, /* SRAM1 and SRAM2 are mapped continuous */
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.sram2 = 32, /* CCM SRAM is mapped as per SRAM2 on G4 */
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.flags = 2,
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.flash_regs_map = stm32l4_flash_regs_map,
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},
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{
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.idcode = ID_STM32G49,
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@ -255,6 +283,7 @@ static struct stm32l4_info const L4info[] = {
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.sram1 = 96, /* SRAM1 and SRAM2 are mapped continuously */
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.sram2 = 16, /* CCM SRAM is mapped as per SRAM2 on G4 */
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.flags = 2,
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.flash_regs_map = stm32l4_flash_regs_map,
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},
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{
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.idcode = ID_STM32L55,
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@ -263,6 +292,16 @@ static struct stm32l4_info const L4info[] = {
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.sram1 = 192, /* SRAM1 and SRAM2 are mapped continuous */
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.sram2 = 64,
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.flags = 2,
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.flash_regs_map = stm32l5_flash_regs_map,
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},
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{
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.idcode = ID_STM32WLXX,
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.family = FAM_STM32WLxx,
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.designator = "STM32WLxx",
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.sram1 = 64,
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.sram2 = 32,
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.flags = 2,
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.flash_regs_map = stm32wl_flash_regs_map,
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},
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{
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/* Terminator */
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@ -279,6 +318,27 @@ static struct stm32l4_info const * stm32l4_get_chip_info(uint32_t idcode) {
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return p;
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}
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static uint32_t stm32l4_flash_read16(target *t, enum stm32l4_flash_regs reg)
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{
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struct stm32l4_info const *chip = stm32l4_get_chip_info(t->idcode);
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uint32_t addr = chip->flash_regs_map[reg];
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return target_mem_read16(t, addr);
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}
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static uint32_t stm32l4_flash_read32(target *t, enum stm32l4_flash_regs reg)
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{
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struct stm32l4_info const *chip = stm32l4_get_chip_info(t->idcode);
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uint32_t addr = chip->flash_regs_map[reg];
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return target_mem_read32(t, addr);
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}
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static void stm32l4_flash_write32(target *t, enum stm32l4_flash_regs reg, uint32_t value)
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{
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struct stm32l4_info const *chip = stm32l4_get_chip_info(t->idcode);
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uint32_t addr = chip->flash_regs_map[reg];
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target_mem_write32(t, addr, value);
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}
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static void stm32l4_add_flash(target *t,
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uint32_t addr, size_t length, size_t blocksize,
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uint32_t bank1_start)
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@ -354,9 +414,9 @@ static bool stm32l4_attach(target *t)
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chip->sram1 : (chip->sram1 + chip->sram2 + chip->sram3);
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target_add_ram(t, 0x20000000, ramsize << 10);
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uint32_t size = target_mem_read16(t, FLASH_SIZE_REG(t->idcode));
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uint32_t size = stm32l4_flash_read16(t, FLASHSIZE);
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/* Add the flash to memory map. */
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uint32_t options = target_mem_read32(t, FLASH_OPTR(t->idcode));
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uint32_t options = stm32l4_flash_read32(t, FLASH_OPTR);
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if (chip->family == FAM_STM32L4Rx) {
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/* rm0432 Rev. 2 does not mention 1 MB devices or explain DB1M.*/
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@ -408,7 +468,7 @@ static bool stm32l4_attach(target *t)
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stm32l4_add_flash(t, 0x08000000, size << 10, 0x800, -1);
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/* Clear all errors in the status register. */
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target_mem_write32(t, FLASH_SR(t->idcode), target_mem_read32(t, FLASH_SR(t->idcode)));
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stm32l4_flash_write32(t, FLASH_SR, stm32l4_flash_read32(t, FLASH_SR));
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return true;
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}
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@ -429,7 +489,7 @@ bool stm32l4_probe(target *t)
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ADIv5_AP_t *ap = cortexm_ap(t);
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if (ap->dp->idcode == 0x0Be12477) {
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idcode_reg = STM32L5_DBGMCU_IDCODE_PHYS;
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if ((target_mem_read32(t, L5_FLASH_OPTR)) & L5_FLASH_OPTR_TZEN) {
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if ((stm32l4_flash_read32(t, FLASH_OPTR)) & L5_FLASH_OPTR_TZEN) {
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DEBUG_WARN("STM32L5 Trust Zone enabled\n");
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}
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}
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@ -450,10 +510,10 @@ bool stm32l4_probe(target *t)
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static void stm32l4_flash_unlock(target *t)
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{
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if ((target_mem_read32(t, FLASH_CR(t->idcode))) & FLASH_CR_LOCK) {
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if ((stm32l4_flash_read32(t, FLASH_CR)) & FLASH_CR_LOCK) {
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/* Enable FPEC controller access */
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target_mem_write32(t, FLASH_KEYR(t->idcode), KEY1);
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target_mem_write32(t, FLASH_KEYR(t->idcode), KEY2);
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stm32l4_flash_write32(t, FLASH_KEYR, KEY1);
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stm32l4_flash_write32(t, FLASH_KEYR, KEY2);
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}
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}
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@ -468,11 +528,11 @@ static int stm32l4_flash_erase(struct target_flash *f, target_addr addr, size_t
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stm32l4_flash_unlock(t);
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/* Read FLASH_SR to poll for BSY bit */
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while(target_mem_read32(t, FLASH_SR(t->idcode)) & FLASH_SR_BSY)
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while(stm32l4_flash_read32(t, FLASH_SR) & FLASH_SR_BSY)
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if(target_check_error(t))
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return -1;
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/* Fixme: OPTVER always set after reset! Wrong option defaults?*/
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target_mem_write32(t, FLASH_SR(t->idcode), target_mem_read32(t, FLASH_SR(t->idcode)));
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stm32l4_flash_write32(t, FLASH_SR, stm32l4_flash_read32(t, FLASH_SR));
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page = (addr - 0x08000000) / blocksize;
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while(len) {
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uint32_t cr;
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@ -481,13 +541,13 @@ static int stm32l4_flash_erase(struct target_flash *f, target_addr addr, size_t
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if (addr >= bank1_start)
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cr |= FLASH_CR_BKER;
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/* Flash page erase instruction */
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target_mem_write32(t, FLASH_CR(t->idcode), cr);
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stm32l4_flash_write32(t, FLASH_CR, cr);
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/* write address to FMA */
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cr |= FLASH_CR_STRT;
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target_mem_write32(t, FLASH_CR(t->idcode), cr);
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stm32l4_flash_write32(t, FLASH_CR, cr);
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/* Read FLASH_SR to poll for BSY bit */
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while(target_mem_read32(t, FLASH_SR(t->idcode)) & FLASH_SR_BSY)
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while(stm32l4_flash_read32(t, FLASH_SR) & FLASH_SR_BSY)
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if(target_check_error(t))
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return -1;
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if (len > blocksize)
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@ -499,7 +559,7 @@ static int stm32l4_flash_erase(struct target_flash *f, target_addr addr, size_t
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}
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/* Check for error */
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sr = target_mem_read32(t, FLASH_SR(t->idcode));
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sr = stm32l4_flash_read32(t, FLASH_SR);
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if(sr & FLASH_SR_ERROR_MASK)
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return -1;
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@ -510,12 +570,12 @@ static int stm32l4_flash_write(struct target_flash *f,
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target_addr dest, const void *src, size_t len)
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{
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target *t = f->t;
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target_mem_write32(t, FLASH_CR(t->idcode), FLASH_CR_PG);
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stm32l4_flash_write32(t, FLASH_CR, FLASH_CR_PG);
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target_mem_write(t, dest, src, len);
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/* Wait for completion or an error */
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uint32_t sr;
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do {
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sr = target_mem_read32(t, FLASH_SR(t->idcode));
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sr = stm32l4_flash_read32(t, FLASH_SR);
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if (target_check_error(t)) {
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DEBUG_WARN("stm32l4 flash write: comm error\n");
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return -1;
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@ -534,18 +594,18 @@ static bool stm32l4_cmd_erase(target *t, uint32_t action)
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stm32l4_flash_unlock(t);
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/* Erase time is 25 ms. No need for a spinner.*/
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/* Flash erase action start instruction */
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target_mem_write32(t, FLASH_CR(t->idcode), action);
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target_mem_write32(t, FLASH_CR(t->idcode), action | FLASH_CR_STRT);
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stm32l4_flash_write32(t, FLASH_CR, action);
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stm32l4_flash_write32(t, FLASH_CR, action | FLASH_CR_STRT);
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/* Read FLASH_SR to poll for BSY bit */
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while (target_mem_read32(t, FLASH_SR(t->idcode)) & FLASH_SR_BSY) {
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while (stm32l4_flash_read32(t, FLASH_SR) & FLASH_SR_BSY) {
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if(target_check_error(t)) {
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return false;
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}
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}
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/* Check for error */
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uint16_t sr = target_mem_read32(t, FLASH_SR(t->idcode));
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uint16_t sr = stm32l4_flash_read32(t, FLASH_SR);
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if (sr & FLASH_SR_ERROR_MASK)
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return false;
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return true;
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@ -585,22 +645,22 @@ static bool stm32l4_option_write(
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{
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tc_printf(t, "Device will lose connection. Rescan!\n");
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stm32l4_flash_unlock(t);
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target_mem_write32(t, FLASH_OPTKEYR(t->idcode), OPTKEY1);
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target_mem_write32(t, FLASH_OPTKEYR(t->idcode), OPTKEY2);
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while (target_mem_read32(t, FLASH_SR(t->idcode)) & FLASH_SR_BSY)
|
||||
stm32l4_flash_write32(t, FLASH_OPTKEYR, OPTKEY1);
|
||||
stm32l4_flash_write32(t, FLASH_OPTKEYR, OPTKEY2);
|
||||
while (stm32l4_flash_read32(t, FLASH_SR) & FLASH_SR_BSY)
|
||||
if(target_check_error(t))
|
||||
return true;
|
||||
for (int i = 0; i < len; i++)
|
||||
target_mem_write32(t, FPEC_BASE + i2offset[i], values[i]);
|
||||
target_mem_write32(t, FLASH_CR(t->idcode), FLASH_CR_OPTSTRT);
|
||||
while (target_mem_read32(t, FLASH_SR(t->idcode)) & FLASH_SR_BSY)
|
||||
target_mem_write32(t, L4_FPEC_BASE + i2offset[i], values[i]);
|
||||
stm32l4_flash_write32(t, FLASH_CR, FLASH_CR_OPTSTRT);
|
||||
while (stm32l4_flash_read32(t, FLASH_SR) & FLASH_SR_BSY)
|
||||
if(target_check_error(t))
|
||||
return true;
|
||||
target_mem_write32(t, FLASH_CR(t->idcode), FLASH_CR_OBL_LAUNCH);
|
||||
while (target_mem_read32(t, FLASH_CR(t->idcode)) & FLASH_CR_OBL_LAUNCH)
|
||||
stm32l4_flash_write32(t, FLASH_CR, FLASH_CR_OBL_LAUNCH);
|
||||
while (stm32l4_flash_read32(t, FLASH_CR) & FLASH_CR_OBL_LAUNCH)
|
||||
if(target_check_error(t))
|
||||
return true;
|
||||
target_mem_write32(t, FLASH_CR(t->idcode), FLASH_CR_LOCK);
|
||||
stm32l4_flash_write32(t, FLASH_CR, FLASH_CR_LOCK);
|
||||
return false;
|
||||
}
|
||||
|
||||
|
|
@ -626,6 +686,10 @@ static bool stm32l4_cmd_option(target *t, int argc, char *argv[])
|
|||
tc_printf(t, "STM32L5 options not implemented!\n");
|
||||
return false;
|
||||
}
|
||||
if (t->idcode == ID_STM32WLXX) {
|
||||
tc_printf(t, "STM32WLxx options not implemented!\n");
|
||||
return false;
|
||||
}
|
||||
static const uint32_t g4_values[11] = {
|
||||
/* SEC_SIZE1 occupies 9 bits on G49/G4A (cat 4),
|
||||
* 8 bits on cat 3 and 7 bits on cat 2.
|
||||
|
|
@ -664,7 +728,7 @@ static bool stm32l4_cmd_option(target *t, int argc, char *argv[])
|
|||
for (i = 2; i < argc; i++)
|
||||
values[i - 2] = strtoul(argv[i], NULL, 0);
|
||||
for (i = i - 2; i < len; i++) {
|
||||
uint32_t addr = FPEC_BASE + i2offset[i];
|
||||
uint32_t addr = L4_FPEC_BASE + i2offset[i];
|
||||
values[i] = target_mem_read32(t, addr);
|
||||
}
|
||||
if ((values[0] & 0xff) == 0xCC) {
|
||||
|
|
@ -681,8 +745,8 @@ static bool stm32l4_cmd_option(target *t, int argc, char *argv[])
|
|||
return false;
|
||||
}
|
||||
for (int i = 0; i < len; i ++) {
|
||||
uint32_t addr = FPEC_BASE + i2offset[i];
|
||||
val = target_mem_read32(t, FPEC_BASE + i2offset[i]);
|
||||
uint32_t addr = L4_FPEC_BASE + i2offset[i];
|
||||
val = target_mem_read32(t, L4_FPEC_BASE + i2offset[i]);
|
||||
tc_printf(t, "0x%08X: 0x%08X\n", addr, val);
|
||||
}
|
||||
return true;
|
||||
|
|
|
|||
Loading…
Reference in New Issue