rp: Run clang-format
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14882c61ab
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bf0302b076
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@ -627,7 +627,8 @@ static void rp_flash_connect_internal(target *t)
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uint32_t reset = target_mem_read32(t, RP_RESETS_RESET);
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uint32_t reset = target_mem_read32(t, RP_RESETS_RESET);
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target_mem_write32(t, RP_RESETS_RESET, reset | RP_RESETS_RESET_IO_QSPI_BITS | RP_RESETS_RESET_PADS_QSPI_BITS);
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target_mem_write32(t, RP_RESETS_RESET, reset | RP_RESETS_RESET_IO_QSPI_BITS | RP_RESETS_RESET_PADS_QSPI_BITS);
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target_mem_write32(t, RP_RESETS_RESET, reset);
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target_mem_write32(t, RP_RESETS_RESET, reset);
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while (~target_mem_read32(t, RP_RESETS_RESET_DONE) & (RP_RESETS_RESET_IO_QSPI_BITS | RP_RESETS_RESET_PADS_QSPI_BITS));
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while (
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~target_mem_read32(t, RP_RESETS_RESET_DONE) & (RP_RESETS_RESET_IO_QSPI_BITS | RP_RESETS_RESET_PADS_QSPI_BITS));
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// Then mux XIP block onto internal QSPI flash pads
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// Then mux XIP block onto internal QSPI flash pads
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target_mem_write32(t, RP_GPIO_QSPI_SCLK_CTRL, 0);
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target_mem_write32(t, RP_GPIO_QSPI_SCLK_CTRL, 0);
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@ -664,7 +665,8 @@ static void rp_flash_init_spi(target *t)
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// Also allow any unbounded loops to check whether the above abort condition
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// Also allow any unbounded loops to check whether the above abort condition
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// was asserted, and terminate early
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// was asserted, and terminate early
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static int rp_flash_was_aborted(target *t) {
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static int rp_flash_was_aborted(target *t)
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{
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return target_mem_read32(t, RP_GPIO_QSPI_SD1_CTRL) & RP_GPIO_QSPI_SD1_CTRL_INOVER_BITS;
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return target_mem_read32(t, RP_GPIO_QSPI_SD1_CTRL) & RP_GPIO_QSPI_SD1_CTRL_INOVER_BITS;
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}
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}
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@ -676,7 +678,8 @@ static int rp_flash_was_aborted(target *t) {
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// If rx_skip is nonzero, this many bytes will first be consumed from the FIFO,
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// If rx_skip is nonzero, this many bytes will first be consumed from the FIFO,
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// before reading a further count bytes into *rx.
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// before reading a further count bytes into *rx.
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// E.g. if you have written a command+address just before calling this function.
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// E.g. if you have written a command+address just before calling this function.
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static void rp_flash_put_get(target *t, const uint8_t *tx, uint8_t *rx, size_t count, size_t rx_skip) {
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static void rp_flash_put_get(target *t, const uint8_t *tx, uint8_t *rx, size_t count, size_t rx_skip)
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{
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// Make sure there is never more data in flight than the depth of the RX
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// Make sure there is never more data in flight than the depth of the RX
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// FIFO. Otherwise, when we are interrupted for long periods, hardware
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// FIFO. Otherwise, when we are interrupted for long periods, hardware
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// will overflow the RX FIFO.
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// will overflow the RX FIFO.
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@ -728,10 +731,9 @@ static void rp_flash_exit_xip(target *t)
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rp_flash_init_spi(t);
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rp_flash_init_spi(t);
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uint32_t padctrl_save = target_mem_read32(t, RP_PADS_QSPI_GPIO_SD0);
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uint32_t padctrl_save = target_mem_read32(t, RP_PADS_QSPI_GPIO_SD0);
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uint32_t padctrl_tmp = (padctrl_save
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uint32_t padctrl_tmp = (padctrl_save & ~(RP_PADS_QSPI_GPIO_SD0_OD_BITS | RP_PADS_QSPI_GPIO_SD0_PUE_BITS |
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& ~(RP_PADS_QSPI_GPIO_SD0_OD_BITS | RP_PADS_QSPI_GPIO_SD0_PUE_BITS |
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RP_PADS_QSPI_GPIO_SD0_PDE_BITS)) |
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RP_PADS_QSPI_GPIO_SD0_PDE_BITS)
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RP_PADS_QSPI_GPIO_SD0_OD_BITS | RP_PADS_QSPI_GPIO_SD0_PDE_BITS;
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) | RP_PADS_QSPI_GPIO_SD0_OD_BITS | RP_PADS_QSPI_GPIO_SD0_PDE_BITS;
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// First two 32-clock sequences
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// First two 32-clock sequences
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// CSn is held high for the first 32 clocks, then asserted low for next 32
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// CSn is held high for the first 32 clocks, then asserted low for next 32
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@ -749,9 +751,7 @@ static void rp_flash_exit_xip(target *t)
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rp_flash_put_get(t, NULL, NULL, 4, 0);
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rp_flash_put_get(t, NULL, NULL, 4, 0);
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padctrl_tmp = (padctrl_tmp
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padctrl_tmp = (padctrl_tmp & ~RP_PADS_QSPI_GPIO_SD0_PDE_BITS) | RP_PADS_QSPI_GPIO_SD0_PUE_BITS;
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& ~RP_PADS_QSPI_GPIO_SD0_PDE_BITS)
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| RP_PADS_QSPI_GPIO_SD0_PUE_BITS;
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rp_spi_chip_select(t, RP_GPIO_QSPI_CS_DRIVE_LOW);
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rp_spi_chip_select(t, RP_GPIO_QSPI_CS_DRIVE_LOW);
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}
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}
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@ -762,9 +762,7 @@ static void rp_flash_exit_xip(target *t)
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target_mem_write32(t, RP_PADS_QSPI_GPIO_SD0, padctrl_save);
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target_mem_write32(t, RP_PADS_QSPI_GPIO_SD0, padctrl_save);
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target_mem_write32(t, RP_PADS_QSPI_GPIO_SD1, padctrl_save);
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target_mem_write32(t, RP_PADS_QSPI_GPIO_SD1, padctrl_save);
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padctrl_save = (padctrl_save
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padctrl_save = (padctrl_save & ~RP_PADS_QSPI_GPIO_SD0_PDE_BITS) | RP_PADS_QSPI_GPIO_SD0_PUE_BITS;
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& ~RP_PADS_QSPI_GPIO_SD0_PDE_BITS
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) | RP_PADS_QSPI_GPIO_SD0_PUE_BITS;
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target_mem_write32(t, RP_PADS_QSPI_GPIO_SD2, padctrl_save);
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target_mem_write32(t, RP_PADS_QSPI_GPIO_SD2, padctrl_save);
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target_mem_write32(t, RP_PADS_QSPI_GPIO_SD3, padctrl_save);
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target_mem_write32(t, RP_PADS_QSPI_GPIO_SD3, padctrl_save);
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