rp: Run clang-format
This commit is contained in:
parent
14882c61ab
commit
bf0302b076
|
@ -627,7 +627,8 @@ static void rp_flash_connect_internal(target *t)
|
|||
uint32_t reset = target_mem_read32(t, RP_RESETS_RESET);
|
||||
target_mem_write32(t, RP_RESETS_RESET, reset | RP_RESETS_RESET_IO_QSPI_BITS | RP_RESETS_RESET_PADS_QSPI_BITS);
|
||||
target_mem_write32(t, RP_RESETS_RESET, reset);
|
||||
while (~target_mem_read32(t, RP_RESETS_RESET_DONE) & (RP_RESETS_RESET_IO_QSPI_BITS | RP_RESETS_RESET_PADS_QSPI_BITS));
|
||||
while (
|
||||
~target_mem_read32(t, RP_RESETS_RESET_DONE) & (RP_RESETS_RESET_IO_QSPI_BITS | RP_RESETS_RESET_PADS_QSPI_BITS));
|
||||
|
||||
// Then mux XIP block onto internal QSPI flash pads
|
||||
target_mem_write32(t, RP_GPIO_QSPI_SCLK_CTRL, 0);
|
||||
|
@ -664,7 +665,8 @@ static void rp_flash_init_spi(target *t)
|
|||
|
||||
// Also allow any unbounded loops to check whether the above abort condition
|
||||
// was asserted, and terminate early
|
||||
static int rp_flash_was_aborted(target *t) {
|
||||
static int rp_flash_was_aborted(target *t)
|
||||
{
|
||||
return target_mem_read32(t, RP_GPIO_QSPI_SD1_CTRL) & RP_GPIO_QSPI_SD1_CTRL_INOVER_BITS;
|
||||
}
|
||||
|
||||
|
@ -676,7 +678,8 @@ static int rp_flash_was_aborted(target *t) {
|
|||
// If rx_skip is nonzero, this many bytes will first be consumed from the FIFO,
|
||||
// before reading a further count bytes into *rx.
|
||||
// E.g. if you have written a command+address just before calling this function.
|
||||
static void rp_flash_put_get(target *t, const uint8_t *tx, uint8_t *rx, size_t count, size_t rx_skip) {
|
||||
static void rp_flash_put_get(target *t, const uint8_t *tx, uint8_t *rx, size_t count, size_t rx_skip)
|
||||
{
|
||||
// Make sure there is never more data in flight than the depth of the RX
|
||||
// FIFO. Otherwise, when we are interrupted for long periods, hardware
|
||||
// will overflow the RX FIFO.
|
||||
|
@ -728,10 +731,9 @@ static void rp_flash_exit_xip(target *t)
|
|||
rp_flash_init_spi(t);
|
||||
|
||||
uint32_t padctrl_save = target_mem_read32(t, RP_PADS_QSPI_GPIO_SD0);
|
||||
uint32_t padctrl_tmp = (padctrl_save
|
||||
& ~(RP_PADS_QSPI_GPIO_SD0_OD_BITS | RP_PADS_QSPI_GPIO_SD0_PUE_BITS |
|
||||
RP_PADS_QSPI_GPIO_SD0_PDE_BITS)
|
||||
) | RP_PADS_QSPI_GPIO_SD0_OD_BITS | RP_PADS_QSPI_GPIO_SD0_PDE_BITS;
|
||||
uint32_t padctrl_tmp = (padctrl_save & ~(RP_PADS_QSPI_GPIO_SD0_OD_BITS | RP_PADS_QSPI_GPIO_SD0_PUE_BITS |
|
||||
RP_PADS_QSPI_GPIO_SD0_PDE_BITS)) |
|
||||
RP_PADS_QSPI_GPIO_SD0_OD_BITS | RP_PADS_QSPI_GPIO_SD0_PDE_BITS;
|
||||
|
||||
// First two 32-clock sequences
|
||||
// CSn is held high for the first 32 clocks, then asserted low for next 32
|
||||
|
@ -749,9 +751,7 @@ static void rp_flash_exit_xip(target *t)
|
|||
|
||||
rp_flash_put_get(t, NULL, NULL, 4, 0);
|
||||
|
||||
padctrl_tmp = (padctrl_tmp
|
||||
& ~RP_PADS_QSPI_GPIO_SD0_PDE_BITS)
|
||||
| RP_PADS_QSPI_GPIO_SD0_PUE_BITS;
|
||||
padctrl_tmp = (padctrl_tmp & ~RP_PADS_QSPI_GPIO_SD0_PDE_BITS) | RP_PADS_QSPI_GPIO_SD0_PUE_BITS;
|
||||
|
||||
rp_spi_chip_select(t, RP_GPIO_QSPI_CS_DRIVE_LOW);
|
||||
}
|
||||
|
@ -762,9 +762,7 @@ static void rp_flash_exit_xip(target *t)
|
|||
|
||||
target_mem_write32(t, RP_PADS_QSPI_GPIO_SD0, padctrl_save);
|
||||
target_mem_write32(t, RP_PADS_QSPI_GPIO_SD1, padctrl_save);
|
||||
padctrl_save = (padctrl_save
|
||||
& ~RP_PADS_QSPI_GPIO_SD0_PDE_BITS
|
||||
) | RP_PADS_QSPI_GPIO_SD0_PUE_BITS;
|
||||
padctrl_save = (padctrl_save & ~RP_PADS_QSPI_GPIO_SD0_PDE_BITS) | RP_PADS_QSPI_GPIO_SD0_PUE_BITS;
|
||||
target_mem_write32(t, RP_PADS_QSPI_GPIO_SD2, padctrl_save);
|
||||
target_mem_write32(t, RP_PADS_QSPI_GPIO_SD3, padctrl_save);
|
||||
|
||||
|
|
Loading…
Reference in New Issue