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rp: Run clang-format

This commit is contained in:
James Turton 2022-09-16 14:45:00 +02:00 committed by Rachel Mant
parent 14882c61ab
commit bf0302b076
1 changed files with 130 additions and 132 deletions
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38
src/target/rp.c
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@ -93,15 +93,15 @@
#define RP_SSI_CTRL0_TMOD_EEPROM (3U << 8U)
#define RP_SSI_CTRL0_DATA_BIT_MASK 0x001f0000U
#define RP_SSI_CTRL0_DATA_BIT_SHIFT 16U
#define RP_SSI_CTRL0_DATA_BITS(x) (((x) - 1U) << RP_SSI_CTRL0_DATA_BIT_SHIFT)
#define RP_SSI_CTRL0_DATA_BITS(x) (((x)-1U) << RP_SSI_CTRL0_DATA_BIT_SHIFT)
#define RP_SSI_CTRL0_MASK (RP_SSI_CTRL0_FRF_MASK | RP_SSI_CTRL0_TMOD_MASK | RP_SSI_CTRL0_DATA_BIT_MASK)
#define RP_SSI_ENABLE_SSI (1U << 0U)
#define RP_SSI_XIP_SPI_CTRL0_FORMAT_STD_SPI (0U << 0U)
#define RP_SSI_XIP_SPI_CTRL0_FORMAT_SPLIT (1U << 0U)
#define RP_SSI_XIP_SPI_CTRL0_FORMAT_FRF (2U << 0U)
#define RP_SSI_XIP_SPI_CTRL0_ADDRESS_LENGTH(x) (((x) * 2U) << 2U)
#define RP_SSI_XIP_SPI_CTRL0_ADDRESS_LENGTH(x) (((x)*2U) << 2U)
#define RP_SSI_XIP_SPI_CTRL0_INSTR_LENGTH_8b (2U << 8U)
#define RP_SSI_XIP_SPI_CTRL0_WAIT_CYCLES(x) (((x) * 8U) << 11U)
#define RP_SSI_XIP_SPI_CTRL0_WAIT_CYCLES(x) (((x)*8U) << 11U)
#define RP_SSI_XIP_SPI_CTRL0_XIP_CMD_SHIFT 24U
#define RP_SSI_XIP_SPI_CTRL0_XIP_CMD(x) ((x) << RP_SSI_XIP_SPI_CTRL0_XIP_CMD_SHIFT)
#define RP_SSI_XIP_SPI_CTRL0_TRANS_1C1A (0U << 0U)
@ -142,7 +142,7 @@
#define RP_SPI_OPCODE(x) (x)
#define RP_SPI_OPCODE_MASK 0x00ffU
#define RP_SPI_INTER_SHIFT 8U
#define RP_SPI_INTER_LENGTH(x) (((x) & 7U) << RP_SPI_INTER_SHIFT)
#define RP_SPI_INTER_LENGTH(x) (((x)&7U) << RP_SPI_INTER_SHIFT)
#define RP_SPI_INTER_MASK 0x0700U
#define RP_SPI_FRAME_OPCODE_ONLY (1 << 11U)
#define RP_SPI_FRAME_OPCODE_3B_ADDR (2 << 11U)
@ -205,9 +205,9 @@ static uint32_t rp_get_flash_length(target *t);
static bool rp_mass_erase(target *t);
// Our own implementation of bootloader functions for handling flash chip
static void __attribute__((unused))rp_flash_connect_internal(target *t);
static void __attribute__((unused)) rp_flash_connect_internal(target *t);
static void rp_flash_exit_xip(target *t);
static void __attribute__((unused))rp_flash_flush_cache(target *t);
static void __attribute__((unused)) rp_flash_flush_cache(target *t);
static void rp_flash_enter_xip(target *t);
static void rp_spi_read_sfdp(target *const t, const uint32_t address, void *const buffer, const size_t length)
@ -627,7 +627,8 @@ static void rp_flash_connect_internal(target *t)
uint32_t reset = target_mem_read32(t, RP_RESETS_RESET);
target_mem_write32(t, RP_RESETS_RESET, reset | RP_RESETS_RESET_IO_QSPI_BITS | RP_RESETS_RESET_PADS_QSPI_BITS);
target_mem_write32(t, RP_RESETS_RESET, reset);
while (~target_mem_read32(t, RP_RESETS_RESET_DONE) & (RP_RESETS_RESET_IO_QSPI_BITS | RP_RESETS_RESET_PADS_QSPI_BITS));
while (
~target_mem_read32(t, RP_RESETS_RESET_DONE) & (RP_RESETS_RESET_IO_QSPI_BITS | RP_RESETS_RESET_PADS_QSPI_BITS));
// Then mux XIP block onto internal QSPI flash pads
target_mem_write32(t, RP_GPIO_QSPI_SCLK_CTRL, 0);
@ -664,7 +665,8 @@ static void rp_flash_init_spi(target *t)
// Also allow any unbounded loops to check whether the above abort condition
// was asserted, and terminate early
static int rp_flash_was_aborted(target *t) {
static int rp_flash_was_aborted(target *t)
{
return target_mem_read32(t, RP_GPIO_QSPI_SD1_CTRL) & RP_GPIO_QSPI_SD1_CTRL_INOVER_BITS;
}
@ -676,7 +678,8 @@ static int rp_flash_was_aborted(target *t) {
// If rx_skip is nonzero, this many bytes will first be consumed from the FIFO,
// before reading a further count bytes into *rx.
// E.g. if you have written a command+address just before calling this function.
static void rp_flash_put_get(target *t, const uint8_t *tx, uint8_t *rx, size_t count, size_t rx_skip) {
static void rp_flash_put_get(target *t, const uint8_t *tx, uint8_t *rx, size_t count, size_t rx_skip)
{
// Make sure there is never more data in flight than the depth of the RX
// FIFO. Otherwise, when we are interrupted for long periods, hardware
// will overflow the RX FIFO.
@ -689,7 +692,7 @@ static void rp_flash_put_get(target *t, const uint8_t *tx, uint8_t *rx, size_t c
uint32_t rx_level = target_mem_read32(t, RP_SSI_RXFLR);
bool did_something = false; // Expect this to be folded into control flow, not register
if (tx_count && tx_level + rx_level < max_in_flight) {
target_mem_write32(t, RP_SSI_DR0, (uint32_t) (tx ? *tx++ : 0));
target_mem_write32(t, RP_SSI_DR0, (uint32_t)(tx ? *tx++ : 0));
--tx_count;
did_something = true;
}
@ -728,10 +731,9 @@ static void rp_flash_exit_xip(target *t)
rp_flash_init_spi(t);
uint32_t padctrl_save = target_mem_read32(t, RP_PADS_QSPI_GPIO_SD0);
uint32_t padctrl_tmp = (padctrl_save
& ~(RP_PADS_QSPI_GPIO_SD0_OD_BITS | RP_PADS_QSPI_GPIO_SD0_PUE_BITS |
RP_PADS_QSPI_GPIO_SD0_PDE_BITS)
) | RP_PADS_QSPI_GPIO_SD0_OD_BITS | RP_PADS_QSPI_GPIO_SD0_PDE_BITS;
uint32_t padctrl_tmp = (padctrl_save & ~(RP_PADS_QSPI_GPIO_SD0_OD_BITS | RP_PADS_QSPI_GPIO_SD0_PUE_BITS |
RP_PADS_QSPI_GPIO_SD0_PDE_BITS)) |
RP_PADS_QSPI_GPIO_SD0_OD_BITS | RP_PADS_QSPI_GPIO_SD0_PDE_BITS;
// First two 32-clock sequences
// CSn is held high for the first 32 clocks, then asserted low for next 32
@ -749,9 +751,7 @@ static void rp_flash_exit_xip(target *t)
rp_flash_put_get(t, NULL, NULL, 4, 0);
padctrl_tmp = (padctrl_tmp
& ~RP_PADS_QSPI_GPIO_SD0_PDE_BITS)
| RP_PADS_QSPI_GPIO_SD0_PUE_BITS;
padctrl_tmp = (padctrl_tmp & ~RP_PADS_QSPI_GPIO_SD0_PDE_BITS) | RP_PADS_QSPI_GPIO_SD0_PUE_BITS;
rp_spi_chip_select(t, RP_GPIO_QSPI_CS_DRIVE_LOW);
}
@ -762,9 +762,7 @@ static void rp_flash_exit_xip(target *t)
target_mem_write32(t, RP_PADS_QSPI_GPIO_SD0, padctrl_save);
target_mem_write32(t, RP_PADS_QSPI_GPIO_SD1, padctrl_save);
padctrl_save = (padctrl_save
& ~RP_PADS_QSPI_GPIO_SD0_PDE_BITS
) | RP_PADS_QSPI_GPIO_SD0_PUE_BITS;
padctrl_save = (padctrl_save & ~RP_PADS_QSPI_GPIO_SD0_PDE_BITS) | RP_PADS_QSPI_GPIO_SD0_PUE_BITS;
target_mem_write32(t, RP_PADS_QSPI_GPIO_SD2, padctrl_save);
target_mem_write32(t, RP_PADS_QSPI_GPIO_SD3, padctrl_save);